mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-11 23:43:09 +00:00
562 lines
16 KiB
VHDL
562 lines
16 KiB
VHDL
---------------------------------------------------------------------------------
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-- Naughty Boy by Dar (darfpga@aol.fr)
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-- http://darfpga.blogspot.fr
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---------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.ALL;
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use ieee.numeric_std.all;
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entity naughty_boy is
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port(
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clock_12 : in std_logic;
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reset : in std_logic;
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dn_addr : in std_logic_vector(15 downto 0);
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dn_data : in std_logic_vector(7 downto 0);
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dn_wr : in std_logic;
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dip_switch : in std_logic_vector(7 downto 0);
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flip_screen : in std_logic;
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game_mod : in std_logic_vector(1 downto 0);
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coin : in std_logic;
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starts : in std_logic_vector(1 downto 0);
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player1_btns : in std_logic_vector(4 downto 0);
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player2_btns : in std_logic_vector(4 downto 0);
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video_r : out std_logic_vector(1 downto 0);
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video_g : out std_logic_vector(1 downto 0);
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video_b : out std_logic_vector(1 downto 0);
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video_csync : out std_logic;
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video_hs : out std_logic;
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video_vs : out std_logic;
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video_hblank : out std_logic;
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video_vblank : out std_logic;
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ce_pix : inout std_logic;
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audio : out std_logic_vector(11 downto 0)
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);
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end naughty_boy;
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architecture struct of naughty_boy is
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signal reset_n: std_logic;
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signal clock_12n : std_logic;
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signal hcnt : std_logic_vector(8 downto 0);
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signal hcnt_1r : std_logic;
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signal ena_pix : std_logic;
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signal vcnt : std_logic_vector(7 downto 0);
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signal hsync : std_logic;
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signal vsync : std_logic;
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signal rdy : std_logic;
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signal cpu_wait : std_logic;
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signal sel_cpu_addr : std_logic;
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signal sel_scrl_addr : std_logic;
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signal hblank : std_logic;
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signal vblank : std_logic;
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signal cpu_ena : std_logic;
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signal cpu_adr : std_logic_vector(15 downto 0);
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signal cpu_di : std_logic_vector( 7 downto 0);
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signal cpu_do : std_logic_vector( 7 downto 0);
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signal cpu_wr_n : std_logic;
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signal prog_do : std_logic_vector( 7 downto 0);
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signal wrk_ram_do : std_logic_vector( 7 downto 0);
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signal wrk_ram_we : std_logic;
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signal horz_cnt : std_logic_vector(8 downto 0) := (others =>'0');
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signal vert_cnt : std_logic_vector(7 downto 0) := (others =>'0');
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signal hcnt_s : std_logic_vector(2 downto 0) := (others =>'0');
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signal frgnd_ram_adr: std_logic_vector(10 downto 0) := (others =>'0');
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signal bkgnd_ram_adr: std_logic_vector(10 downto 0) := (others =>'0');
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signal frgnd_ram_do : std_logic_vector( 7 downto 0) := (others =>'0');
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signal bkgnd_ram_do : std_logic_vector( 7 downto 0) := (others =>'0');
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signal frgnd_ram_we : std_logic := '0';
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signal bkgnd_ram_we : std_logic := '0';
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signal frgnd_graph_adr : std_logic_vector(11 downto 0) := (others =>'0');
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signal bkgnd_graph_adr : std_logic_vector(11 downto 0) := (others =>'0');
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signal palette_adr : std_logic_vector( 7 downto 0) := (others =>'0');
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signal frgnd_tile_id : std_logic_vector(7 downto 0) := (others =>'0');
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signal bkgnd_tile_id : std_logic_vector(7 downto 0) := (others =>'0');
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signal frgnd_bit0_graph : std_logic_vector(7 downto 0) := (others =>'0');
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signal frgnd_bit1_graph : std_logic_vector(7 downto 0) := (others =>'0');
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signal bkgnd_bit0_graph : std_logic_vector(7 downto 0) := (others =>'0');
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signal bkgnd_bit1_graph : std_logic_vector(7 downto 0) := (others =>'0');
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signal fr_bit0 : std_logic;
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signal fr_bit1 : std_logic;
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signal bk_bit0 : std_logic;
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signal bk_bit1 : std_logic;
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signal fr_lin : std_logic_vector(2 downto 0);
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signal bk_lin : std_logic_vector(2 downto 0);
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signal color_set : std_logic_vector(1 downto 0);
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signal color_id : std_logic_vector(5 downto 0);
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signal rgb_0 : std_logic_vector(7 downto 0);
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signal rgb_1 : std_logic_vector(7 downto 0);
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signal graphx_bank : std_logic := '0';
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signal player2 : std_logic := '0';
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signal pl2_cocktail : std_logic := '0';
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signal bkgnd_offset : std_logic_vector(7 downto 0) := (others =>'0');
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signal sound_a : std_logic_vector(7 downto 0) := (others =>'0');
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signal sound_b : std_logic_vector(7 downto 0) := (others =>'0');
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signal sound_c : std_logic_vector(1 downto 0) := (others =>'0');
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signal tms3615_notes : std_logic_vector(11 downto 0) := (others =>'0');
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signal tms3615_clk : std_logic := '0';
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signal tms3615_octave: std_logic_vector(1 downto 0) := (others =>'0');
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signal melody : std_logic_vector(11 downto 0) := (others =>'0');
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signal snd1 : std_logic_vector( 1 downto 0) := (others =>'0');
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signal snd2 : std_logic := '0';
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signal noise : std_logic := '0';
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signal snd_C5 : std_logic_vector( 7 downto 0) := (others =>'0');
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signal snd_A5 : std_logic_vector( 7 downto 0) := (others =>'0');
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signal snd_A6 : std_logic_vector( 7 downto 0) := (others =>'0');
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signal snd_A7 : std_logic_vector( 7 downto 0) := (others =>'0');
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signal coin_n : std_logic;
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signal buttons : std_logic_vector(4 downto 0);
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signal romp_cs, rom10_cs, rom11_cs, rom20_cs, rom21_cs : std_logic;
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begin
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-- video address/sync generator
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video_gen : entity work.naughty_boy_video
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port map(
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clk12 => clock_12,
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hcnt => hcnt,
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vcnt => vcnt,
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ena_pix => ena_pix,
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hsync => video_hs,
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vsync => video_vs,
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csync => video_csync,
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cpu_wait => cpu_wait,
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hblank => hblank,
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vblank => vblank,
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sel_cpu_addr => sel_cpu_addr,
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sel_scrl_addr => sel_scrl_addr
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);
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-- misc
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clock_12n<= not clock_12;
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reset_n <= not reset;
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rdy <= not cpu_wait when (cpu_adr(15 downto 12) = "1000") else '1';
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ce_pix <= ena_pix;
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coin_n <= not coin;
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buttons <= player1_btns when player2 = '0' else player2_btns;
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-- ena_cpu
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cpu_ena <= '1' when hcnt_1r ='0' and hcnt(0) = '1' else '0';
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process (clock_12)
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begin
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if rising_edge(clock_12) then
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hcnt_1r <= hcnt(0);
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end if;
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end process;
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-- microprocessor Z80 - 1
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Z80 : entity work.T80se
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generic map(Mode => 0, T2Write => 1, IOWait => 1)
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port map(
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RESET_n => reset_n,
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CLK_n => clock_12,
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CLKEN => cpu_ena,
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WAIT_n => rdy,
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INT_n => '1',
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NMI_n => coin_n,
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BUSRQ_n => '1',
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M1_n => open,
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MREQ_n => open,
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IORQ_n => open,
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RD_n => open,
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WR_n => cpu_wr_n,
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RFSH_n => open,
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HALT_n => open,
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BUSAK_n => open,
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A => cpu_adr,
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DI => cpu_di,
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DO => cpu_do
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);
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-- mux prog, ram, vblank, switch... to processor data bus in
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cpu_di <= prog_do when cpu_adr(15 downto 14) = "00" else
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wrk_ram_do when cpu_adr(15 downto 14) = "01" else
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frgnd_ram_do when cpu_adr(15 downto 11) = "10000" else
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bkgnd_ram_do when cpu_adr(15 downto 11) = "10001" else
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not(buttons) &'0'& not(starts) when cpu_adr(15 downto 11) = "10110" else
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not(vblank) & dip_switch(6 downto 0) when cpu_adr(15 downto 11) = "10111" else
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x"FF";
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-- write enable to RAMs from cpu
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wrk_ram_we <= '1' when cpu_wr_n = '0' and cpu_adr(15 downto 14) = "01" else '0';
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frgnd_ram_we <= '1' when cpu_wr_n = '0' and cpu_adr(15) = '1' and cpu_adr(13 downto 11) = "000" and sel_cpu_addr = '1' else '0';
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bkgnd_ram_we <= '1' when cpu_wr_n = '0' and cpu_adr(15) = '1' and cpu_adr(13 downto 11) = "001" and sel_cpu_addr = '1' else '0';
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-- RAMs address mux cpu/video_generator
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frgnd_ram_adr <= cpu_adr(10 downto 0) when sel_cpu_addr ='1' else
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vert_cnt(7 downto 3) & horz_cnt(8 downto 3) when sel_scrl_addr = '1' else
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"1110" & vert_cnt(7 downto 3) & hcnt(4 downto 3) when pl2_cocktail = '0' else
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"1110" & vert_cnt(7 downto 3) & not hcnt(4 downto 3);
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bkgnd_ram_adr <= frgnd_ram_adr;
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-- demux cpu data to registers : background scrolling, sound control,
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-- player id (1/2), palette color set.
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process (clock_12)
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begin
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if rising_edge(clock_12) then
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if cpu_wr_n = '0' then
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case cpu_adr(15 downto 11) is
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when "10010" => player2 <= cpu_do(0);
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color_set <= cpu_do(2 downto 1);
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sound_c <= cpu_do(5 downto 4);
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when "10011" => bkgnd_offset <= cpu_do;
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when "10100" => sound_a <= cpu_do;
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when "10101" => sound_b <= cpu_do;
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case cpu_do(3 downto 0) is
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when x"0" => tms3615_notes <= x"001";
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when x"1" => tms3615_notes <= x"002";
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when x"2" => tms3615_notes <= x"004";
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when x"3" => tms3615_notes <= x"008";
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when x"4" => tms3615_notes <= x"010";
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when x"5" => tms3615_notes <= x"020";
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when x"6" => tms3615_notes <= x"040";
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when x"7" => tms3615_notes <= x"080";
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when x"8" => tms3615_notes <= x"100";
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when x"9" => tms3615_notes <= x"200";
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when x"A" => tms3615_notes <= x"400";
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when x"B" => tms3615_notes <= x"800";
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when x"F" => tms3615_notes <= x"000";
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when others => null;
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end case;
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case cpu_do(7 downto 6) is
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when "00" => tms3615_octave <= "00";
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when "01" => tms3615_octave <= "01";
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when "10" => tms3615_octave <= "10";
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when others => null; -- keep previous octave when "11"
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end case;
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when others => null;
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end case;
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end if;
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end if;
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end process;
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---- player2 and cocktail mode (flip horizontal/vertical)
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pl2_cocktail <= (player2 and dip_switch(7)) xor flip_screen;
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--
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---- horizontal scan video RAMs address background and foreground
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---- with flip and scroll offset
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horz_cnt <=
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('0'&hcnt(7 downto 0)) + ('0'&bkgnd_offset) when pl2_cocktail = '0'else
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('0'¬ hcnt(7 downto 0)) + ('0'&bkgnd_offset);
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---- vertical scan video RAMs address
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vert_cnt <= vcnt when pl2_cocktail = '0' else not (vcnt + X"20");
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-- get tile_ids from RAMs
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frgnd_tile_id <= frgnd_ram_do;
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bkgnd_tile_id <= bkgnd_ram_do;
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-- address graphix ROMs with tile_ids and line counter
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graphx_bank <= color_set(1);
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frgnd_graph_adr <= graphx_bank & frgnd_tile_id & vert_cnt(2 downto 0);
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bkgnd_graph_adr <= graphx_bank & bkgnd_tile_id & vert_cnt(2 downto 0);
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hcnt_s <=
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horz_cnt(2 downto 0) when sel_scrl_addr = '1' else
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hcnt(2 downto 0) when pl2_cocktail = '0' else
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not hcnt(2 downto 0);
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---- latch foreground/background next graphix byte, high bit and low bit
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---- and palette_ids (fr_lin, bklin)
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---- demux background and foreground pixel bits (0/1) from graphix byte with horizontal counter
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---- and apply blanking
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process (clock_12)
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begin
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if rising_edge(clock_12) then
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if ena_pix = '1' then
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if (hblank = '0' and vblank = '0') then
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fr_bit0 <= frgnd_bit0_graph(to_integer(unsigned(hcnt_s)));
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fr_bit1 <= frgnd_bit1_graph(to_integer(unsigned(hcnt_s)));
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bk_bit0 <= bkgnd_bit0_graph(to_integer(unsigned(hcnt_s)));
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bk_bit1 <= bkgnd_bit1_graph(to_integer(unsigned(hcnt_s)));
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else
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fr_bit0 <= '0';
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fr_bit1 <= '0';
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bk_bit0 <= '0';
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bk_bit1 <= '0';
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end if;
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fr_lin <= frgnd_tile_id(7 downto 5);
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bk_lin <= bkgnd_tile_id(7 downto 5);
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end if;
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end if;
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end process;
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---- select pixel bits and palette_id with foreground priority
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color_id <= (fr_bit0 or fr_bit1) & fr_bit1 & fr_bit0 & fr_lin when (fr_bit0 or fr_bit1) = '1' else
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(fr_bit0 or fr_bit1) & bk_bit1 & bk_bit0 & bk_lin;
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-- address palette with pixel bits color and color set
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palette_adr <= color_set & color_id;
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-- output video to top level
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video_r <= rgb_1(0) & rgb_0(0);
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video_g <= rgb_1(2) & rgb_0(2);
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video_b <= rgb_1(1) & rgb_0(1);
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video_hblank <= hblank;
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video_vblank <= vblank;
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-- download ROM CS
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romp_cs <= '1' when dn_addr(15 downto 14) = "00" else '0';
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rom10_cs <= '1' when dn_addr(15 downto 12) = "0100" else '0';
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rom11_cs <= '1' when dn_addr(15 downto 12) = "0101" else '0';
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rom20_cs <= '1' when dn_addr(15 downto 12) = "0110" else '0';
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rom21_cs <= '1' when dn_addr(15 downto 12) = "0111" else '0';
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-- foreground graphix ROM graph2 bit0
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frgnd_bit0 : entity work.dpram generic map (12,8)
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port map
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(
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clock_a => clock_12,
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wren_a => dn_wr and rom20_cs,
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address_a => dn_addr(11 downto 0),
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data_a => dn_data,
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clock_b => clock_12,
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address_b => frgnd_graph_adr,
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q_b => frgnd_bit0_graph
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);
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--frgnd_bit0 : entity work.prom_graphx_2_bit0
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--port map(
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-- clk => clock_12,
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-- addr => frgnd_graph_adr,
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-- data => frgnd_bit0_graph
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--);
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-- foreground graphix ROM graph2 bit1
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frgnd_bit1 : entity work.dpram generic map (12,8)
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port map
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(
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clock_a => clock_12,
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wren_a => dn_wr and rom21_cs,
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address_a => dn_addr(11 downto 0),
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data_a => dn_data,
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clock_b => clock_12,
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address_b => frgnd_graph_adr,
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q_b => frgnd_bit1_graph
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);
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--frgnd_bit1 : entity work.prom_graphx_2_bit1
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--port map(
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-- clk => clock_12,
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-- addr => frgnd_graph_adr,
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-- data => frgnd_bit1_graph
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--);
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-- background graphix ROM graph1 bit0
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bkgnd_bit0 : entity work.dpram generic map (12,8)
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port map
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(
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clock_a => clock_12,
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wren_a => dn_wr and rom10_cs,
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address_a => dn_addr(11 downto 0),
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data_a => dn_data,
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clock_b => clock_12,
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address_b => bkgnd_graph_adr,
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q_b => bkgnd_bit0_graph
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);
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--bkgnd_bit0 : entity work.prom_graphx_1_bit0
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--port map(
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-- clk => clock_12,
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-- addr => bkgnd_graph_adr,
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-- data => bkgnd_bit0_graph
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--);
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-- background graphix ROM graph1 bit1
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bkgnd_bit1 : entity work.dpram generic map (12,8)
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port map
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(
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clock_a => clock_12,
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wren_a => dn_wr and rom11_cs,
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address_a => dn_addr(11 downto 0),
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data_a => dn_data,
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clock_b => clock_12,
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address_b => bkgnd_graph_adr,
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q_b => bkgnd_bit1_graph
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);
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--bkgnd_bit1 : entity work.prom_graphx_1_bit1
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--port map(
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-- clk => clock_12,
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-- addr => bkgnd_graph_adr,
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-- data => bkgnd_bit1_graph
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--);
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-- color palette ROM RBG low intensity
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palette_0 : entity work.prom_palette_1
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port map(
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clk => clock_12,
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addr => palette_adr,
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data => rgb_0
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);
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-- color palette ROM RBG high intensity
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palette_1 : entity work.prom_palette_2
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port map(
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clk => clock_12,
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addr => palette_adr,
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data => rgb_1
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);
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-- Program PROM 0x0000-0x3FFF
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prog : entity work.dpram generic map (14,8)
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port map
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(
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clock_a => clock_12,
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wren_a => dn_wr and romp_cs,
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address_a => dn_addr(13 downto 0),
|
|
data_a => dn_data,
|
|
|
|
clock_b => clock_12,
|
|
address_b => cpu_adr(13 downto 0),
|
|
q_b => prog_do
|
|
);
|
|
--prog : entity work.prom_prog
|
|
--port map(
|
|
-- clk => clock_12,
|
|
-- addr => cpu_adr(13 downto 0),
|
|
-- data => prog_do
|
|
--);
|
|
|
|
-- working RAM 0x4000-0x47FF
|
|
working_ram : entity work.gen_ram
|
|
generic map( dWidth => 8, aWidth => 10)
|
|
port map(
|
|
clk => clock_12,
|
|
we => wrk_ram_we,
|
|
addr => cpu_adr(9 downto 0),
|
|
d => cpu_do,
|
|
q => wrk_ram_do
|
|
);
|
|
|
|
-- foreground RAM 0x8000-0x87FF
|
|
frgnd_ram : entity work.gen_ram
|
|
generic map( dWidth => 8, aWidth => 11)
|
|
port map(
|
|
clk => clock_12n,
|
|
we => frgnd_ram_we,
|
|
addr => frgnd_ram_adr,
|
|
d => cpu_do,
|
|
q => frgnd_ram_do
|
|
);
|
|
|
|
-- background RAM 0x8800-0x8FFF
|
|
bkgnd_ram : entity work.gen_ram
|
|
generic map( dWidth => 8, aWidth => 11)
|
|
port map(
|
|
clk => clock_12n,
|
|
we => bkgnd_ram_we,
|
|
addr => bkgnd_ram_adr,
|
|
d => cpu_do,
|
|
q => bkgnd_ram_do
|
|
);
|
|
--
|
|
---- sound effect1
|
|
effect1 : entity work.naughty_boy_effect1
|
|
port map(
|
|
clk12 => clock_12,
|
|
trigger_B54 => sound_b(5 downto 4),
|
|
snd => snd1
|
|
);
|
|
|
|
---- sound effect2
|
|
effect2 : entity work.naughty_boy_effect2
|
|
port map(
|
|
clk12 => clock_12,
|
|
clksnd => vcnt(0),
|
|
divider => sound_a(3 downto 0),
|
|
snd => snd2
|
|
);
|
|
|
|
noise_gen : entity work.naughty_boy_noise
|
|
port map(
|
|
clk12 => clock_12,
|
|
trigger => sound_a(4),
|
|
noise => noise
|
|
);
|
|
|
|
effect3 : entity work.naughty_boy_effect3
|
|
port map(
|
|
clk12 => clock_12,
|
|
trigger_C4 => sound_c(0),
|
|
trigger_C5 => sound_c(1),
|
|
trigger_A5 => sound_a(5),
|
|
noise => noise,
|
|
snd_C5 => snd_C5,
|
|
snd_A5 => snd_A5
|
|
);
|
|
|
|
effect4 : entity work.naughty_boy_effect4
|
|
port map(
|
|
clk12 => clock_12,
|
|
trigger_A6 => sound_a(6),
|
|
trigger_A7 => sound_a(7),
|
|
noise => noise,
|
|
snd_A6 => snd_A6,
|
|
snd_A7 => snd_A7
|
|
);
|
|
|
|
|
|
-- tms3615
|
|
tms3615_clk <= '0' when tms3615_octave = "11" -- could not happen
|
|
else hcnt(1) when tms3615_octave = "10"
|
|
else hcnt(2) when tms3615_octave = "01"
|
|
else hcnt(3) when tms3615_octave = "00";
|
|
|
|
tms3615ns : entity work.tms3615
|
|
port map(
|
|
clk_sys => hcnt(0),
|
|
clk_snd => tms3615_clk,
|
|
trigger => '0'&tms3615_notes,
|
|
audio => melody
|
|
);
|
|
|
|
--audio <= melody;
|
|
--audio <= "000000" & snd1 & "0000"; -- alerte monsters
|
|
--audio <= "00000" & snd2 & "000000"; -- rock hit monsters, misc jingles, ...
|
|
--audio <= "00" & snd_A5 & "00"; -- rock hit monsters
|
|
--audio <= "0000000" & snd_C5(7 downto 3) ; -- rock is flying
|
|
--audio <= "0000" & snd_A6 ; -- rock hit floor, castle fire
|
|
--audio <= "000000" & snd_A7(7 downto 2) ; -- trop fort -- boy step, castle fire
|
|
|
|
---- mix effects and music
|
|
audio <=
|
|
melody
|
|
+ ("000000" & snd1 & "0000")
|
|
+ ("00000" & snd2 & "000000")
|
|
+ ("00" & snd_A5 & "00")
|
|
+ ("0000000" & snd_C5(7 downto 3))
|
|
+ ("0000" & snd_A6)
|
|
+ ("000000" & snd_A7(7 downto 2));
|
|
|
|
end struct;
|