mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-11 23:43:09 +00:00
Naughty Boy by DAR
This commit is contained in:
Marcel
parent
9b12a8ed0a
commit
275e792b2d
31
Arcade_MiST/Jaleco NaughtyBoy/NBoy.qpf
Normal file
31
Arcade_MiST/Jaleco NaughtyBoy/NBoy.qpf
Normal file
@ -0,0 +1,31 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2016 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel MegaCore Function License Agreement, or other
|
||||
# applicable license agreement, including, without limitation,
|
||||
# that your use is for the sole purpose of programming logic
|
||||
# devices manufactured by Intel and sold by Intel or its
|
||||
# authorized distributors. Please refer to the applicable
|
||||
# agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
|
||||
# Date created = 11:17:10 October 25, 2017
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "16.1"
|
||||
DATE = "11:17:10 October 25, 2017"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "NBoy"
|
||||
240
Arcade_MiST/Jaleco NaughtyBoy/NBoy.qsf
Normal file
240
Arcade_MiST/Jaleco NaughtyBoy/NBoy.qsf
Normal file
@ -0,0 +1,240 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2014 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
# Date created = 16:13:47 September 09, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# NaughtyBoy_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_location_assignment PIN_7 -to LED
|
||||
set_location_assignment PIN_54 -to CLOCK_27
|
||||
set_location_assignment PIN_144 -to VGA_R[5]
|
||||
set_location_assignment PIN_143 -to VGA_R[4]
|
||||
set_location_assignment PIN_142 -to VGA_R[3]
|
||||
set_location_assignment PIN_141 -to VGA_R[2]
|
||||
set_location_assignment PIN_137 -to VGA_R[1]
|
||||
set_location_assignment PIN_135 -to VGA_R[0]
|
||||
set_location_assignment PIN_133 -to VGA_B[5]
|
||||
set_location_assignment PIN_132 -to VGA_B[4]
|
||||
set_location_assignment PIN_125 -to VGA_B[3]
|
||||
set_location_assignment PIN_121 -to VGA_B[2]
|
||||
set_location_assignment PIN_120 -to VGA_B[1]
|
||||
set_location_assignment PIN_115 -to VGA_B[0]
|
||||
set_location_assignment PIN_114 -to VGA_G[5]
|
||||
set_location_assignment PIN_113 -to VGA_G[4]
|
||||
set_location_assignment PIN_112 -to VGA_G[3]
|
||||
set_location_assignment PIN_111 -to VGA_G[2]
|
||||
set_location_assignment PIN_110 -to VGA_G[1]
|
||||
set_location_assignment PIN_106 -to VGA_G[0]
|
||||
set_location_assignment PIN_136 -to VGA_VS
|
||||
set_location_assignment PIN_119 -to VGA_HS
|
||||
set_location_assignment PIN_65 -to AUDIO_L
|
||||
set_location_assignment PIN_80 -to AUDIO_R
|
||||
set_location_assignment PIN_105 -to SPI_DO
|
||||
set_location_assignment PIN_88 -to SPI_DI
|
||||
set_location_assignment PIN_126 -to SPI_SCK
|
||||
set_location_assignment PIN_91 -to SPI_SS3
|
||||
set_location_assignment PIN_13 -to CONF_DATA0
|
||||
set_location_assignment PIN_49 -to SDRAM_A[0]
|
||||
set_location_assignment PIN_44 -to SDRAM_A[1]
|
||||
set_location_assignment PIN_42 -to SDRAM_A[2]
|
||||
set_location_assignment PIN_39 -to SDRAM_A[3]
|
||||
set_location_assignment PIN_4 -to SDRAM_A[4]
|
||||
set_location_assignment PIN_6 -to SDRAM_A[5]
|
||||
set_location_assignment PIN_8 -to SDRAM_A[6]
|
||||
set_location_assignment PIN_10 -to SDRAM_A[7]
|
||||
set_location_assignment PIN_11 -to SDRAM_A[8]
|
||||
set_location_assignment PIN_28 -to SDRAM_A[9]
|
||||
set_location_assignment PIN_50 -to SDRAM_A[10]
|
||||
set_location_assignment PIN_30 -to SDRAM_A[11]
|
||||
set_location_assignment PIN_32 -to SDRAM_A[12]
|
||||
set_location_assignment PIN_83 -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_79 -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_77 -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_76 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_72 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_71 -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_69 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_68 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_86 -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_87 -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_98 -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_99 -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_100 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_101 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_103 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_104 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_58 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_51 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_85 -to SDRAM_DQMH
|
||||
set_location_assignment PIN_67 -to SDRAM_DQML
|
||||
set_location_assignment PIN_60 -to SDRAM_nRAS
|
||||
set_location_assignment PIN_64 -to SDRAM_nCAS
|
||||
set_location_assignment PIN_66 -to SDRAM_nWE
|
||||
set_location_assignment PIN_59 -to SDRAM_nCS
|
||||
set_location_assignment PIN_33 -to SDRAM_CKE
|
||||
set_location_assignment PIN_43 -to SDRAM_CLK
|
||||
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
|
||||
|
||||
|
||||
|
||||
# Classic Timing Assignments
|
||||
# ==========================
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY naughty_boy_mist
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
|
||||
set_global_assignment -name ENABLE_NCE_PIN OFF
|
||||
|
||||
# EDA Netlist Writer Assignments
|
||||
# ==============================
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
|
||||
# SignalTap II Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
|
||||
|
||||
# Power Estimation Assignments
|
||||
# ============================
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
# Advanced I/O Timing Assignments
|
||||
# ===============================
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
|
||||
# -------------------------
|
||||
# start ENTITY(pooyan_mist)
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
# end ENTITY(pooyan_mist)
|
||||
# -----------------------
|
||||
set_location_assignment PIN_127 -to SPI_SS2
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/naughty_boy_mist.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/naughty_boy.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/naughty_boy_video.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/naughty_boy_noise.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/naughty_boy_effect4.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/naughty_boy_effect3.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/naughty_boy_effect2.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/naughty_boy_effect1.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/prom_palette_1.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/prom_palette_2.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/tms3615.vhd
|
||||
set_global_assignment -name VERILOG_FILE rtl/pll.v
|
||||
set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
|
||||
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
63
Arcade_MiST/Jaleco NaughtyBoy/README.txt
Normal file
63
Arcade_MiST/Jaleco NaughtyBoy/README.txt
Normal file
@ -0,0 +1,63 @@
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
-- Naughty Boy FPGA - DAR - 2025 - WIP
|
||||
-- http://darfpga.blogspot.fr
|
||||
-- darfpga : GitHub, sourceforge
|
||||
---------------------------------------------------------------------------------
|
||||
--
|
||||
-- Support screen and controls rotation on HDMI output.
|
||||
-- Only controls are rotated on VGA output.
|
||||
--
|
||||
--
|
||||
-- Keyboard inputs :
|
||||
--
|
||||
-- F3 : Add coin
|
||||
-- F2 : Start 2 players
|
||||
-- F1 : Start 1 player
|
||||
-- SPACE : Fire
|
||||
-- UP/RIGHT : Move up
|
||||
-- DOWN/LEFT : Move down
|
||||
--
|
||||
-- MAME/IPAC/JPAC Style Keyboard inputs:
|
||||
-- 5 : Coin 1
|
||||
-- 6 : Coin 2
|
||||
-- 1 : Start 1 Player
|
||||
-- 2 : Start 2 Players
|
||||
-- D,G : Player 2 Movements
|
||||
-- A : Player 2 Fire
|
||||
--
|
||||
-- Joystick support.
|
||||
--
|
||||
--
|
||||
----------------------------------------------
|
||||
|
||||
Hiscore save/load: TODO
|
||||
|
||||
Save and load of hiscores is supported for this core:
|
||||
|
||||
To save your hiscores manually, press the 'Save Settings' option in the OSD. Hiscores will be automatically loaded when the core is started.
|
||||
|
||||
To enable automatic saving of hiscores, turn on the 'Autosave Hiscores' option, press the 'Save Settings' option in the OSD, and reload the core. Hiscores will then be automatically saved (if they have changed) any time the OSD is opened.
|
||||
|
||||
Hiscore data is stored in /media/fat/config/nvram/ as ```<mra filename>.nvm```
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
*** Attention ***
|
||||
|
||||
ROMs are not included. In order to use this arcade, you need to provide the
|
||||
correct ROMs.
|
||||
|
||||
To simplify the process .mra files are provided in the releases folder, that
|
||||
specifies the required ROMs with checksums. The ROMs .zip filename refers to the
|
||||
corresponding file of the M.A.M.E. project.
|
||||
|
||||
Please refer to https://github.com/MiSTer-devel/Main_MiSTer/wiki/Arcade-Roms for
|
||||
information on how to setup and use the environment.
|
||||
|
||||
Quickreference for folders and file placement:
|
||||
|
||||
/_Arcade/<game name>.mra
|
||||
/_Arcade/cores/<game rbf>.rbf
|
||||
/_Arcade/mame/<mame rom>.zip
|
||||
/_Arcade/hbmame/<hbmame rom>.zip
|
||||
15
Arcade_MiST/Jaleco NaughtyBoy/clean.bat
Normal file
15
Arcade_MiST/Jaleco NaughtyBoy/clean.bat
Normal file
@ -0,0 +1,15 @@
|
||||
@echo off
|
||||
del /s *.bak
|
||||
del /s *.orig
|
||||
del /s *.rej
|
||||
rmdir /s /q db
|
||||
rmdir /s /q incremental_db
|
||||
rmdir /s /q output_files
|
||||
rmdir /s /q simulation
|
||||
rmdir /s /q greybox_tmp
|
||||
del PLLJ_PLLSPE_INFO.txt
|
||||
del *.qws
|
||||
del *.ppf
|
||||
del *.qip
|
||||
del *.ddb
|
||||
pause
|
||||
36
Arcade_MiST/Jaleco NaughtyBoy/meta/NBoy.mra
Normal file
36
Arcade_MiST/Jaleco NaughtyBoy/meta/NBoy.mra
Normal file
@ -0,0 +1,36 @@
|
||||
<misterromdescription>
|
||||
<name>NBoy</name>
|
||||
<mratimestamp>20250316000000</mratimestamp>
|
||||
<mameversion>0217</mameversion>
|
||||
<year>1982</year>
|
||||
<manufacturer>Jaleco</manufacturer>
|
||||
<category>Shooter - Gallery</category>
|
||||
<rbf>NBoy</rbf>
|
||||
|
||||
<rom index="1"></rom>
|
||||
<rom index='0' md5='8dbe444fd490d709c29e618340fcca0c' type='merged|nonmerged|split' zip='naughtyb.zip'>
|
||||
<part crc="f6e1178e" name="1.30"></part>
|
||||
<part crc="b803eb8c" name="2.29"></part>
|
||||
<part crc="004d0ba7" name="3.28"></part>
|
||||
<part crc="3c7bcac6" name="4.27"></part>
|
||||
<part crc="ea80f39b" name="5.26"></part>
|
||||
<part crc="66d9f942" name="6.25"></part>
|
||||
<part crc="00caf9be" name="7.24"></part>
|
||||
<part crc="17c3b6fb" name="8.23"></part>
|
||||
|
||||
<part crc="d692f9c7" name="15.44"></part>
|
||||
<part crc="d3ba8b27" name="16.43"></part>
|
||||
<part crc="c1669cd5" name="13.46"></part>
|
||||
<part crc="eef2c8e5" name="14.45"></part>
|
||||
|
||||
<part crc="75ec9710" name="11.48"></part>
|
||||
<part crc="ef0706c3" name="12.47"></part>
|
||||
<part crc="8c8db764" name="9.50"></part>
|
||||
<part crc="c97c97b9" name="10.49"></part>
|
||||
</rom>
|
||||
<rom index="2"></rom>
|
||||
<rom index="3"></rom>
|
||||
<rom index="4"></rom>
|
||||
|
||||
<nvram index="4" size="27"></nvram>
|
||||
</misterromdescription>
|
||||
24
Arcade_MiST/Jaleco NaughtyBoy/meta/NotWorking/TriviaM.mra
Normal file
24
Arcade_MiST/Jaleco NaughtyBoy/meta/NotWorking/TriviaM.mra
Normal file
@ -0,0 +1,24 @@
|
||||
<misterromdescription>
|
||||
<name>TriviaM</name>
|
||||
<mratimestamp>20250316000000</mratimestamp>
|
||||
<mameversion>0217</mameversion>
|
||||
<year>1985</year>
|
||||
<manufacturer>Enerdyne Technologies Inc.</manufacturer>
|
||||
<category>Trivia</category>
|
||||
<rbf>NBoy</rbf>
|
||||
|
||||
<rom index="1"></rom>
|
||||
<rom index='0' md5='31f41f483f5977d24385d13a3eaca4d1' type='merged|nonmerged|split' zip='trvmstr.zip'>
|
||||
<part crc="4ccd0537" name="ic30.bin"></part>
|
||||
<part crc="782a2b8c" name="ic28.bin"></part>
|
||||
<part crc="1362010a" name="ic26.bin"></part>
|
||||
<part crc="1362010a" name="ic26.bin"></part>
|
||||
|
||||
|
||||
<part crc="dac8cff7" name="ic44.bin"></part>
|
||||
<part crc="a97ab879" name="ic46.bin"></part>
|
||||
|
||||
<part crc="79952015" name="ic48.bin"></part>
|
||||
<part crc="f09da428" name="ic50.bin"></part>
|
||||
</rom>
|
||||
</misterromdescription>
|
||||
25
Arcade_MiST/Jaleco NaughtyBoy/meta/PopF.mra
Normal file
25
Arcade_MiST/Jaleco NaughtyBoy/meta/PopF.mra
Normal file
@ -0,0 +1,25 @@
|
||||
<misterromdescription>
|
||||
<name>PopF</name>
|
||||
<mratimestamp>20250316000000</mratimestamp>
|
||||
<mameversion>0217</mameversion>
|
||||
<year>1982</year>
|
||||
<manufacturer>Jaleco</manufacturer>
|
||||
<category>Shooter - Gallery</category>
|
||||
<rbf>NBoy</rbf>
|
||||
|
||||
<rom index="1"></rom>
|
||||
<rom index='0' md5='fdc3e6937e974389705145449ec71d2c' type='merged|nonmerged|split' zip='popflame.zip | popflamea.zip'>
|
||||
<part crc="5e32bbdf" name="ic86.pop"></part>
|
||||
<part crc="b77abf3d" name="ic80.pop"></part>
|
||||
<part crc="945a3c0f" name="ic94.pop"></part>
|
||||
<part crc="f9f2343b" name="ic100.pop"></part>
|
||||
|
||||
|
||||
<part crc="2367131e" name="ic13.pop"></part>
|
||||
<part crc="deed0a8b" name="ic3.pop"></part>
|
||||
|
||||
<part crc="7b54f60f" name="ic29.pop"></part>
|
||||
<part crc="dd2d9601" name="ic38.pop"></part>
|
||||
</rom>
|
||||
|
||||
</misterromdescription>
|
||||
35
Arcade_MiST/Jaleco NaughtyBoy/rtl/build_id.tcl
Normal file
35
Arcade_MiST/Jaleco NaughtyBoy/rtl/build_id.tcl
Normal file
@ -0,0 +1,35 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
|
||||
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "rtl/build_id.v"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
# Output the Verilog source
|
||||
puts $outputFile "`define BUILD_DATE \"$buildDate\""
|
||||
puts $outputFile "`define BUILD_TIME \"$buildTime\""
|
||||
close $outputFile
|
||||
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
|
||||
post_message "Date: $buildDate"
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
75
Arcade_MiST/Jaleco NaughtyBoy/rtl/dpram.vhd
Normal file
75
Arcade_MiST/Jaleco NaughtyBoy/rtl/dpram.vhd
Normal file
@ -0,0 +1,75 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.altera_mf_components.all;
|
||||
|
||||
entity dpram is
|
||||
generic (
|
||||
addr_width_g : integer := 8;
|
||||
data_width_g : integer := 8
|
||||
);
|
||||
PORT
|
||||
(
|
||||
address_a : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
|
||||
address_b : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
|
||||
clock_a : IN STD_LOGIC := '1';
|
||||
clock_b : IN STD_LOGIC ;
|
||||
data_a : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
|
||||
data_b : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0) := (others => '0');
|
||||
enable_a : IN STD_LOGIC := '1';
|
||||
enable_b : IN STD_LOGIC := '1';
|
||||
wren_a : IN STD_LOGIC := '0';
|
||||
wren_b : IN STD_LOGIC := '0';
|
||||
q_a : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
|
||||
q_b : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
|
||||
);
|
||||
END dpram;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF dpram IS
|
||||
BEGIN
|
||||
altsyncram_component : altsyncram
|
||||
GENERIC MAP (
|
||||
-- address_reg_b => "CLOCK1",
|
||||
clock_enable_input_a => "NORMAL",
|
||||
clock_enable_input_b => "NORMAL",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
clock_enable_output_b => "BYPASS",
|
||||
-- indata_reg_b => "CLOCK1",
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 2**addr_width_g,
|
||||
numwords_b => 2**addr_width_g,
|
||||
operation_mode => "BIDIR_DUAL_PORT",
|
||||
outdata_aclr_a => "NONE",
|
||||
outdata_aclr_b => "NONE",
|
||||
outdata_reg_a => "UNREGISTERED",
|
||||
outdata_reg_b => "UNREGISTERED",
|
||||
power_up_uninitialized => "FALSE",
|
||||
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
|
||||
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
|
||||
widthad_a => addr_width_g,
|
||||
widthad_b => addr_width_g,
|
||||
width_a => data_width_g,
|
||||
width_b => data_width_g,
|
||||
width_byteena_a => 1,
|
||||
width_byteena_b => 1
|
||||
-- wrcontrol_wraddress_reg_b => "CLOCK1"
|
||||
)
|
||||
PORT MAP (
|
||||
address_a => address_a,
|
||||
address_b => address_b,
|
||||
clock0 => clock_a,
|
||||
clock1 => clock_b,
|
||||
clocken0 => enable_a,
|
||||
clocken1 => enable_b,
|
||||
data_a => data_a,
|
||||
data_b => data_b,
|
||||
wren_a => wren_a,
|
||||
wren_b => wren_b,
|
||||
q_a => q_a,
|
||||
q_b => q_b
|
||||
);
|
||||
|
||||
END SYN;
|
||||
82
Arcade_MiST/Jaleco NaughtyBoy/rtl/gen_ram.vhd
Normal file
82
Arcade_MiST/Jaleco NaughtyBoy/rtl/gen_ram.vhd
Normal file
@ -0,0 +1,82 @@
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- Syntiac's generic VHDL support files.
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
|
||||
-- http://www.syntiac.com/fpga64.html
|
||||
--
|
||||
-- Modified April 2016 by Dar (darfpga@aol.fr)
|
||||
-- http://darfpga.blogspot.fr
|
||||
-- Remove address register when writing
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- gen_rwram.vhd
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
--
|
||||
-- generic ram.
|
||||
--
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
entity gen_ram is
|
||||
generic (
|
||||
dWidth : integer := 8;
|
||||
aWidth : integer := 10
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
we : in std_logic;
|
||||
addr : in std_logic_vector((aWidth-1) downto 0);
|
||||
d : in std_logic_vector((dWidth-1) downto 0);
|
||||
q : out std_logic_vector((dWidth-1) downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
|
||||
architecture rtl of gen_ram is
|
||||
subtype addressRange is integer range 0 to ((2**aWidth)-1);
|
||||
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
|
||||
signal ram: ramDef;
|
||||
|
||||
signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
|
||||
signal qReg : std_logic_vector((dWidth-1) downto 0);
|
||||
begin
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Signals to entity interface
|
||||
-- -----------------------------------------------------------------------
|
||||
q <= qReg;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Memory write
|
||||
-- -----------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if we = '1' then
|
||||
ram(to_integer(unsigned(addr))) <= d;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- -----------------------------------------------------------------------
|
||||
-- Memory read
|
||||
-- -----------------------------------------------------------------------
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
-- qReg <= ram(to_integer(unsigned(rAddrReg)));
|
||||
-- rAddrReg <= addr;
|
||||
qReg <= ram(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
|
||||
561
Arcade_MiST/Jaleco NaughtyBoy/rtl/naughty_boy.vhd
Normal file
561
Arcade_MiST/Jaleco NaughtyBoy/rtl/naughty_boy.vhd
Normal file
@ -0,0 +1,561 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Naughty Boy by Dar (darfpga@aol.fr)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity naughty_boy is
|
||||
port(
|
||||
clock_12 : in std_logic;
|
||||
reset : in std_logic;
|
||||
|
||||
dn_addr : in std_logic_vector(15 downto 0);
|
||||
dn_data : in std_logic_vector(7 downto 0);
|
||||
dn_wr : in std_logic;
|
||||
|
||||
dip_switch : in std_logic_vector(7 downto 0);
|
||||
flip_screen : in std_logic;
|
||||
game_mod : in std_logic_vector(1 downto 0);
|
||||
coin : in std_logic;
|
||||
starts : in std_logic_vector(1 downto 0);
|
||||
player1_btns : in std_logic_vector(4 downto 0);
|
||||
player2_btns : in std_logic_vector(4 downto 0);
|
||||
video_r : out std_logic_vector(1 downto 0);
|
||||
video_g : out std_logic_vector(1 downto 0);
|
||||
video_b : out std_logic_vector(1 downto 0);
|
||||
video_csync : out std_logic;
|
||||
video_hs : out std_logic;
|
||||
video_vs : out std_logic;
|
||||
video_hblank : out std_logic;
|
||||
video_vblank : out std_logic;
|
||||
ce_pix : inout std_logic;
|
||||
audio : out std_logic_vector(11 downto 0)
|
||||
);
|
||||
end naughty_boy;
|
||||
|
||||
architecture struct of naughty_boy is
|
||||
|
||||
signal reset_n: std_logic;
|
||||
|
||||
signal clock_12n : std_logic;
|
||||
signal hcnt : std_logic_vector(8 downto 0);
|
||||
signal hcnt_1r : std_logic;
|
||||
signal ena_pix : std_logic;
|
||||
signal vcnt : std_logic_vector(7 downto 0);
|
||||
signal hsync : std_logic;
|
||||
signal vsync : std_logic;
|
||||
|
||||
signal rdy : std_logic;
|
||||
signal cpu_wait : std_logic;
|
||||
signal sel_cpu_addr : std_logic;
|
||||
signal sel_scrl_addr : std_logic;
|
||||
signal hblank : std_logic;
|
||||
signal vblank : std_logic;
|
||||
|
||||
signal cpu_ena : std_logic;
|
||||
signal cpu_adr : std_logic_vector(15 downto 0);
|
||||
signal cpu_di : std_logic_vector( 7 downto 0);
|
||||
signal cpu_do : std_logic_vector( 7 downto 0);
|
||||
signal cpu_wr_n : std_logic;
|
||||
signal prog_do : std_logic_vector( 7 downto 0);
|
||||
|
||||
signal wrk_ram_do : std_logic_vector( 7 downto 0);
|
||||
signal wrk_ram_we : std_logic;
|
||||
|
||||
signal horz_cnt : std_logic_vector(8 downto 0) := (others =>'0');
|
||||
signal vert_cnt : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal hcnt_s : std_logic_vector(2 downto 0) := (others =>'0');
|
||||
|
||||
signal frgnd_ram_adr: std_logic_vector(10 downto 0) := (others =>'0');
|
||||
signal bkgnd_ram_adr: std_logic_vector(10 downto 0) := (others =>'0');
|
||||
signal frgnd_ram_do : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
signal bkgnd_ram_do : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
signal frgnd_ram_we : std_logic := '0';
|
||||
signal bkgnd_ram_we : std_logic := '0';
|
||||
|
||||
signal frgnd_graph_adr : std_logic_vector(11 downto 0) := (others =>'0');
|
||||
signal bkgnd_graph_adr : std_logic_vector(11 downto 0) := (others =>'0');
|
||||
signal palette_adr : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
|
||||
signal frgnd_tile_id : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal bkgnd_tile_id : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
|
||||
signal frgnd_bit0_graph : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal frgnd_bit1_graph : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal bkgnd_bit0_graph : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal bkgnd_bit1_graph : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
|
||||
signal fr_bit0 : std_logic;
|
||||
signal fr_bit1 : std_logic;
|
||||
signal bk_bit0 : std_logic;
|
||||
signal bk_bit1 : std_logic;
|
||||
signal fr_lin : std_logic_vector(2 downto 0);
|
||||
signal bk_lin : std_logic_vector(2 downto 0);
|
||||
|
||||
signal color_set : std_logic_vector(1 downto 0);
|
||||
signal color_id : std_logic_vector(5 downto 0);
|
||||
signal rgb_0 : std_logic_vector(7 downto 0);
|
||||
signal rgb_1 : std_logic_vector(7 downto 0);
|
||||
|
||||
signal graphx_bank : std_logic := '0';
|
||||
signal player2 : std_logic := '0';
|
||||
signal pl2_cocktail : std_logic := '0';
|
||||
signal bkgnd_offset : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal sound_a : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal sound_b : std_logic_vector(7 downto 0) := (others =>'0');
|
||||
signal sound_c : std_logic_vector(1 downto 0) := (others =>'0');
|
||||
|
||||
signal tms3615_notes : std_logic_vector(11 downto 0) := (others =>'0');
|
||||
signal tms3615_clk : std_logic := '0';
|
||||
signal tms3615_octave: std_logic_vector(1 downto 0) := (others =>'0');
|
||||
|
||||
signal melody : std_logic_vector(11 downto 0) := (others =>'0');
|
||||
signal snd1 : std_logic_vector( 1 downto 0) := (others =>'0');
|
||||
signal snd2 : std_logic := '0';
|
||||
signal noise : std_logic := '0';
|
||||
signal snd_C5 : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
signal snd_A5 : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
signal snd_A6 : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
signal snd_A7 : std_logic_vector( 7 downto 0) := (others =>'0');
|
||||
|
||||
signal coin_n : std_logic;
|
||||
signal buttons : std_logic_vector(4 downto 0);
|
||||
|
||||
signal romp_cs, rom10_cs, rom11_cs, rom20_cs, rom21_cs : std_logic;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-- video address/sync generator
|
||||
video_gen : entity work.naughty_boy_video
|
||||
port map(
|
||||
clk12 => clock_12,
|
||||
hcnt => hcnt,
|
||||
vcnt => vcnt,
|
||||
ena_pix => ena_pix,
|
||||
hsync => video_hs,
|
||||
vsync => video_vs,
|
||||
csync => video_csync,
|
||||
cpu_wait => cpu_wait,
|
||||
hblank => hblank,
|
||||
vblank => vblank,
|
||||
sel_cpu_addr => sel_cpu_addr,
|
||||
sel_scrl_addr => sel_scrl_addr
|
||||
);
|
||||
|
||||
-- misc
|
||||
clock_12n<= not clock_12;
|
||||
reset_n <= not reset;
|
||||
rdy <= not cpu_wait when (cpu_adr(15 downto 12) = "1000") else '1';
|
||||
ce_pix <= ena_pix;
|
||||
|
||||
|
||||
coin_n <= not coin;
|
||||
buttons <= player1_btns when player2 = '0' else player2_btns;
|
||||
|
||||
-- ena_cpu
|
||||
cpu_ena <= '1' when hcnt_1r ='0' and hcnt(0) = '1' else '0';
|
||||
|
||||
process (clock_12)
|
||||
begin
|
||||
if rising_edge(clock_12) then
|
||||
hcnt_1r <= hcnt(0);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- microprocessor Z80 - 1
|
||||
Z80 : entity work.T80se
|
||||
generic map(Mode => 0, T2Write => 1, IOWait => 1)
|
||||
port map(
|
||||
RESET_n => reset_n,
|
||||
CLK_n => clock_12,
|
||||
CLKEN => cpu_ena,
|
||||
WAIT_n => rdy,
|
||||
INT_n => '1',
|
||||
NMI_n => coin_n,
|
||||
BUSRQ_n => '1',
|
||||
M1_n => open,
|
||||
MREQ_n => open,
|
||||
IORQ_n => open,
|
||||
RD_n => open,
|
||||
WR_n => cpu_wr_n,
|
||||
RFSH_n => open,
|
||||
HALT_n => open,
|
||||
BUSAK_n => open,
|
||||
A => cpu_adr,
|
||||
DI => cpu_di,
|
||||
DO => cpu_do
|
||||
);
|
||||
|
||||
-- mux prog, ram, vblank, switch... to processor data bus in
|
||||
cpu_di <= prog_do when cpu_adr(15 downto 14) = "00" else
|
||||
wrk_ram_do when cpu_adr(15 downto 14) = "01" else
|
||||
frgnd_ram_do when cpu_adr(15 downto 11) = "10000" else
|
||||
bkgnd_ram_do when cpu_adr(15 downto 11) = "10001" else
|
||||
not(buttons) &'0'& not(starts) when cpu_adr(15 downto 11) = "10110" else
|
||||
not(vblank) & dip_switch(6 downto 0) when cpu_adr(15 downto 11) = "10111" else
|
||||
x"FF";
|
||||
|
||||
-- write enable to RAMs from cpu
|
||||
wrk_ram_we <= '1' when cpu_wr_n = '0' and cpu_adr(15 downto 14) = "01" else '0';
|
||||
frgnd_ram_we <= '1' when cpu_wr_n = '0' and cpu_adr(15) = '1' and cpu_adr(13 downto 11) = "000" and sel_cpu_addr = '1' else '0';
|
||||
bkgnd_ram_we <= '1' when cpu_wr_n = '0' and cpu_adr(15) = '1' and cpu_adr(13 downto 11) = "001" and sel_cpu_addr = '1' else '0';
|
||||
|
||||
-- RAMs address mux cpu/video_generator
|
||||
frgnd_ram_adr <= cpu_adr(10 downto 0) when sel_cpu_addr ='1' else
|
||||
vert_cnt(7 downto 3) & horz_cnt(8 downto 3) when sel_scrl_addr = '1' else
|
||||
"1110" & vert_cnt(7 downto 3) & hcnt(4 downto 3) when pl2_cocktail = '0' else
|
||||
"1110" & vert_cnt(7 downto 3) & not hcnt(4 downto 3);
|
||||
|
||||
bkgnd_ram_adr <= frgnd_ram_adr;
|
||||
|
||||
-- demux cpu data to registers : background scrolling, sound control,
|
||||
-- player id (1/2), palette color set.
|
||||
process (clock_12)
|
||||
begin
|
||||
if rising_edge(clock_12) then
|
||||
if cpu_wr_n = '0' then
|
||||
case cpu_adr(15 downto 11) is
|
||||
when "10010" => player2 <= cpu_do(0);
|
||||
color_set <= cpu_do(2 downto 1);
|
||||
sound_c <= cpu_do(5 downto 4);
|
||||
when "10011" => bkgnd_offset <= cpu_do;
|
||||
when "10100" => sound_a <= cpu_do;
|
||||
when "10101" => sound_b <= cpu_do;
|
||||
|
||||
case cpu_do(3 downto 0) is
|
||||
when x"0" => tms3615_notes <= x"001";
|
||||
when x"1" => tms3615_notes <= x"002";
|
||||
when x"2" => tms3615_notes <= x"004";
|
||||
when x"3" => tms3615_notes <= x"008";
|
||||
when x"4" => tms3615_notes <= x"010";
|
||||
when x"5" => tms3615_notes <= x"020";
|
||||
when x"6" => tms3615_notes <= x"040";
|
||||
when x"7" => tms3615_notes <= x"080";
|
||||
when x"8" => tms3615_notes <= x"100";
|
||||
when x"9" => tms3615_notes <= x"200";
|
||||
when x"A" => tms3615_notes <= x"400";
|
||||
when x"B" => tms3615_notes <= x"800";
|
||||
when x"F" => tms3615_notes <= x"000";
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
case cpu_do(7 downto 6) is
|
||||
when "00" => tms3615_octave <= "00";
|
||||
when "01" => tms3615_octave <= "01";
|
||||
when "10" => tms3615_octave <= "10";
|
||||
when others => null; -- keep previous octave when "11"
|
||||
end case;
|
||||
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---- player2 and cocktail mode (flip horizontal/vertical)
|
||||
pl2_cocktail <= (player2 and dip_switch(7)) xor flip_screen;
|
||||
--
|
||||
---- horizontal scan video RAMs address background and foreground
|
||||
---- with flip and scroll offset
|
||||
horz_cnt <=
|
||||
('0'&hcnt(7 downto 0)) + ('0'&bkgnd_offset) when pl2_cocktail = '0'else
|
||||
('0'¬ hcnt(7 downto 0)) + ('0'&bkgnd_offset);
|
||||
|
||||
---- vertical scan video RAMs address
|
||||
vert_cnt <= vcnt when pl2_cocktail = '0' else not (vcnt + X"20");
|
||||
|
||||
-- get tile_ids from RAMs
|
||||
frgnd_tile_id <= frgnd_ram_do;
|
||||
bkgnd_tile_id <= bkgnd_ram_do;
|
||||
|
||||
-- address graphix ROMs with tile_ids and line counter
|
||||
graphx_bank <= color_set(1);
|
||||
frgnd_graph_adr <= graphx_bank & frgnd_tile_id & vert_cnt(2 downto 0);
|
||||
bkgnd_graph_adr <= graphx_bank & bkgnd_tile_id & vert_cnt(2 downto 0);
|
||||
|
||||
hcnt_s <=
|
||||
horz_cnt(2 downto 0) when sel_scrl_addr = '1' else
|
||||
hcnt(2 downto 0) when pl2_cocktail = '0' else
|
||||
not hcnt(2 downto 0);
|
||||
|
||||
---- latch foreground/background next graphix byte, high bit and low bit
|
||||
---- and palette_ids (fr_lin, bklin)
|
||||
---- demux background and foreground pixel bits (0/1) from graphix byte with horizontal counter
|
||||
---- and apply blanking
|
||||
process (clock_12)
|
||||
begin
|
||||
if rising_edge(clock_12) then
|
||||
if ena_pix = '1' then
|
||||
if (hblank = '0' and vblank = '0') then
|
||||
fr_bit0 <= frgnd_bit0_graph(to_integer(unsigned(hcnt_s)));
|
||||
fr_bit1 <= frgnd_bit1_graph(to_integer(unsigned(hcnt_s)));
|
||||
bk_bit0 <= bkgnd_bit0_graph(to_integer(unsigned(hcnt_s)));
|
||||
bk_bit1 <= bkgnd_bit1_graph(to_integer(unsigned(hcnt_s)));
|
||||
else
|
||||
fr_bit0 <= '0';
|
||||
fr_bit1 <= '0';
|
||||
bk_bit0 <= '0';
|
||||
bk_bit1 <= '0';
|
||||
end if;
|
||||
fr_lin <= frgnd_tile_id(7 downto 5);
|
||||
bk_lin <= bkgnd_tile_id(7 downto 5);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
---- select pixel bits and palette_id with foreground priority
|
||||
color_id <= (fr_bit0 or fr_bit1) & fr_bit1 & fr_bit0 & fr_lin when (fr_bit0 or fr_bit1) = '1' else
|
||||
(fr_bit0 or fr_bit1) & bk_bit1 & bk_bit0 & bk_lin;
|
||||
|
||||
-- address palette with pixel bits color and color set
|
||||
palette_adr <= color_set & color_id;
|
||||
|
||||
-- output video to top level
|
||||
video_r <= rgb_1(0) & rgb_0(0);
|
||||
video_g <= rgb_1(2) & rgb_0(2);
|
||||
video_b <= rgb_1(1) & rgb_0(1);
|
||||
|
||||
video_hblank <= hblank;
|
||||
video_vblank <= vblank;
|
||||
|
||||
-- download ROM CS
|
||||
romp_cs <= '1' when dn_addr(15 downto 14) = "00" else '0';
|
||||
rom10_cs <= '1' when dn_addr(15 downto 12) = "0100" else '0';
|
||||
rom11_cs <= '1' when dn_addr(15 downto 12) = "0101" else '0';
|
||||
rom20_cs <= '1' when dn_addr(15 downto 12) = "0110" else '0';
|
||||
rom21_cs <= '1' when dn_addr(15 downto 12) = "0111" else '0';
|
||||
|
||||
-- foreground graphix ROM graph2 bit0
|
||||
frgnd_bit0 : entity work.dpram generic map (12,8)
|
||||
port map
|
||||
(
|
||||
clock_a => clock_12,
|
||||
wren_a => dn_wr and rom20_cs,
|
||||
address_a => dn_addr(11 downto 0),
|
||||
data_a => dn_data,
|
||||
|
||||
clock_b => clock_12,
|
||||
address_b => frgnd_graph_adr,
|
||||
q_b => frgnd_bit0_graph
|
||||
);
|
||||
--frgnd_bit0 : entity work.prom_graphx_2_bit0
|
||||
--port map(
|
||||
-- clk => clock_12,
|
||||
-- addr => frgnd_graph_adr,
|
||||
-- data => frgnd_bit0_graph
|
||||
--);
|
||||
|
||||
-- foreground graphix ROM graph2 bit1
|
||||
frgnd_bit1 : entity work.dpram generic map (12,8)
|
||||
port map
|
||||
(
|
||||
clock_a => clock_12,
|
||||
wren_a => dn_wr and rom21_cs,
|
||||
address_a => dn_addr(11 downto 0),
|
||||
data_a => dn_data,
|
||||
|
||||
clock_b => clock_12,
|
||||
address_b => frgnd_graph_adr,
|
||||
q_b => frgnd_bit1_graph
|
||||
);
|
||||
--frgnd_bit1 : entity work.prom_graphx_2_bit1
|
||||
--port map(
|
||||
-- clk => clock_12,
|
||||
-- addr => frgnd_graph_adr,
|
||||
-- data => frgnd_bit1_graph
|
||||
--);
|
||||
|
||||
-- background graphix ROM graph1 bit0
|
||||
bkgnd_bit0 : entity work.dpram generic map (12,8)
|
||||
port map
|
||||
(
|
||||
clock_a => clock_12,
|
||||
wren_a => dn_wr and rom10_cs,
|
||||
address_a => dn_addr(11 downto 0),
|
||||
data_a => dn_data,
|
||||
|
||||
clock_b => clock_12,
|
||||
address_b => bkgnd_graph_adr,
|
||||
q_b => bkgnd_bit0_graph
|
||||
);
|
||||
--bkgnd_bit0 : entity work.prom_graphx_1_bit0
|
||||
--port map(
|
||||
-- clk => clock_12,
|
||||
-- addr => bkgnd_graph_adr,
|
||||
-- data => bkgnd_bit0_graph
|
||||
--);
|
||||
|
||||
-- background graphix ROM graph1 bit1
|
||||
bkgnd_bit1 : entity work.dpram generic map (12,8)
|
||||
port map
|
||||
(
|
||||
clock_a => clock_12,
|
||||
wren_a => dn_wr and rom11_cs,
|
||||
address_a => dn_addr(11 downto 0),
|
||||
data_a => dn_data,
|
||||
|
||||
clock_b => clock_12,
|
||||
address_b => bkgnd_graph_adr,
|
||||
q_b => bkgnd_bit1_graph
|
||||
);
|
||||
--bkgnd_bit1 : entity work.prom_graphx_1_bit1
|
||||
--port map(
|
||||
-- clk => clock_12,
|
||||
-- addr => bkgnd_graph_adr,
|
||||
-- data => bkgnd_bit1_graph
|
||||
--);
|
||||
|
||||
-- color palette ROM RBG low intensity
|
||||
palette_0 : entity work.prom_palette_1
|
||||
port map(
|
||||
clk => clock_12,
|
||||
addr => palette_adr,
|
||||
data => rgb_0
|
||||
);
|
||||
|
||||
-- color palette ROM RBG high intensity
|
||||
palette_1 : entity work.prom_palette_2
|
||||
port map(
|
||||
clk => clock_12,
|
||||
addr => palette_adr,
|
||||
data => rgb_1
|
||||
);
|
||||
|
||||
|
||||
-- Program PROM 0x0000-0x3FFF
|
||||
prog : entity work.dpram generic map (14,8)
|
||||
port map
|
||||
(
|
||||
clock_a => clock_12,
|
||||
wren_a => dn_wr and romp_cs,
|
||||
address_a => dn_addr(13 downto 0),
|
||||
data_a => dn_data,
|
||||
|
||||
clock_b => clock_12,
|
||||
address_b => cpu_adr(13 downto 0),
|
||||
q_b => prog_do
|
||||
);
|
||||
--prog : entity work.prom_prog
|
||||
--port map(
|
||||
-- clk => clock_12,
|
||||
-- addr => cpu_adr(13 downto 0),
|
||||
-- data => prog_do
|
||||
--);
|
||||
|
||||
-- working RAM 0x4000-0x47FF
|
||||
working_ram : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 10)
|
||||
port map(
|
||||
clk => clock_12,
|
||||
we => wrk_ram_we,
|
||||
addr => cpu_adr(9 downto 0),
|
||||
d => cpu_do,
|
||||
q => wrk_ram_do
|
||||
);
|
||||
|
||||
-- foreground RAM 0x8000-0x87FF
|
||||
frgnd_ram : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 11)
|
||||
port map(
|
||||
clk => clock_12n,
|
||||
we => frgnd_ram_we,
|
||||
addr => frgnd_ram_adr,
|
||||
d => cpu_do,
|
||||
q => frgnd_ram_do
|
||||
);
|
||||
|
||||
-- background RAM 0x8800-0x8FFF
|
||||
bkgnd_ram : entity work.gen_ram
|
||||
generic map( dWidth => 8, aWidth => 11)
|
||||
port map(
|
||||
clk => clock_12n,
|
||||
we => bkgnd_ram_we,
|
||||
addr => bkgnd_ram_adr,
|
||||
d => cpu_do,
|
||||
q => bkgnd_ram_do
|
||||
);
|
||||
--
|
||||
---- sound effect1
|
||||
effect1 : entity work.naughty_boy_effect1
|
||||
port map(
|
||||
clk12 => clock_12,
|
||||
trigger_B54 => sound_b(5 downto 4),
|
||||
snd => snd1
|
||||
);
|
||||
|
||||
---- sound effect2
|
||||
effect2 : entity work.naughty_boy_effect2
|
||||
port map(
|
||||
clk12 => clock_12,
|
||||
clksnd => vcnt(0),
|
||||
divider => sound_a(3 downto 0),
|
||||
snd => snd2
|
||||
);
|
||||
|
||||
noise_gen : entity work.naughty_boy_noise
|
||||
port map(
|
||||
clk12 => clock_12,
|
||||
trigger => sound_a(4),
|
||||
noise => noise
|
||||
);
|
||||
|
||||
effect3 : entity work.naughty_boy_effect3
|
||||
port map(
|
||||
clk12 => clock_12,
|
||||
trigger_C4 => sound_c(0),
|
||||
trigger_C5 => sound_c(1),
|
||||
trigger_A5 => sound_a(5),
|
||||
noise => noise,
|
||||
snd_C5 => snd_C5,
|
||||
snd_A5 => snd_A5
|
||||
);
|
||||
|
||||
effect4 : entity work.naughty_boy_effect4
|
||||
port map(
|
||||
clk12 => clock_12,
|
||||
trigger_A6 => sound_a(6),
|
||||
trigger_A7 => sound_a(7),
|
||||
noise => noise,
|
||||
snd_A6 => snd_A6,
|
||||
snd_A7 => snd_A7
|
||||
);
|
||||
|
||||
|
||||
-- tms3615
|
||||
tms3615_clk <= '0' when tms3615_octave = "11" -- could not happen
|
||||
else hcnt(1) when tms3615_octave = "10"
|
||||
else hcnt(2) when tms3615_octave = "01"
|
||||
else hcnt(3) when tms3615_octave = "00";
|
||||
|
||||
tms3615ns : entity work.tms3615
|
||||
port map(
|
||||
clk_sys => hcnt(0),
|
||||
clk_snd => tms3615_clk,
|
||||
trigger => '0'&tms3615_notes,
|
||||
audio => melody
|
||||
);
|
||||
|
||||
--audio <= melody;
|
||||
--audio <= "000000" & snd1 & "0000"; -- alerte monsters
|
||||
--audio <= "00000" & snd2 & "000000"; -- rock hit monsters, misc jingles, ...
|
||||
--audio <= "00" & snd_A5 & "00"; -- rock hit monsters
|
||||
--audio <= "0000000" & snd_C5(7 downto 3) ; -- rock is flying
|
||||
--audio <= "0000" & snd_A6 ; -- rock hit floor, castle fire
|
||||
--audio <= "000000" & snd_A7(7 downto 2) ; -- trop fort -- boy step, castle fire
|
||||
|
||||
---- mix effects and music
|
||||
audio <=
|
||||
melody
|
||||
+ ("000000" & snd1 & "0000")
|
||||
+ ("00000" & snd2 & "000000")
|
||||
+ ("00" & snd_A5 & "00")
|
||||
+ ("0000000" & snd_C5(7 downto 3))
|
||||
+ ("0000" & snd_A6)
|
||||
+ ("000000" & snd_A7(7 downto 2));
|
||||
|
||||
end struct;
|
||||
141
Arcade_MiST/Jaleco NaughtyBoy/rtl/naughty_boy_effect1.vhd
Normal file
141
Arcade_MiST/Jaleco NaughtyBoy/rtl/naughty_boy_effect1.vhd
Normal file
@ -0,0 +1,141 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Naughty Boy sound effect1 by Dar (darfpga@aol.fr) (April 2025)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity naughty_boy_effect1 is
|
||||
port(
|
||||
clk12 : in std_logic;
|
||||
trigger_B54 : in std_logic_vector(1 downto 0);
|
||||
snd : out std_logic_vector(1 downto 0)
|
||||
); end naughty_boy_effect1;
|
||||
|
||||
architecture struct of naughty_boy_effect1 is
|
||||
|
||||
signal clk_div : std_logic_vector(2 downto 0) := (others => '0');
|
||||
signal ena_1p5M : std_logic;
|
||||
|
||||
signal u_c1 : unsigned(15 downto 0) := (others => '0');
|
||||
signal u_c2 : unsigned(15 downto 0) := (others => '0');
|
||||
signal u_c3 : unsigned(15 downto 0) := (others => '0');
|
||||
signal flip1 : std_logic := '0';
|
||||
signal flip2 : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
-- Commande
|
||||
-- R1 = 10k, C=10e-6 SR=1.5MHz
|
||||
-- Charge : VF1 = 65536, k1 = 1172 (R1)
|
||||
-- Decharge : VF2 = 2321, k2 = 1172 (R1)
|
||||
-- Div = 2^7
|
||||
|
||||
process (clk12)
|
||||
variable cnt : unsigned(15 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
clk_div <= clk_div + 1;
|
||||
ena_1p5M <= '0';
|
||||
if clk_div = "111" then
|
||||
clk_div <= (others => '0');
|
||||
ena_1p5M <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
process (clk12)
|
||||
variable cnt : unsigned(12 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
if ena_1p5M = '1' then
|
||||
cnt := cnt + 1;
|
||||
if trigger_B54(0) = '1' then
|
||||
if cnt > 1172 then
|
||||
cnt := (others => '0');
|
||||
u_c1 <= u_c1 + (65535 - u_c1)/128;
|
||||
end if;
|
||||
else
|
||||
if cnt > 1172 then
|
||||
cnt := (others => '0');
|
||||
u_c1 <= u_c1 - (u_c1 - 2321)/128;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Oscillateur 1
|
||||
-- R1 = 10k, R2 = 200k, C=0.01e-6 SR=12MHz
|
||||
-- Charge : VF1 = 65535, k1 = 197 (R1+R2)
|
||||
-- Decharge : VF2 = 2621, k2 = 188 (R2)
|
||||
-- Div = 2^7
|
||||
|
||||
process (clK12)
|
||||
variable cnt : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
if trigger_B54(1) = '0' then
|
||||
cnt := (others => '0');
|
||||
u_c2 <= (others => '0');
|
||||
flip1 <= '0';
|
||||
else
|
||||
if u_c2 > u_c1 then flip1 <= '0'; end if;
|
||||
if u_c2 < u_c1/2 then flip1 <= '1'; end if;
|
||||
cnt := cnt + 1;
|
||||
if flip1 = '1' then
|
||||
if cnt > 197 then
|
||||
cnt := (others => '0');
|
||||
u_c2 <= u_c2 + (65535 - u_c2)/128;
|
||||
end if;
|
||||
else
|
||||
if cnt > 188 then
|
||||
cnt := (others => '0');
|
||||
u_c2 <= u_c2 - (u_c2 - 2621)/128;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Oscillateur 2
|
||||
-- R1 = 47k, R2 = 200k, C=0.01e-6 SR=12MHz
|
||||
-- Charge : VF1 = 65535, k1 = 232 (R1+R2)
|
||||
-- Decharge : VF2 = 2621, k2 = 188 (R2)
|
||||
-- Div = 2^7
|
||||
|
||||
process (clK12)
|
||||
variable cnt : unsigned(7 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
if trigger_B54(1) = '0' then
|
||||
cnt := (others => '0');
|
||||
u_c3 <= (others => '0');
|
||||
flip2 <= '0';
|
||||
else
|
||||
if u_c3 > u_c1 then flip2 <= '0'; end if;
|
||||
if u_c3 < u_c1/2 then flip2 <= '1'; end if;
|
||||
cnt := cnt + 1;
|
||||
if flip2 = '1' then
|
||||
if cnt > 232 then
|
||||
cnt := (others => '0');
|
||||
u_c3 <= u_c3 + (65535 - u_c3)/128;
|
||||
end if;
|
||||
else
|
||||
if cnt > 188 then
|
||||
cnt := (others => '0');
|
||||
u_c3 <= u_c3 - (u_c3 - 2621)/128;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
snd <= ('0'&flip1)+('0'&flip2);
|
||||
|
||||
end struct;
|
||||
|
||||
52
Arcade_MiST/Jaleco NaughtyBoy/rtl/naughty_boy_effect2.vhd
Normal file
52
Arcade_MiST/Jaleco NaughtyBoy/rtl/naughty_boy_effect2.vhd
Normal file
@ -0,0 +1,52 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Naughty Boy sound effect2 by Dar (darfpga@aol.fr) (April 2025)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity naughty_boy_effect2 is
|
||||
port(
|
||||
clk12 : in std_logic;
|
||||
clksnd : in std_logic;
|
||||
divider : in std_logic_vector(3 downto 0);
|
||||
snd : out std_logic
|
||||
); end naughty_boy_effect2;
|
||||
|
||||
architecture struct of naughty_boy_effect2 is
|
||||
|
||||
signal clksnd_r : std_logic := '0';
|
||||
signal sound : std_logic := '0';
|
||||
|
||||
begin
|
||||
|
||||
-- Diviseur
|
||||
-- LS163 : Count up, Sync load when 0xF (no toggle sound if divider = 0xF)
|
||||
-- LS74 : Divide by 2
|
||||
|
||||
process (clk12)
|
||||
variable cnt : unsigned(3 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
if divider = "1111" then
|
||||
sound <= '0';
|
||||
else
|
||||
clksnd_r <= clksnd;
|
||||
if clksnd = '1' and clksnd_r = '0' then
|
||||
cnt := cnt + 1;
|
||||
if cnt = "0000" then
|
||||
cnt := unsigned(divider);
|
||||
sound <= not sound;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
snd <= sound;
|
||||
|
||||
end struct;
|
||||
|
||||
164
Arcade_MiST/Jaleco NaughtyBoy/rtl/naughty_boy_effect3.vhd
Normal file
164
Arcade_MiST/Jaleco NaughtyBoy/rtl/naughty_boy_effect3.vhd
Normal file
@ -0,0 +1,164 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Naughty boy sound effect3 by Dar (darfpga@aol.fr) (April 2025)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity naughty_boy_effect3 is
|
||||
port(
|
||||
clk12 : in std_logic;
|
||||
trigger_C4 : in std_logic;
|
||||
trigger_C5 : in std_logic;
|
||||
trigger_A5 : in std_logic;
|
||||
noise : in std_logic;
|
||||
snd_C5 : out std_logic_vector(7 downto 0);
|
||||
snd_A5 : out std_logic_vector(7 downto 0)
|
||||
); end naughty_boy_effect3;
|
||||
|
||||
architecture struct of naughty_boy_effect3 is
|
||||
|
||||
signal u_c1 : unsigned(15 downto 0) := (others => '0');
|
||||
|
||||
signal u_c2 : unsigned(15 downto 0) := (others => '0');
|
||||
signal u_ctrl2 : unsigned(15 downto 0) := (others => '0');
|
||||
signal flip2 : std_logic := '0';
|
||||
|
||||
signal u_c3 : unsigned(15 downto 0) := (others => '0');
|
||||
signal u_c4 : unsigned(15 downto 0) := (others => '0');
|
||||
|
||||
signal clk_div : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal ena_47k : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-- Commande1 (C4)
|
||||
-- R1 = 3k, R2 = 2k, C=10e-6 SR=12MHz
|
||||
-- Charge : VF1 = 65536 k1 = 2344 (R1+R2)
|
||||
-- Decharge : VF2 = 8651, k2 = 938 (R2)
|
||||
-- Div = 2^8
|
||||
|
||||
process (clk12)
|
||||
variable cnt : unsigned(15 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
cnt := cnt + 1;
|
||||
if trigger_C4 = '1' then
|
||||
if cnt > 2344 then
|
||||
cnt := (others => '0');
|
||||
u_c1 <= u_c1 + (65535 - u_c1)/256;
|
||||
end if;
|
||||
else
|
||||
if cnt > 938 then
|
||||
cnt := (others => '0');
|
||||
u_c1 <= u_c1 - (u_c1 - 8651)/256;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Oscillateur
|
||||
-- R1 = 33k, R2 = 100k, C=0.0047e-6, SR=12MHz
|
||||
-- Charge : VF1 = 65536, k1 = 469 (R1+R2, C)
|
||||
-- Decharge : VF2 = 2621, k2 = 353 (R2, C)
|
||||
-- Div = 2^4
|
||||
|
||||
u_ctrl2 <= u_c1/2 when noise = '0' else u_c1/2 + 65536/4;
|
||||
|
||||
process (clk12)
|
||||
variable cnt : unsigned(15 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
if u_c2 > u_ctrl2 then flip2 <= '0'; end if;
|
||||
if u_c2 < u_ctrl2/2 then flip2 <= '1'; end if;
|
||||
cnt := cnt + 1;
|
||||
if flip2 = '1' then
|
||||
if cnt > 469 then
|
||||
cnt := (others => '0');
|
||||
u_c2 <= u_c2 + (65535 - u_c2)/16;
|
||||
end if;
|
||||
else
|
||||
if cnt > 353 then
|
||||
cnt := (others => '0');
|
||||
u_c2 <= u_c2 - (u_c2 - 2621)/16;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
---- Commande2 (A5)
|
||||
---- R1 = 330k, R2 = 220k, C=10e-6 SR=0.046875MHz (12MHz/256)
|
||||
---- Charge : VF1 = 29753, k1 = 604 (R1)
|
||||
---- Decharge : VF2 = 0, k2 = 403 (R2)
|
||||
---- Div = 2^8
|
||||
|
||||
process (clk12)
|
||||
variable cnt : unsigned(15 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
clk_div <= clk_div + 1;
|
||||
ena_47k <= '0';
|
||||
if clk_div = x"FF" then
|
||||
clk_div <= (others => '0');
|
||||
ena_47k <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk12)
|
||||
variable cnt : unsigned(15 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
if ena_47k = '1' then
|
||||
cnt := cnt + 1;
|
||||
if trigger_A5 = '1' then
|
||||
if cnt > 604 then
|
||||
cnt := (others => '0');
|
||||
u_c3 <= u_c3 + (29753 - u_c3)/256;
|
||||
end if;
|
||||
else
|
||||
if cnt > 403 then
|
||||
cnt := (others => '0');
|
||||
u_c3 <= u_c3 - (u_c3 - 0)/256;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- chop u_C3 voltage with ocillator output
|
||||
snd_A5 <= std_logic_vector(u_c3(15 downto 8)) when flip2 = '1' else (others => '0');
|
||||
|
||||
---- Commande3 (C5)
|
||||
---- R1 = 330, R2 = 330, C=10e-6 SR=12MHz
|
||||
---- Charge : VF1 = 65536, k1 = 155 (R1)
|
||||
---- Decharge : VF2 = 0, k2 = 4688 (R2)
|
||||
---- Div = 2^8
|
||||
|
||||
process (clk12)
|
||||
variable cnt : unsigned(15 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
cnt := cnt + 1;
|
||||
if trigger_C5 = '1' then
|
||||
if cnt > 155 then
|
||||
cnt := (others => '0');
|
||||
u_c4 <= u_c4 + (65535 - u_c4)/256;
|
||||
end if;
|
||||
else
|
||||
if cnt > 4688 then
|
||||
cnt := (others => '0');
|
||||
u_c4 <= u_c4 - (u_c4 - 0)/256;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- chop u_C4 voltage with ocillator output
|
||||
snd_C5 <= std_logic_vector(u_c4(15 downto 8)) when flip2 = '1' else (others => '0');
|
||||
|
||||
end struct;
|
||||
58
Arcade_MiST/Jaleco NaughtyBoy/rtl/naughty_boy_effect4.vhd
Normal file
58
Arcade_MiST/Jaleco NaughtyBoy/rtl/naughty_boy_effect4.vhd
Normal file
@ -0,0 +1,58 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Naughty boy sound effect4 by Dar (darfpga@aol.fr) (April 2025)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity naughty_boy_effect4 is
|
||||
port(
|
||||
clk12 : in std_logic;
|
||||
trigger_A6 : in std_logic;
|
||||
trigger_A7 : in std_logic;
|
||||
noise : in std_logic;
|
||||
snd_A6 : out std_logic_vector(7 downto 0);
|
||||
snd_A7 : out std_logic_vector(7 downto 0)
|
||||
); end naughty_boy_effect4;
|
||||
|
||||
architecture struct of naughty_boy_effect4 is
|
||||
|
||||
signal u_c1 : unsigned(15 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
-- Commande1 (A6)
|
||||
-- R1 = 330, R2 = 10k, C=10e-6 SR=12MHz
|
||||
-- Charge : VF1 = 59507 k1 = 34 (R1)
|
||||
-- Decharge : VF2 = 0 k2 = 1031 (R2)
|
||||
-- Div = 2^8
|
||||
|
||||
process (clk12)
|
||||
variable cnt : unsigned(15 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
cnt := cnt + 1;
|
||||
if trigger_A6 = '1' then
|
||||
if cnt > 34 then
|
||||
cnt := (others => '0');
|
||||
u_c1 <= u_c1 + (59507 - u_c1)/256;
|
||||
end if;
|
||||
else
|
||||
if cnt > 1031 then
|
||||
cnt := (others => '0');
|
||||
u_c1 <= u_c1 - (u_c1 - 0)/256;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- chop u_C3 voltage with noise
|
||||
snd_A6 <= std_logic_vector(u_c1(15 downto 8)) when noise = '1' else (others => '0');
|
||||
|
||||
-- chop trigger A7 with noise
|
||||
snd_A7 <= (others => '1') when trigger_A7 ='1' and noise = '1' else (others => '0');
|
||||
|
||||
end struct;
|
||||
229
Arcade_MiST/Jaleco NaughtyBoy/rtl/naughty_boy_mist.sv
Normal file
229
Arcade_MiST/Jaleco NaughtyBoy/rtl/naughty_boy_mist.sv
Normal file
@ -0,0 +1,229 @@
|
||||
module naughty_boy_mist(
|
||||
output LED,
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_HS,
|
||||
output VGA_VS,
|
||||
output AUDIO_L,
|
||||
output AUDIO_R,
|
||||
input SPI_SCK,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
input SPI_SS2,
|
||||
input SPI_SS3,
|
||||
input CONF_DATA0,
|
||||
input CLOCK_27
|
||||
);
|
||||
|
||||
|
||||
`include "rtl\build_id.v"
|
||||
|
||||
localparam CONF_STR = {
|
||||
"NBOY;;",
|
||||
"O2,Rotate Controls,Off,On;",
|
||||
"O34,Scanlines,Off,25%,50%,75%;",
|
||||
"O5,Joystick Swap,Off,On;",
|
||||
"OF,Flip Screen,Off,On;",
|
||||
|
||||
"O89,Lives,2,3,4,5;",
|
||||
"OA,Difficulty,Easier,Harder;",
|
||||
"ODE,Bonus Life,10k,30k,50k,70k;",
|
||||
"OC,Cabinet,Upright,Cocktail;",
|
||||
|
||||
"T0,Reset;",
|
||||
"V,v1.15.",`BUILD_DATE
|
||||
};
|
||||
|
||||
wire rotate = status[2];
|
||||
wire [1:0] scanlines = status[4:3];
|
||||
wire blend = status[5];
|
||||
//wire [1:0] lives = status[7:6];
|
||||
//wire bonus = status[8];
|
||||
//wire [2:0] difficulty = status[11:9];
|
||||
//wire demosnd = status[12];
|
||||
|
||||
assign LED = 1;
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
|
||||
wire clock_24, clock_12, pll_locked;
|
||||
pll pll(
|
||||
.inclk0(CLOCK_27),
|
||||
.c0(clock_24),//48
|
||||
.c1(clock_12),//12
|
||||
.locked(pll_locked)
|
||||
);
|
||||
|
||||
wire [63:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire [1:0] switches;
|
||||
wire [15:0] joystick_0;
|
||||
wire [15:0] joystick_1;
|
||||
wire scandoublerD;
|
||||
wire ypbpr;
|
||||
wire no_csync;
|
||||
wire key_strobe;
|
||||
wire key_pressed;
|
||||
wire [7:0] key_code;
|
||||
|
||||
user_io #(
|
||||
.STRLEN($size(CONF_STR)>>3),
|
||||
.ROM_DIRECT_UPLOAD(0))
|
||||
user_io(
|
||||
.clk_sys (clock_24 ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_CLK (SPI_SCK ),
|
||||
.SPI_SS_IO (CONF_DATA0 ),
|
||||
.SPI_MISO (SPI_DO ),
|
||||
.SPI_MOSI (SPI_DI ),
|
||||
.buttons (buttons ),
|
||||
.switches (switches ),
|
||||
.scandoubler_disable (scandoublerD ),
|
||||
.ypbpr (ypbpr ),
|
||||
.no_csync (no_csync ),
|
||||
.core_mod (game_mod),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_code (key_code ),
|
||||
.joystick_0 (joystick_0 ),
|
||||
.joystick_1 (joystick_1 ),
|
||||
.status (status )
|
||||
);
|
||||
|
||||
wire ioctl_downl;
|
||||
wire [7:0] ioctl_index;
|
||||
wire ioctl_wr;
|
||||
wire [24:0] ioctl_addr;
|
||||
wire [7:0] ioctl_dout;
|
||||
|
||||
data_io data_io(
|
||||
.clk_sys ( clock_12 ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS2 ( SPI_SS2 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
.ioctl_download( ioctl_downl ),
|
||||
.ioctl_index ( ioctl_index ),
|
||||
.ioctl_wr ( ioctl_wr ),
|
||||
.ioctl_addr ( ioctl_addr ),
|
||||
.ioctl_dout ( ioctl_dout )
|
||||
);
|
||||
|
||||
// reset generation
|
||||
reg reset = 1;
|
||||
reg rom_loaded = 0;
|
||||
always @(posedge clock_12) begin
|
||||
reg ioctl_downlD;
|
||||
ioctl_downlD <= ioctl_downl;
|
||||
|
||||
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
|
||||
reset <= status[0] | buttons[1] | ~rom_loaded;
|
||||
end
|
||||
|
||||
wire [11:0] audio;
|
||||
wire [1:0] game_mod;
|
||||
wire hs, vs, cs;
|
||||
wire hb, vb;
|
||||
wire blankn = ~(hb | vb);
|
||||
wire [1:0] r, g, b;
|
||||
|
||||
wire [7:0] dip_switch = { status[12],status[10],1'b0,1'b1,status[14:13],status[9:8]};
|
||||
wire [4:0]buttons1, buttons2;
|
||||
always @ (posedge clock_12) begin
|
||||
case (game_mod)
|
||||
2'b00 : begin //Naughty Boy
|
||||
buttons1 = {m_left,m_right,m_down,m_up,m_fireA};
|
||||
buttons2 = {m_left2,m_right2,m_down2,m_up2,m_fire2A};
|
||||
end
|
||||
2'b01 : begin //Pop Flamer
|
||||
buttons1 = {m_left,m_right,m_down,m_up,m_fireA};
|
||||
buttons2 = {m_left2,m_right2,m_down2,m_up2,m_fire2A};
|
||||
end
|
||||
2'b10 : begin //Trivia Master
|
||||
buttons1 = {m_fireD,m_fireC,m_fireB,m_fireA,1'b0};
|
||||
buttons2 = {m_fire2D,m_fire2C,m_fire2B,m_fire2A,1'b0};
|
||||
end
|
||||
default : begin
|
||||
buttons1 = {m_left,m_right,m_down,m_up,m_fireA};
|
||||
buttons2 = {m_left2,m_right2,m_down2,m_up2,m_fire2A};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
naughty_boy naughty_boy_inst(
|
||||
.clock_12 (clock_12) ,
|
||||
.reset (reset) ,
|
||||
.game_mod (game_mod) ,
|
||||
.dn_addr (ioctl_addr) ,
|
||||
.dn_data (ioctl_dout) ,
|
||||
.dn_wr (ioctl_wr) ,
|
||||
.dip_switch (dip_switch) ,
|
||||
.flip_screen (status[6]) ,
|
||||
.coin (m_coin1) ,
|
||||
.starts ({m_two_players, m_one_player}) ,
|
||||
.player1_btns (buttons1),
|
||||
.player2_btns (buttons2),
|
||||
.video_r (r) ,
|
||||
.video_g (g) ,
|
||||
.video_b (b) ,
|
||||
.video_csync (cs) ,
|
||||
.video_hs (hs) ,
|
||||
.video_vs (vs) ,
|
||||
.video_hblank (hb) ,
|
||||
.video_vblank (vb) ,
|
||||
.ce_pix () ,
|
||||
.audio (audio)
|
||||
);
|
||||
|
||||
mist_video #(.COLOR_DEPTH(2), .SD_HCNT_WIDTH(11)) mist_video(
|
||||
.clk_sys ( clock_24 ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS3 ( SPI_SS3 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
.R ( blankn ? r : 0 ),
|
||||
.G ( blankn ? g : 0 ),
|
||||
.B ( blankn ? b : 0 ),
|
||||
.HSync ( hs ),
|
||||
.VSync ( vs ),
|
||||
.VGA_R ( VGA_R ),
|
||||
.VGA_G ( VGA_G ),
|
||||
.VGA_B ( VGA_B ),
|
||||
.VGA_VS ( VGA_VS ),
|
||||
.VGA_HS ( VGA_HS ),
|
||||
.rotate ( { 1'b1, rotate } ),
|
||||
.scandoubler_disable( scandoublerD ),
|
||||
.blend ( blend ),
|
||||
.scanlines ( scanlines ),
|
||||
.ypbpr ( ypbpr ),
|
||||
.no_csync ( no_csync )
|
||||
);
|
||||
|
||||
dac #(.C_bits(16))dac(
|
||||
.clk_i(clock_24),
|
||||
.res_n_i(1),
|
||||
.dac_i({audio, 4'b0000}),
|
||||
.dac_o(AUDIO_L)
|
||||
);
|
||||
|
||||
// Arcade inputs
|
||||
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
|
||||
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
|
||||
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
|
||||
|
||||
arcade_inputs inputs (
|
||||
.clk ( clock_12 ),
|
||||
.key_strobe ( key_strobe ),
|
||||
.key_pressed ( key_pressed ),
|
||||
.key_code ( key_code ),
|
||||
.joystick_0 ( joystick_0 ),
|
||||
.joystick_1 ( joystick_1 ),
|
||||
.rotate ( rotate ),
|
||||
.orientation ( 2'b11 ),
|
||||
.joyswap ( status[5] ),
|
||||
.oneplayer ( 1'b1 ),
|
||||
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
|
||||
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
|
||||
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
|
||||
);
|
||||
|
||||
endmodule
|
||||
87
Arcade_MiST/Jaleco NaughtyBoy/rtl/naughty_boy_noise.vhd
Normal file
87
Arcade_MiST/Jaleco NaughtyBoy/rtl/naughty_boy_noise.vhd
Normal file
@ -0,0 +1,87 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Naughty Boy sound effect3 (noise) by Dar (darfpga@aol.fr) (April 2016)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity naughty_boy_noise is
|
||||
port(
|
||||
clk12 : in std_logic;
|
||||
trigger : in std_logic;
|
||||
noise : out std_logic
|
||||
); end naughty_boy_noise;
|
||||
|
||||
architecture struct of naughty_boy_noise is
|
||||
|
||||
signal u_c1 : unsigned(15 downto 0) := (others => '0');
|
||||
signal flip1 : std_logic := '0';
|
||||
signal flip1_r : std_logic := '0';
|
||||
signal u_ctrl : unsigned(15 downto 0) := (others => '0');
|
||||
signal shift_reg : std_logic_vector(17 downto 0) := (others => '0');
|
||||
|
||||
begin
|
||||
|
||||
-- control voltage from LS136 (open collector)
|
||||
|
||||
-- when trigger = '0', ouput LS136 H (Z): 2K open
|
||||
--
|
||||
-- u_ctrl = 2/3*VCC (0xAAAA)
|
||||
-- |
|
||||
-- VCC |---[ 5k ]-|-[ 5k ]---[ 5k ]---|GND
|
||||
--
|
||||
|
||||
-- when trigger = '1', output LS136 L : 2K // (5K+5K) to GND
|
||||
--
|
||||
-- u_ctrl = 0.25*VCC (0x4000)
|
||||
-- |
|
||||
-- VCC |---[ 5k ]-|-[ 5k ]---[ 5k ]---|GND
|
||||
-- |-[ 2K ]------------|
|
||||
|
||||
|
||||
u_ctrl <= x"AAAA" when trigger = '0' else x"4000";
|
||||
|
||||
-- Oscillateur
|
||||
-- R1 = 200k, R2 = 1k, C=0.01e-6, SR=12MHz
|
||||
-- Charge : VF1 = 65536, k1 = 1508 (R1+R2, C)
|
||||
-- Decharge : VF2 = 2621, k2 = 8 (R2, C)
|
||||
-- Div = 2^4
|
||||
|
||||
process (clk12)
|
||||
variable cnt : unsigned(15 downto 0) := (others => '0');
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
if u_c1 > u_ctrl then flip1 <= '0'; end if;
|
||||
if u_c1 < u_ctrl/2 then flip1 <= '1'; end if;
|
||||
cnt := cnt + 1;
|
||||
if flip1 = '1' then
|
||||
if cnt > 1508 then
|
||||
cnt := (others => '0');
|
||||
u_c1 <= u_c1 + (65535 - u_c1)/16;
|
||||
end if;
|
||||
else
|
||||
if cnt > 8 then
|
||||
cnt := (others => '0');
|
||||
u_c1 <= u_c1 - (u_c1 - 2621)/16;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- noise generator triggered by oscillator output
|
||||
process (clk12)
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
flip1_r <= flip1;
|
||||
if flip1_r = '0' and flip1 ='1' then
|
||||
shift_reg <= shift_reg(16 downto 0) & not(shift_reg(17) xor shift_reg(16));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
noise <= not(shift_reg(17) xor shift_reg(16));
|
||||
|
||||
end struct;
|
||||
146
Arcade_MiST/Jaleco NaughtyBoy/rtl/naughty_boy_video.vhd
Normal file
146
Arcade_MiST/Jaleco NaughtyBoy/rtl/naughty_boy_video.vhd
Normal file
@ -0,0 +1,146 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- Naughty Boy video generator by Dar (darfpga@aol.fr)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity naughty_boy_video is
|
||||
port(
|
||||
clk12 : in std_logic;
|
||||
hcnt : out std_logic_vector(8 downto 0);
|
||||
vcnt : out std_logic_vector(7 downto 0);
|
||||
ena_pix : inout std_logic;
|
||||
hsync : out std_logic;
|
||||
vsync : out std_logic;
|
||||
csync : out std_logic;
|
||||
cpu_wait : out std_logic;
|
||||
-- clr_vid : out std_logic;
|
||||
|
||||
hblank : out std_logic;
|
||||
vblank : out std_logic;
|
||||
|
||||
sel_cpu_addr : out std_logic;
|
||||
sel_scrl_addr : out std_logic
|
||||
); end naughty_boy_video;
|
||||
|
||||
architecture struct of naughty_boy_video is
|
||||
signal hcnt_i : unsigned(8 downto 0) := (others=>'0');
|
||||
signal vcnt_i : unsigned(7 downto 0) := (others=>'0');
|
||||
|
||||
constant start_l : integer := 170;
|
||||
|
||||
begin
|
||||
|
||||
-- horizontal counter clock (pixel clock)
|
||||
process (clk12)
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
ena_pix <= not ena_pix;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- horizontal counter from 0x080 to 0x1FF : 384 pixels
|
||||
process (clk12)
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
if ena_pix = '1' then
|
||||
if hcnt_i = "111111111" then
|
||||
hcnt_i <= "010000000";
|
||||
else
|
||||
hcnt_i <= hcnt_i + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- vertical counter from 0x00 to 0xFF : 256 lines
|
||||
process (clk12)
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
if ena_pix = '1' and hcnt_i = 159 then
|
||||
if vcnt_i = "11111111" then
|
||||
vcnt_i <= (others=>'0');
|
||||
else
|
||||
vcnt_i <= vcnt_i +1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- Misc
|
||||
sel_scrl_addr <= hcnt_i(8);
|
||||
|
||||
hsync <= '0' when (hcnt_i > (192-16)) and (hcnt_i < (220-16)) else '1';
|
||||
vsync <= '0' when (vcnt_i > 232) and (vcnt_i < 240) else '1';
|
||||
|
||||
hblank <= '1' when (hcnt_i > (128+15)) and (hcnt_i < (255-15)) else '0';
|
||||
vblank <= '1' when (vcnt_i > 223) else '0';
|
||||
|
||||
process (clk12)
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
if ena_pix = '1' then
|
||||
|
||||
if hcnt_i = 159 then cpu_wait <= '0'; end if;
|
||||
if hcnt_i = 223 and vcnt_i < 224 then cpu_wait <= '1'; end if;
|
||||
|
||||
if hcnt_i = 143 then sel_cpu_addr <= '1'; end if;
|
||||
if hcnt_i = 239 and vcnt_i < 224 then sel_cpu_addr <= '0'; end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
hcnt <= std_logic_vector(hcnt_i);
|
||||
vcnt <= std_logic_vector(vcnt_i);
|
||||
|
||||
-- Composite Sync
|
||||
process (clk12)
|
||||
begin
|
||||
if rising_edge(clk12) then
|
||||
if ena_pix = '1' then
|
||||
|
||||
if vcnt_i >= 224 and vcnt_i <= 225 then
|
||||
if hcnt_i = start_l then csync <= '0'; end if;
|
||||
if hcnt_i = start_l +14 then csync <= '1'; end if;
|
||||
if hcnt_i = start_l+192 then csync <= '0'; end if;
|
||||
if hcnt_i = start_l+192+14 then csync <= '1'; end if;
|
||||
|
||||
elsif vcnt_i = 226 then
|
||||
if hcnt_i = start_l then csync <= '0'; end if;
|
||||
if hcnt_i = start_l +14 then csync <= '1'; end if;
|
||||
if hcnt_i = start_l+192 then csync <= '0'; end if;
|
||||
|
||||
elsif vcnt_i >= 227 and vcnt_i <= 228 then
|
||||
if hcnt_i = start_l -14 then csync <= '1'; end if;
|
||||
if hcnt_i = start_l then csync <= '0'; end if;
|
||||
if hcnt_i = start_l+192-14 then csync <= '1'; end if;
|
||||
if hcnt_i = start_l+192 then csync <= '0'; end if;
|
||||
|
||||
elsif vcnt_i = 229 then
|
||||
if hcnt_i = start_l -14 then csync <= '1'; end if;
|
||||
if hcnt_i = start_l then csync <= '0'; end if;
|
||||
if hcnt_i = start_l +14 then csync <= '1'; end if;
|
||||
if hcnt_i = start_l+192 then csync <= '0'; end if;
|
||||
if hcnt_i = start_l+192+14 then csync <= '1'; end if;
|
||||
|
||||
elsif vcnt_i = 230 then
|
||||
if hcnt_i = start_l then csync <= '0'; end if;
|
||||
if hcnt_i = start_l +14 then csync <= '1'; end if;
|
||||
if hcnt_i = start_l+192 then csync <= '0'; end if;
|
||||
if hcnt_i = start_l+192+14 then csync <= '1'; end if;
|
||||
|
||||
else
|
||||
if hcnt_i = start_l then csync <= '0'; end if;
|
||||
if hcnt_i = start_l +28 then csync <= '1'; end if;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end struct;
|
||||
4
Arcade_MiST/Jaleco NaughtyBoy/rtl/pll.qip
Normal file
4
Arcade_MiST/Jaleco NaughtyBoy/rtl/pll.qip
Normal file
@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
|
||||
337
Arcade_MiST/Jaleco NaughtyBoy/rtl/pll.v
Normal file
337
Arcade_MiST/Jaleco NaughtyBoy/rtl/pll.v
Normal file
@ -0,0 +1,337 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2013 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll (
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
locked);
|
||||
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output locked;
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire2;
|
||||
wire [0:0] sub_wire6 = 1'h0;
|
||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire locked = sub_wire2;
|
||||
wire c0 = sub_wire3;
|
||||
wire sub_wire4 = inclk0;
|
||||
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
|
||||
|
||||
altpll altpll_component (
|
||||
.inclk (sub_wire5),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire2),
|
||||
.activeclock (),
|
||||
.areset (1'b0),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 9,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 16,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 9,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 4,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_USED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.self_reset_on_loss_lock = "OFF",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
38
Arcade_MiST/Jaleco NaughtyBoy/rtl/prom_palette_1.vhd
Normal file
38
Arcade_MiST/Jaleco NaughtyBoy/rtl/prom_palette_1.vhd
Normal file
@ -0,0 +1,38 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity prom_palette_1 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(7 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of prom_palette_1 is
|
||||
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"02",X"05",X"05",X"05",X"02",X"02",X"02",
|
||||
X"02",X"01",X"06",X"06",X"06",X"01",X"01",X"01",X"01",X"04",X"03",X"03",X"03",X"04",X"04",X"04",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"01",X"01",X"01",X"03",X"03",X"03",X"03",
|
||||
X"01",X"04",X"06",X"06",X"05",X"01",X"01",X"01",X"07",X"07",X"01",X"01",X"01",X"05",X"05",X"05",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"02",X"01",X"01",X"01",X"01",X"01",X"01",
|
||||
X"04",X"01",X"02",X"02",X"02",X"02",X"02",X"02",X"01",X"04",X"07",X"07",X"07",X"07",X"07",X"07",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"01",X"07",X"07",X"03",X"03",X"03",X"03",
|
||||
X"01",X"04",X"01",X"01",X"05",X"01",X"01",X"01",X"07",X"07",X"01",X"01",X"01",X"05",X"05",X"05",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"05",
|
||||
X"02",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"01",X"06",X"06",X"06",X"06",X"06",X"06",X"06",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"05",X"03",X"03",X"03",X"01",X"01",
|
||||
X"04",X"04",X"06",X"05",X"05",X"01",X"04",X"02",X"07",X"07",X"01",X"06",X"06",X"05",X"02",X"03",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
|
||||
X"04",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"01",X"02",X"02",X"02",X"02",X"02",X"02",X"02",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"05",X"01",X"01",X"03",X"01",X"01",
|
||||
X"04",X"04",X"06",X"02",X"02",X"01",X"04",X"02",X"07",X"07",X"01",X"04",X"04",X"05",X"02",X"03");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
38
Arcade_MiST/Jaleco NaughtyBoy/rtl/prom_palette_2.vhd
Normal file
38
Arcade_MiST/Jaleco NaughtyBoy/rtl/prom_palette_2.vhd
Normal file
@ -0,0 +1,38 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all,ieee.numeric_std.all;
|
||||
|
||||
entity prom_palette_2 is
|
||||
port (
|
||||
clk : in std_logic;
|
||||
addr : in std_logic_vector(7 downto 0);
|
||||
data : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity;
|
||||
|
||||
architecture prom of prom_palette_2 is
|
||||
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
|
||||
signal rom_data: rom := (
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"06",X"05",X"05",X"05",X"03",X"03",X"03",
|
||||
X"02",X"05",X"06",X"06",X"06",X"01",X"01",X"01",X"01",X"04",X"03",X"03",X"03",X"04",X"04",X"04",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"01",X"07",X"07",X"03",X"03",X"03",X"03",
|
||||
X"01",X"04",X"07",X"07",X"05",X"07",X"07",X"07",X"07",X"07",X"01",X"01",X"01",X"05",X"05",X"05",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"07",X"06",X"01",X"01",X"01",X"01",X"01",X"01",
|
||||
X"04",X"05",X"02",X"02",X"02",X"02",X"02",X"02",X"01",X"05",X"07",X"07",X"07",X"07",X"07",X"07",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"01",X"07",X"07",X"03",X"03",X"03",X"03",
|
||||
X"01",X"04",X"01",X"01",X"05",X"07",X"07",X"07",X"07",X"07",X"01",X"01",X"01",X"05",X"05",X"05",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"05",
|
||||
X"02",X"03",X"03",X"03",X"03",X"03",X"03",X"03",X"01",X"06",X"06",X"06",X"06",X"06",X"06",X"06",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"05",X"03",X"03",X"03",X"05",X"01",
|
||||
X"04",X"04",X"07",X"05",X"05",X"07",X"05",X"02",X"07",X"07",X"01",X"06",X"06",X"05",X"03",X"03",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"05",X"01",X"01",X"01",X"01",X"01",X"01",X"01",
|
||||
X"04",X"05",X"05",X"05",X"05",X"05",X"05",X"05",X"01",X"02",X"02",X"02",X"02",X"02",X"02",X"02",
|
||||
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"05",X"01",X"01",X"03",X"05",X"01",
|
||||
X"04",X"04",X"07",X"02",X"02",X"07",X"05",X"02",X"07",X"07",X"01",X"04",X"04",X"05",X"03",X"03");
|
||||
begin
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
data <= rom_data(to_integer(unsigned(addr)));
|
||||
end if;
|
||||
end process;
|
||||
end architecture;
|
||||
111
Arcade_MiST/Jaleco NaughtyBoy/rtl/tms3615.vhd
Normal file
111
Arcade_MiST/Jaleco NaughtyBoy/rtl/tms3615.vhd
Normal file
@ -0,0 +1,111 @@
|
||||
---------------------------------------------------------------------------------
|
||||
-- TMS3615 by Dar (darfpga@aol.fr) (April 2025)
|
||||
-- http://darfpga.blogspot.fr
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.ALL;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity tms3615 is
|
||||
port(
|
||||
clk_sys : in std_logic;
|
||||
clk_snd : in std_logic;
|
||||
trigger : in std_logic_vector(12 downto 0);
|
||||
|
||||
audio : out std_logic_vector(11 downto 0)
|
||||
|
||||
); end tms3615;
|
||||
|
||||
architecture struct of tms3615 is
|
||||
|
||||
type ton_array is array(0 to 12) of integer range 956 downto 478;
|
||||
constant tons : ton_array := (956,902,852,804,758,716,676,638,602,568,536,506,478);
|
||||
|
||||
type cnt_array is array(0 to 12) of std_logic_vector(9 downto 0);
|
||||
signal cnts : cnt_array := (others => (others => '0'));
|
||||
|
||||
signal freqs : std_logic_vector(12 downto 0) := "0000000000000";
|
||||
|
||||
type amp_array is array(0 to 12) of unsigned(6 downto 0);
|
||||
signal amps : amp_array := (others => (others => '0'));
|
||||
|
||||
type level_array is array(0 to 12) of signed(11 downto 0);
|
||||
signal levels : level_array := (others => (others => '0'));
|
||||
|
||||
type decay_array is array(0 to 12) of std_logic_vector(15 downto 0);
|
||||
signal decays : decay_array := (others => (others => '0'));
|
||||
|
||||
signal trigger_r : std_logic_vector(12 downto 0);
|
||||
signal clk_snd_r : std_logic;
|
||||
signal clk_ena : std_logic;
|
||||
|
||||
signal sum : signed(11 downto 0) := (others=>'0');
|
||||
signal sum_lim : signed(11 downto 0) := (others=>'0');
|
||||
|
||||
begin
|
||||
|
||||
|
||||
process (clk_sys)
|
||||
begin
|
||||
if rising_edge(clk_sys) then
|
||||
clk_snd_r <= clk_snd;
|
||||
clk_ena <= '0';
|
||||
if clk_snd = '1' and clk_snd_r = '0' then
|
||||
clk_ena <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
voices : for kv in 0 to 11 generate
|
||||
process (clk_sys)
|
||||
begin
|
||||
if rising_edge(clk_sys) then
|
||||
|
||||
trigger_r(kv) <= trigger(kv);
|
||||
|
||||
if clk_ena = '1' then
|
||||
|
||||
cnts(kv) <= cnts(kv) + 1;
|
||||
if cnts(kv) = std_logic_vector(to_unsigned(tons(kv),10)) then
|
||||
cnts(kv) <= (others => '0');
|
||||
freqs(kv) <= not freqs(kv);
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
if trigger(kv) = '1' then
|
||||
amps(kv) <= (others => '1');
|
||||
decays(kv) <= (others => '0');
|
||||
else
|
||||
if amps(kv) > 0 then
|
||||
decays(kv) <= decays(kv) + 1;
|
||||
if decays(kv) = x"4000" then
|
||||
decays(kv) <= (others => '0');
|
||||
amps(kv) <= amps(kv) - (amps(kv) srl 3); -- Exponential decay: A = A - (A >> 3)
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
if freqs(kv) = '1' then
|
||||
levels(kv) <= to_signed(to_integer(amps(kv)),12);
|
||||
else
|
||||
levels(kv) <= -to_signed(to_integer(amps(kv)),12);
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
sum <= ( levels(0) + levels(1) + levels( 2) + levels( 3) +
|
||||
levels(4) + levels(5) + levels( 6) + levels( 7) +
|
||||
levels(8) + levels(9) + levels(10) + levels(11) ) / 8 ;
|
||||
|
||||
sum_lim <= to_signed( 511,12) when sum > to_signed( 511,12)
|
||||
else to_signed(-511,12) when sum < to_signed(-511,12)
|
||||
else sum;
|
||||
|
||||
audio <= std_logic_vector(sum_lim)+std_logic_vector(to_unsigned(512,12));
|
||||
|
||||
end struct;
|
||||
Loading…
x
Reference in New Issue
Block a user