mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-11 23:43:09 +00:00
142 lines
3.3 KiB
VHDL
142 lines
3.3 KiB
VHDL
---------------------------------------------------------------------------------
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-- Naughty Boy sound effect1 by Dar (darfpga@aol.fr) (April 2025)
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-- http://darfpga.blogspot.fr
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---------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.ALL;
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use ieee.numeric_std.all;
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entity naughty_boy_effect1 is
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port(
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clk12 : in std_logic;
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trigger_B54 : in std_logic_vector(1 downto 0);
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snd : out std_logic_vector(1 downto 0)
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); end naughty_boy_effect1;
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architecture struct of naughty_boy_effect1 is
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signal clk_div : std_logic_vector(2 downto 0) := (others => '0');
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signal ena_1p5M : std_logic;
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signal u_c1 : unsigned(15 downto 0) := (others => '0');
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signal u_c2 : unsigned(15 downto 0) := (others => '0');
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signal u_c3 : unsigned(15 downto 0) := (others => '0');
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signal flip1 : std_logic := '0';
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signal flip2 : std_logic := '0';
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begin
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-- Commande
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-- R1 = 10k, C=10e-6 SR=1.5MHz
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-- Charge : VF1 = 65536, k1 = 1172 (R1)
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-- Decharge : VF2 = 2321, k2 = 1172 (R1)
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-- Div = 2^7
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process (clk12)
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variable cnt : unsigned(15 downto 0) := (others => '0');
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begin
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if rising_edge(clk12) then
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clk_div <= clk_div + 1;
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ena_1p5M <= '0';
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if clk_div = "111" then
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clk_div <= (others => '0');
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ena_1p5M <= '1';
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end if;
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end if;
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end process;
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process (clk12)
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variable cnt : unsigned(12 downto 0) := (others => '0');
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begin
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if rising_edge(clk12) then
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if ena_1p5M = '1' then
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cnt := cnt + 1;
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if trigger_B54(0) = '1' then
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if cnt > 1172 then
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cnt := (others => '0');
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u_c1 <= u_c1 + (65535 - u_c1)/128;
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end if;
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else
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if cnt > 1172 then
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cnt := (others => '0');
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u_c1 <= u_c1 - (u_c1 - 2321)/128;
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end if;
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end if;
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end if;
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end if;
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end process;
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-- Oscillateur 1
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-- R1 = 10k, R2 = 200k, C=0.01e-6 SR=12MHz
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-- Charge : VF1 = 65535, k1 = 197 (R1+R2)
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-- Decharge : VF2 = 2621, k2 = 188 (R2)
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-- Div = 2^7
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process (clK12)
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variable cnt : unsigned(7 downto 0) := (others => '0');
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begin
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if rising_edge(clk12) then
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if trigger_B54(1) = '0' then
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cnt := (others => '0');
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u_c2 <= (others => '0');
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flip1 <= '0';
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else
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if u_c2 > u_c1 then flip1 <= '0'; end if;
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if u_c2 < u_c1/2 then flip1 <= '1'; end if;
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cnt := cnt + 1;
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if flip1 = '1' then
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if cnt > 197 then
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cnt := (others => '0');
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u_c2 <= u_c2 + (65535 - u_c2)/128;
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end if;
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else
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if cnt > 188 then
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cnt := (others => '0');
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u_c2 <= u_c2 - (u_c2 - 2621)/128;
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end if;
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end if;
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end if;
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end if;
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end process;
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-- Oscillateur 2
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-- R1 = 47k, R2 = 200k, C=0.01e-6 SR=12MHz
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-- Charge : VF1 = 65535, k1 = 232 (R1+R2)
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-- Decharge : VF2 = 2621, k2 = 188 (R2)
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-- Div = 2^7
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process (clK12)
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variable cnt : unsigned(7 downto 0) := (others => '0');
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begin
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if rising_edge(clk12) then
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if trigger_B54(1) = '0' then
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cnt := (others => '0');
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u_c3 <= (others => '0');
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flip2 <= '0';
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else
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if u_c3 > u_c1 then flip2 <= '0'; end if;
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if u_c3 < u_c1/2 then flip2 <= '1'; end if;
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cnt := cnt + 1;
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if flip2 = '1' then
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if cnt > 232 then
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cnt := (others => '0');
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u_c3 <= u_c3 + (65535 - u_c3)/128;
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end if;
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else
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if cnt > 188 then
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cnt := (others => '0');
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u_c3 <= u_c3 - (u_c3 - 2621)/128;
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end if;
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end if;
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end if;
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end if;
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end process;
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snd <= ('0'&flip1)+('0'&flip2);
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end struct;
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