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https://github.com/Gehstock/Mist_FPGA.git
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58 lines
1.5 KiB
VHDL
58 lines
1.5 KiB
VHDL
---------------------------------------------------------------------------------
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-- Naughty boy sound effect4 by Dar (darfpga@aol.fr) (April 2025)
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-- http://darfpga.blogspot.fr
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---------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.ALL;
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use ieee.numeric_std.all;
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entity naughty_boy_effect4 is
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port(
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clk12 : in std_logic;
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trigger_A6 : in std_logic;
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trigger_A7 : in std_logic;
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noise : in std_logic;
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snd_A6 : out std_logic_vector(7 downto 0);
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snd_A7 : out std_logic_vector(7 downto 0)
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); end naughty_boy_effect4;
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architecture struct of naughty_boy_effect4 is
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signal u_c1 : unsigned(15 downto 0) := (others => '0');
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begin
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-- Commande1 (A6)
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-- R1 = 330, R2 = 10k, C=10e-6 SR=12MHz
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-- Charge : VF1 = 59507 k1 = 34 (R1)
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-- Decharge : VF2 = 0 k2 = 1031 (R2)
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-- Div = 2^8
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process (clk12)
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variable cnt : unsigned(15 downto 0) := (others => '0');
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begin
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if rising_edge(clk12) then
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cnt := cnt + 1;
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if trigger_A6 = '1' then
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if cnt > 34 then
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cnt := (others => '0');
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u_c1 <= u_c1 + (59507 - u_c1)/256;
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end if;
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else
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if cnt > 1031 then
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cnt := (others => '0');
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u_c1 <= u_c1 - (u_c1 - 0)/256;
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end if;
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end if;
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end if;
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end process;
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-- chop u_C3 voltage with noise
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snd_A6 <= std_logic_vector(u_c1(15 downto 8)) when noise = '1' else (others => '0');
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-- chop trigger A7 with noise
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snd_A7 <= (others => '1') when trigger_A7 ='1' and noise = '1' else (others => '0');
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end struct; |