mirror of
https://github.com/Gehstock/Mist_FPGA.git
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111 lines
2.9 KiB
VHDL
111 lines
2.9 KiB
VHDL
---------------------------------------------------------------------------------
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-- TMS3615 by Dar (darfpga@aol.fr) (April 2025)
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-- http://darfpga.blogspot.fr
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---------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.ALL;
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use ieee.numeric_std.all;
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entity tms3615 is
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port(
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clk_sys : in std_logic;
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clk_snd : in std_logic;
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trigger : in std_logic_vector(12 downto 0);
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audio : out std_logic_vector(11 downto 0)
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); end tms3615;
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architecture struct of tms3615 is
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type ton_array is array(0 to 12) of integer range 956 downto 478;
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constant tons : ton_array := (956,902,852,804,758,716,676,638,602,568,536,506,478);
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type cnt_array is array(0 to 12) of std_logic_vector(9 downto 0);
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signal cnts : cnt_array := (others => (others => '0'));
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signal freqs : std_logic_vector(12 downto 0) := "0000000000000";
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type amp_array is array(0 to 12) of unsigned(6 downto 0);
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signal amps : amp_array := (others => (others => '0'));
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type level_array is array(0 to 12) of signed(11 downto 0);
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signal levels : level_array := (others => (others => '0'));
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type decay_array is array(0 to 12) of std_logic_vector(15 downto 0);
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signal decays : decay_array := (others => (others => '0'));
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signal trigger_r : std_logic_vector(12 downto 0);
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signal clk_snd_r : std_logic;
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signal clk_ena : std_logic;
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signal sum : signed(11 downto 0) := (others=>'0');
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signal sum_lim : signed(11 downto 0) := (others=>'0');
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begin
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process (clk_sys)
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begin
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if rising_edge(clk_sys) then
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clk_snd_r <= clk_snd;
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clk_ena <= '0';
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if clk_snd = '1' and clk_snd_r = '0' then
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clk_ena <= '1';
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end if;
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end if;
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end process;
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voices : for kv in 0 to 11 generate
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process (clk_sys)
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begin
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if rising_edge(clk_sys) then
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trigger_r(kv) <= trigger(kv);
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if clk_ena = '1' then
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cnts(kv) <= cnts(kv) + 1;
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if cnts(kv) = std_logic_vector(to_unsigned(tons(kv),10)) then
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cnts(kv) <= (others => '0');
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freqs(kv) <= not freqs(kv);
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end if;
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end if;
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if trigger(kv) = '1' then
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amps(kv) <= (others => '1');
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decays(kv) <= (others => '0');
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else
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if amps(kv) > 0 then
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decays(kv) <= decays(kv) + 1;
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if decays(kv) = x"4000" then
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decays(kv) <= (others => '0');
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amps(kv) <= amps(kv) - (amps(kv) srl 3); -- Exponential decay: A = A - (A >> 3)
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end if;
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end if;
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end if;
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if freqs(kv) = '1' then
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levels(kv) <= to_signed(to_integer(amps(kv)),12);
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else
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levels(kv) <= -to_signed(to_integer(amps(kv)),12);
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end if;
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end if;
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end process;
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end generate;
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sum <= ( levels(0) + levels(1) + levels( 2) + levels( 3) +
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levels(4) + levels(5) + levels( 6) + levels( 7) +
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levels(8) + levels(9) + levels(10) + levels(11) ) / 8 ;
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sum_lim <= to_signed( 511,12) when sum > to_signed( 511,12)
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else to_signed(-511,12) when sum < to_signed(-511,12)
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else sum;
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audio <= std_logic_vector(sum_lim)+std_logic_vector(to_unsigned(512,12));
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end struct; |