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https://github.com/Gehstock/Mist_FPGA.git
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60 lines
982 B
Verilog
60 lines
982 B
Verilog
module RESET_DE(
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CLK, // 50MHz
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SYS_RESET_N,
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RESET_N, // 50MHz/32/65536
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RESET_AHEAD_N // 提前恢复，可以接 FLASH_RESET_N
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);
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input CLK;
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input SYS_RESET_N;
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output RESET_N;
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output RESET_AHEAD_N;
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wire RESET_N;
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wire RESET_AHEAD_N;
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reg [5:0] CLK_CNT;
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reg [16:0] RESET_COUNT;
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wire RESET_COUNT_CLK;
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wire RESET_DE_N;
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wire RESET_AHEAD_DE_N;
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assign RESET_COUNT_CLK = CLK_CNT[5];
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assign RESET_DE_N = RESET_COUNT[16]!=1'b0;
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assign RESET_N = SYS_RESET_N && RESET_DE_N;
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assign RESET_AHEAD_DE_N = RESET_COUNT[16:15]!=2'b00;
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assign RESET_AHEAD_N = SYS_RESET_N && RESET_AHEAD_DE_N;
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`ifdef SIMULATE
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initial
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begin
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CLK_CNT = 6'b0;
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end
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`endif
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// 50MHz/32 = 1.5625MHz
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always @ (posedge CLK)
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CLK_CNT <= CLK_CNT+1;
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// 50MHz/32/65536 = 23.84HZ
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always @ (posedge RESET_COUNT_CLK or negedge SYS_RESET_N)
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begin
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if(~SYS_RESET_N)
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begin
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RESET_COUNT <= 17'h00000;
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end
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else
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begin
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if(RESET_COUNT!=17'h10000)
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RESET_COUNT <= RESET_COUNT+1;
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end
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end
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endmodule
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