mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-03-25 17:48:46 +00:00
Laser 310 Snapshot
This commit is contained in:
Marcel
@@ -161,4 +161,5 @@ set_global_assignment -name VHDL_FILE src/T80.vhd
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set_global_assignment -name VHDL_FILE src/T80_ALU.vhd
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set_global_assignment -name VHDL_FILE src/T80_Reg.vhd
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set_global_assignment -name VHDL_FILE src/T80_MCode.vhd
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set_global_assignment -name VHDL_FILE src/invaders_video.vhd
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@@ -0,0 +1,127 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity invaders_video is
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port(
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Video : in std_logic;
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Overlay : in std_logic;
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CLK : in std_logic;
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Rst_n_s : in std_logic;
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HSync : in std_logic;
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VSync : in std_logic;
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O_VIDEO_R : out std_logic;
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O_VIDEO_G : out std_logic;
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O_VIDEO_B : out std_logic;
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O_HSYNC : out std_logic;
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O_VSYNC : out std_logic
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);
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end invaders_video;
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architecture rtl of invaders_video is
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signal HCnt : std_logic_vector(11 downto 0);
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signal VCnt : std_logic_vector(11 downto 0);
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signal HSync_t1 : std_logic;
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signal Overlay_G1 : boolean;
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signal Overlay_G2 : boolean;
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signal Overlay_R1 : boolean;
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signal Overlay_G1_VCnt : boolean;
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signal VideoRGB : std_logic_vector(2 downto 0);
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begin
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process (Rst_n_s, Clk)
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variable cnt : unsigned(3 downto 0);
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begin
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if Rst_n_s = '0' then
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cnt := "0000";
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elsif Clk'event and Clk = '1' then
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if cnt = 9 then
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cnt := "0000";
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else
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cnt := cnt + 1;
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end if;
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end if;
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end process;
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p_overlay : process(Rst_n_s, Clk)
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variable HStart : boolean;
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begin
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if Rst_n_s = '0' then
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HCnt <= (others => '0');
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VCnt <= (others => '0');
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HSync_t1 <= '0';
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Overlay_G1_VCnt <= false;
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Overlay_G1 <= false;
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Overlay_G2 <= false;
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Overlay_R1 <= false;
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elsif Clk'event and Clk = '1' then
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HSync_t1 <= HSync;
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HStart := (HSync_t1 = '0') and (HSync = '1');
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if HStart then
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HCnt <= (others => '0');
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else
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HCnt <= HCnt + "1";
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end if;
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if (VSync = '0') then
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VCnt <= (others => '0');
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elsif HStart then
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VCnt <= VCnt + "1";
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end if;
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if HStart then
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if (Vcnt = x"1F") then
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Overlay_G1_VCnt <= true;
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elsif (Vcnt = x"95") then
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Overlay_G1_VCnt <= false;
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end if;
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end if;
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if (HCnt = x"027") and Overlay_G1_VCnt then
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Overlay_G1 <= true;
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elsif (HCnt = x"046") then
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Overlay_G1 <= false;
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end if;
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if (HCnt = x"046") then
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Overlay_G2 <= true;
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elsif (HCnt = x"0B6") then
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Overlay_G2 <= false;
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end if;
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if (HCnt = x"1A6") then
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Overlay_R1 <= true;
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elsif (HCnt = x"1E6") then
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Overlay_R1 <= false;
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end if;
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end if;
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end process;
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p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1)
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begin
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if (Video = '0') then
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VideoRGB <= "000";
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else
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if Overlay_G1 or Overlay_G2 then
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VideoRGB <= "010";
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elsif Overlay_R1 then
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VideoRGB <= "100";
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else
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VideoRGB <= "111";
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end if;
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end if;
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end process;
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O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
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O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
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O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
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O_HSYNC <= not HSync;
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O_VSYNC <= not VSync;
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end;
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@@ -10,9 +10,9 @@ package platform_variant_pkg is
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--Test Area
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--$0000
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constant ROM_0_NAME : string := "../roms/jatrespecter.hex";
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constant ROM_0_NAME : string := "../roms/lrescue0.hex";
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--$4000
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constant ROM_1_NAME : string := "";
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constant ROM_1_NAME : string := "../roms/lrescue1.hex";
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constant VRAM_NAME : string := "../roms/sivram.hex";
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@@ -0,0 +1,692 @@
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2014 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
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# Date created = 13:56:11 June 04, 2019
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#
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# -------------------------------------------------------------------------- #
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#
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# Note:
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#
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# 1) Do not modify this file. This file was generated
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# automatically by the Quartus II software and is used
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# to preserve global assignments across Quartus II versions.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
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set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
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set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
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set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
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set_global_assignment -name SMART_RECOMPILE Off
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set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
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set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
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set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
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set_global_assignment -name HC_OUTPUT_DIR hc_output
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set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
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set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
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set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
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set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
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set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
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set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
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set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
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set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
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set_global_assignment -name REVISION_TYPE Base
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set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
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set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
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set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
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set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
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set_global_assignment -name DO_COMBINED_ANALYSIS Off
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set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT On
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set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
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set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
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||||
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
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||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
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||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
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||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
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||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
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set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
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set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
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set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
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set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
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set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
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set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
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set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
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set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
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set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
|
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set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
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set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
|
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set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
|
||||
set_global_assignment -name MUX_RESTRUCTURE Auto
|
||||
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
|
||||
set_global_assignment -name ENABLE_IP_DEBUG Off
|
||||
set_global_assignment -name SAVE_DISK_SPACE On
|
||||
set_global_assignment -name DISABLE_OCP_HW_EVAL Off
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
|
||||
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
|
||||
set_global_assignment -name FAMILY "Cyclone IV GX"
|
||||
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
|
||||
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
|
||||
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
|
||||
set_global_assignment -name SAFE_STATE_MACHINE Off
|
||||
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
|
||||
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
|
||||
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
|
||||
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
|
||||
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
|
||||
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
|
||||
set_global_assignment -name PARALLEL_SYNTHESIS On
|
||||
set_global_assignment -name DSP_BLOCK_BALANCING Auto
|
||||
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
|
||||
set_global_assignment -name NOT_GATE_PUSH_BACK On
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
|
||||
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
|
||||
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
|
||||
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
|
||||
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
|
||||
set_global_assignment -name IGNORE_SOFT_BUFFERS On
|
||||
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
|
||||
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
|
||||
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
|
||||
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
|
||||
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
|
||||
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
|
||||
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
|
||||
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
|
||||
set_global_assignment -name AUTO_LCELL_INSERTION On
|
||||
set_global_assignment -name CARRY_CHAIN_LENGTH 48
|
||||
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
|
||||
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
|
||||
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
|
||||
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
|
||||
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
|
||||
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
|
||||
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
|
||||
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
|
||||
set_global_assignment -name AUTO_CARRY_CHAINS On
|
||||
set_global_assignment -name AUTO_CASCADE_CHAINS On
|
||||
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
|
||||
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
|
||||
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
|
||||
set_global_assignment -name AUTO_ROM_RECOGNITION On
|
||||
set_global_assignment -name AUTO_RAM_RECOGNITION On
|
||||
set_global_assignment -name AUTO_DSP_RECOGNITION On
|
||||
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
|
||||
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
||||
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
|
||||
set_global_assignment -name STRICT_RAM_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
|
||||
set_global_assignment -name FORCE_SYNCH_CLEAR Off
|
||||
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
|
||||
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
|
||||
set_global_assignment -name AUTO_RESOURCE_SHARING Off
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
|
||||
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
|
||||
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
|
||||
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
|
||||
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
|
||||
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
|
||||
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
|
||||
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
|
||||
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
|
||||
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
|
||||
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
|
||||
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
|
||||
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
|
||||
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
|
||||
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
|
||||
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
|
||||
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
|
||||
set_global_assignment -name SYNTHESIS_EFFORT Auto
|
||||
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
|
||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
|
||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
|
||||
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
|
||||
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
|
||||
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
|
||||
set_global_assignment -name SYNTHESIS_SEED 1
|
||||
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
|
||||
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
|
||||
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
|
||||
set_global_assignment -name AUTO_MERGE_PLLS On
|
||||
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
|
||||
set_global_assignment -name TXPMA_SLEW_RATE Low
|
||||
set_global_assignment -name ADCE_ENABLED Auto
|
||||
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
|
||||
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
|
||||
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
|
||||
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
|
||||
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
|
||||
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
|
||||
set_global_assignment -name DEVICE AUTO
|
||||
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
|
||||
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
|
||||
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
|
||||
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
|
||||
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
|
||||
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
|
||||
set_global_assignment -name STRATIX_UPDATE_MODE Standard
|
||||
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE Standard
|
||||
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
|
||||
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
|
||||
set_global_assignment -name CVP_MODE Off
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name USER_START_UP_CLOCK Off
|
||||
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
|
||||
set_global_assignment -name ENABLE_VREFA_PIN Off
|
||||
set_global_assignment -name ENABLE_VREFB_PIN Off
|
||||
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
|
||||
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
|
||||
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
|
||||
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
|
||||
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
|
||||
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
|
||||
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
|
||||
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
|
||||
set_global_assignment -name ENABLE_NCE_PIN On
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
|
||||
set_global_assignment -name CRC_ERROR_CHECKING Off
|
||||
set_global_assignment -name INTERNAL_SCRUBBING Off
|
||||
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
|
||||
set_global_assignment -name PR_READY_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_CVP_CONFDONE Off
|
||||
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
|
||||
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
|
||||
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
|
||||
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
|
||||
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
|
||||
set_global_assignment -name OPTIMIZE_SSN Off
|
||||
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
|
||||
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
|
||||
set_global_assignment -name ECO_REGENERATE_REPORT Off
|
||||
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
|
||||
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
|
||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
|
||||
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
|
||||
set_global_assignment -name SEED 1
|
||||
set_global_assignment -name SLOW_SLEW_RATE Off
|
||||
set_global_assignment -name PCI_IO Off
|
||||
set_global_assignment -name VREF_MODE EXTERNAL
|
||||
set_global_assignment -name TURBO_BIT On
|
||||
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
|
||||
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
|
||||
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
|
||||
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS Off
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
|
||||
set_global_assignment -name NORMAL_LCELL_INSERT On
|
||||
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
|
||||
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
|
||||
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
|
||||
set_global_assignment -name AUTO_TURBO_BIT ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
|
||||
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
|
||||
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
|
||||
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
|
||||
set_global_assignment -name FITTER_EFFORT "Auto Fit"
|
||||
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
|
||||
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
|
||||
set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
|
||||
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
|
||||
set_global_assignment -name AUTO_GLOBAL_CLOCK On
|
||||
set_global_assignment -name AUTO_GLOBAL_OE On
|
||||
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
|
||||
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
|
||||
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
|
||||
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
|
||||
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
|
||||
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
|
||||
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
|
||||
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
|
||||
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
|
||||
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_LARGE_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
|
||||
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
|
||||
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
|
||||
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
|
||||
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
|
||||
set_global_assignment -name PR_DONE_OPEN_DRAIN On
|
||||
set_global_assignment -name NCEO_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
|
||||
set_global_assignment -name ENABLE_PR_PINS Off
|
||||
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
|
||||
set_global_assignment -name CLAMPING_DIODE Off
|
||||
set_global_assignment -name TRI_STATE_SPI_PINS Off
|
||||
set_global_assignment -name UNUSED_TSD_PINS_GND Off
|
||||
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
|
||||
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
|
||||
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
|
||||
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
|
||||
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
|
||||
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
|
||||
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
|
||||
set_global_assignment -name COMPRESSION_MODE Off
|
||||
set_global_assignment -name CLOCK_SOURCE Internal
|
||||
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
|
||||
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
|
||||
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
||||
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
|
||||
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
||||
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
|
||||
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
|
||||
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
|
||||
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
|
||||
set_global_assignment -name SECURITY_BIT Off
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
|
||||
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
|
||||
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
|
||||
set_global_assignment -name GENERATE_TTF_FILE Off
|
||||
set_global_assignment -name GENERATE_RBF_FILE Off
|
||||
set_global_assignment -name GENERATE_HEX_FILE Off
|
||||
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
|
||||
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
|
||||
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
|
||||
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
|
||||
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
|
||||
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
|
||||
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off
|
||||
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
|
||||
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
|
||||
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
|
||||
set_global_assignment -name START_TIME 0ns
|
||||
set_global_assignment -name SIMULATION_MODE TIMING
|
||||
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
|
||||
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
|
||||
set_global_assignment -name SETUP_HOLD_DETECTION Off
|
||||
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
|
||||
set_global_assignment -name CHECK_OUTPUTS Off
|
||||
set_global_assignment -name SIMULATION_COVERAGE On
|
||||
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name GLITCH_DETECTION Off
|
||||
set_global_assignment -name GLITCH_INTERVAL 1ns
|
||||
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
|
||||
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
|
||||
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
|
||||
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
|
||||
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
|
||||
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
|
||||
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
|
||||
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
|
||||
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
|
||||
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
|
||||
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
|
||||
set_global_assignment -name DRC_TOP_FANOUT 50
|
||||
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
|
||||
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
|
||||
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
|
||||
set_global_assignment -name ENABLE_DRC_SETTINGS Off
|
||||
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
|
||||
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
|
||||
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
|
||||
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
|
||||
set_global_assignment -name MERGE_HEX_FILE Off
|
||||
set_global_assignment -name GENERATE_SVF_FILE Off
|
||||
set_global_assignment -name GENERATE_ISC_FILE Off
|
||||
set_global_assignment -name GENERATE_JAM_FILE Off
|
||||
set_global_assignment -name GENERATE_JBC_FILE Off
|
||||
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
|
||||
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
|
||||
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
|
||||
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
|
||||
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
|
||||
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
|
||||
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
|
||||
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
|
||||
set_global_assignment -name POWER_USE_PVA On
|
||||
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
|
||||
set_global_assignment -name POWER_USE_INPUT_FILES Off
|
||||
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
|
||||
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
|
||||
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
|
||||
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
|
||||
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
|
||||
set_global_assignment -name POWER_TJ_VALUE 25
|
||||
set_global_assignment -name POWER_USE_TA_VALUE 25
|
||||
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
|
||||
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
|
||||
set_global_assignment -name POWER_HPS_ENABLE Off
|
||||
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
|
||||
set_global_assignment -name IGNORE_PARTITIONS Off
|
||||
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
|
||||
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
|
||||
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
|
||||
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
|
||||
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
|
||||
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
|
||||
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
|
||||
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
|
||||
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
|
||||
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
|
||||
set_global_assignment -name EQC_BBOX_MERGE On
|
||||
set_global_assignment -name EQC_LVDS_MERGE On
|
||||
set_global_assignment -name EQC_RAM_UNMERGING On
|
||||
set_global_assignment -name EQC_DFF_SS_EMULATION On
|
||||
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
|
||||
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
|
||||
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
|
||||
set_global_assignment -name EQC_STRUCTURE_MATCHING On
|
||||
set_global_assignment -name EQC_AUTO_BREAK_CONE On
|
||||
set_global_assignment -name EQC_POWER_UP_COMPARE Off
|
||||
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
|
||||
set_global_assignment -name EQC_AUTO_INVERSION On
|
||||
set_global_assignment -name EQC_AUTO_TERMINATE On
|
||||
set_global_assignment -name EQC_SUB_CONE_REPORT Off
|
||||
set_global_assignment -name EQC_RENAMING_RULES On
|
||||
set_global_assignment -name EQC_PARAMETER_CHECK On
|
||||
set_global_assignment -name EQC_AUTO_PORTSWAP On
|
||||
set_global_assignment -name EQC_DETECT_DONT_CARES On
|
||||
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
|
||||
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
|
||||
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
|
||||
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
|
||||
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
|
||||
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
|
||||
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
|
||||
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
|
||||
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
|
||||
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
|
||||
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
|
||||
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
|
||||
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
|
||||
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
|
||||
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
|
||||
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
|
||||
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
|
||||
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
|
||||
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
|
||||
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
|
||||
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
|
||||
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
|
||||
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
|
||||
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
|
||||
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
|
||||
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
|
||||
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
|
||||
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
|
||||
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
|
||||
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
|
||||
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
|
||||
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
|
||||
Binary file not shown.
Binary file not shown.
@@ -3,7 +3,7 @@ module invaders_memory(
|
||||
input Clock,
|
||||
input RW_n,
|
||||
input [15:0]Addr,
|
||||
input [12:0]Ram_Addr,
|
||||
input [15:0]Ram_Addr,
|
||||
output [7:0]Ram_out,
|
||||
input [7:0]Ram_in,
|
||||
output [7:0]Rom_out
|
||||
@@ -27,11 +27,13 @@ sprom #(
|
||||
`ifdef invaders .init_file("./roms/SpaceInvaders/invaders_h.hex"), `endif//working
|
||||
`ifdef gunfight .init_file("./roms/Gunfight/7609_e.hex"), `endif//not working
|
||||
`ifdef supearth .init_file("./roms/SuperEarthInvasion/earthinv_h.hex"), `endif//working
|
||||
`ifdef seawolf .init_file("./roms/Seawolf/sw0041_h.hex"), `endif//not working
|
||||
`ifdef seawolf .init_file("./roms/Seawolf/hg.hex"), `endif//not working
|
||||
`ifdef dogpatch .init_file("./roms/Dogpatch/dogpatch_h.hex"), `endif//not working
|
||||
`ifdef jspecter .init_file("./roms/jspecter/rom_h.hex"), `endif//not working
|
||||
`ifdef invadrev .init_file("./roms/InvadersRevenge/invrvnge_e.hex"), `endif//not
|
||||
`ifdef blueshark .init_file("./roms/BlueShark/blueshrk_h.hex"), `endif//
|
||||
`ifdef spacewalk .init_file("./roms/Spacewalk/hg.hex"), `endif
|
||||
`ifdef extrainning .init_file("./roms/ExtraInning/ei.h.hex"), `endif
|
||||
`ifdef zzzap280 .widthad_a(10), `endif//
|
||||
`ifdef generic .widthad_a(11), `endif//
|
||||
// .widthad_a(11),
|
||||
@@ -51,11 +53,13 @@ sprom #(
|
||||
`ifdef invaders .init_file("./roms/SpaceInvaders/invaders_g.hex"), `endif
|
||||
`ifdef gunfight .init_file("./roms/Gunfight/7609_f.hex"), `endif//not working
|
||||
`ifdef supearth .init_file("./roms/SuperEarthInvasion/earthinv_g.hex"), `endif//working
|
||||
`ifdef seawolf .init_file("./roms/Seawolf/sw0042_g.hex"), `endif//not working
|
||||
`ifdef seawolf .init_file("./roms/Seawolf/fe.hex"), `endif//not working
|
||||
`ifdef dogpatch .init_file("./roms/Dogpatch/dogpatch_g.hex"), `endif//not working
|
||||
`ifdef jspecter .init_file("./roms/jspecter/rom_g.hex"), `endif//not working
|
||||
`ifdef invadrev .init_file("./roms/InvadersRevenge/invrvnge_f.hex"), `endif//not working
|
||||
`ifdef blueshark .init_file("./roms/BlueShark/blueshrk_g.hex"), `endif//
|
||||
`ifdef spacewalk .init_file("./roms/Spacewalk/fe.hex"), `endif
|
||||
`ifdef extrainning .init_file("./roms/ExtraInning/ei.g.hex"), `endif
|
||||
`ifdef zzzap280 .widthad_a(10), `endif//
|
||||
`ifdef generic .widthad_a(11), `endif//
|
||||
// .widthad_a(11),
|
||||
@@ -67,6 +71,7 @@ u_rom_g (
|
||||
.q(rom_data_1)
|
||||
);
|
||||
|
||||
`ifndef seawolf
|
||||
sprom #(
|
||||
`ifdef sflush .init_file("./roms/Strightflush/fr03_sc4.hex"), `endif//
|
||||
`ifdef zzzap280 .init_file("./roms/280zzz/zzzap_e.hex"), `endif//
|
||||
@@ -75,11 +80,13 @@ sprom #(
|
||||
`ifdef invaders .init_file("./roms/SpaceInvaders/invaders_f.hex"), `endif
|
||||
`ifdef gunfight .init_file("./roms/Gunfight/7609_g.hex"), `endif//not working
|
||||
`ifdef supearth .init_file("./roms/SuperEarthInvasion/earthinv_f.hex"), `endif//working
|
||||
`ifdef seawolf .init_file("./roms/Seawolf/sw0043_f.hex"), `endif//not working
|
||||
|
||||
`ifdef dogpatch .init_file("./roms/Dogpatch/dogpatch_f.hex"), `endif//not working
|
||||
`ifdef jspecter .init_file("./roms/jspecter/rom_f.hex"), `endif//not working
|
||||
`ifdef invadrev .init_file("./roms/InvadersRevenge/invrvnge_g.hex"), `endif//not working
|
||||
`ifdef blueshark .init_file("./roms/BlueShark/blueshrk_f.hex"), `endif//
|
||||
`ifdef spacewalk .init_file("./roms/Spacewalk/dc.hex"), `endif
|
||||
`ifdef extrainning .init_file("./roms/ExtraInning/ei.f.hex"), `endif
|
||||
`ifdef zzzap280 .widthad_a(10), `endif//
|
||||
`ifdef generic .widthad_a(11), `endif//
|
||||
// .widthad_a(11),
|
||||
@@ -100,10 +107,12 @@ sprom #(
|
||||
`ifdef invaders .init_file("./roms/SpaceInvaders/invaders_e.hex"), `endif
|
||||
`ifdef gunfight .init_file("./roms/Gunfight/7609_h.hex"), `endif//not working
|
||||
`ifdef supearth .init_file("./roms/SuperEarthInvasion/earthinv_e.hex"), `endif//working
|
||||
`ifdef seawolf .init_file("./roms/Seawolf/sw0044_e.hex"), `endif//not working
|
||||
|
||||
`ifdef dogpatch .init_file("./roms/Dogpatch/dogpatch_e.hex"), `endif//not working
|
||||
`ifdef jspecter .init_file("./roms/jspecter/rom_e.hex"), `endif//not working
|
||||
`ifdef invadrev .init_file("./roms/InvadersRevenge/invrvnge_h.hex"), `endif//not working
|
||||
`ifdef spacewalk .init_file("./roms/Spacewalk/ba.hex"), `endif
|
||||
`ifdef extrainning .init_file("./roms/ExtraInning/ei.e.hex"), `endif
|
||||
`ifdef zzzap280 .widthad_a(10), `endif//
|
||||
`ifdef generic .widthad_a(11), `endif//
|
||||
.width_a(8))
|
||||
@@ -113,12 +122,15 @@ u_rom_e (
|
||||
`ifdef generic .Address(Addr[10:0]), `endif
|
||||
.q(rom_data_3)
|
||||
);
|
||||
`endif//
|
||||
`ifndef generic
|
||||
`endif//
|
||||
|
||||
//`ifndef generic
|
||||
`ifdef extrainning
|
||||
sprom #(
|
||||
`ifdef sflush .init_file("./roms/Strightflush/fr05_sc2.hex"), `endif//
|
||||
`ifdef zzzap280 .init_file("./roms/280zzz/zzzap_g.hex"), `endif//
|
||||
`ifdef lrescue .init_file("./roms/LunarRescue/lrescue_5.hex"), `endif
|
||||
`ifdef extrainning .init_file("./roms/ExtraInning/ei.b.hex"), `endif
|
||||
`ifdef zzzap280 .widthad_a(10), `endif//
|
||||
`ifdef generic .widthad_a(11), `endif//
|
||||
.width_a(8))
|
||||
@@ -128,6 +140,9 @@ u_rom_i (
|
||||
`ifdef generic .Address(Addr[10:0]), `endif
|
||||
.q(rom_data_4)
|
||||
);
|
||||
`endif//extrainning
|
||||
`ifndef generic
|
||||
|
||||
|
||||
sprom #(
|
||||
`ifdef zzzap280 .init_file("./roms/280zzz/zzzap_h.hex"), `endif//
|
||||
@@ -142,6 +157,7 @@ u_rom_j (
|
||||
.q(rom_data_5)
|
||||
);
|
||||
`endif//
|
||||
`endif//
|
||||
always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5, rom_data_6, rom_data_7) begin
|
||||
Rom_out = 8'b00000000;
|
||||
case (Addr[13:11])
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE pinplan>
|
||||
<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
|
||||
<global>
|
||||
<pin name="inclk0" direction="input" scope="external" source="clock" />
|
||||
<pin name="c0" direction="output" scope="external" source="clock" />
|
||||
<pin name="c1" direction="output" scope="external" source="clock" />
|
||||
|
||||
</global>
|
||||
</pinplan>
|
||||
Binary file not shown.
@@ -0,0 +1,129 @@
|
||||
:10000000190107200103200C501BD01A0208205CA4
|
||||
:1000100050126E2000E0202020E1129C2040E020C1
|
||||
:100020008001E112CA2080E020E020E112F8208067
|
||||
:10003000FF0CC850E212262138FF0CA02EE2125409
|
||||
:100040002120FF0C582EE212822100FF0C3050E2DA
|
||||
:1000500012B02160FF0C817AE2072051126E2090CD
|
||||
:10006000E0202020F1129C20C0E0208001F112CA83
|
||||
:1000700020E0E020E020F112F820FFFF0CC850F251
|
||||
:10008000122621E0FF0CA02EF2125421D0FF0C58B2
|
||||
:100090002EF212822180FF0C3050F212B021A0FF0C
|
||||
:1000A0000C817AF207205107020820E850136E20D5
|
||||
:1000B0003090E2E1139C2030D0E2E113CA2030E01E
|
||||
:1000C000E2E113F82008FFFFE213262108E0FFE237
|
||||
:1000D00013542108D0FFE21382210880FFE213B0FD
|
||||
:1000E0002108A0FFE2072051136E203000E2F11337
|
||||
:1000F0009C203040E2F113CA203080E2F113F82056
|
||||
:100100000880FFF21326210838FFF213542108203B
|
||||
:10011000FFF21382210810FFF213B0210860FFF2F2
|
||||
:10012000198061201C09181499040F3D148F04389C
|
||||
:1001300034148F040F2D148F0426341A021C160158
|
||||
:1001400008204B5115048003D8390915078503D6BB
|
||||
:100150003909091900662019000620161900E12244
|
||||
:100160001905602015026C031A381900E1221900E4
|
||||
:10017000232315076C038D26150963030B261AA08C
|
||||
:1001800052191E61201C15096C030B26191E6120D3
|
||||
:100190001C076E51171AA0521AF9110826510800AF
|
||||
:1001A000501508780301261901FE2212962280D8E4
|
||||
:1001B000207D78E01C13962220C453E01C13962265
|
||||
:1001C00020DC23E01C13962220BC17E0150B5803FB
|
||||
:1001D00014261C139622209C31E01C139622207CAE
|
||||
:1001E00004E01C139622205431E01C139622201C9C
|
||||
:1001F00023C01C139622202C53C01C139622207D52
|
||||
:100200007DC01C193C61201C08A850193C61201CB1
|
||||
:100210000794511900E122193C61201C08A85019CB
|
||||
:100220003C61201C074552171A5714170111203A38
|
||||
:10023000521539DF030028074052152C1804002CF2
|
||||
:1002400019FF61201C1708265108005019000720CB
|
||||
:10025000190A6220010620CC1D193C662007CC1D1E
|
||||
:100260001120000A77197719030A77197719030AF9
|
||||
:1002700077197719030A77197719030A7719771904
|
||||
:10028000030A77197719030A77197719030A771977
|
||||
:100290007719030A77197719030A7719771903C9A8
|
||||
:1002A0002134200607AF772305C2A652C9530D0A91
|
||||
:1002B00042414C4C440945515509353048093B42AF
|
||||
:1002C000414C4C204449535420464F5220504954ED
|
||||
:1002D00043480D0A42504F530945515509343409DA
|
||||
:1002E0003B4241542041444445520D0A5345430981
|
||||
:1002F0004551550936300D0A3B20504F5254530D8D
|
||||
:100300000A534150094551550931093B5348494663
|
||||
:100310005420414D540D0A534E445009455155093E
|
||||
:1003200033093B534F554E44530D0A534F50094523
|
||||
:1003300051550932093B53484946542044415441E0
|
||||
:100340000D0A534950094551550933093B53484952
|
||||
:10035000465420494E0D0A5032495009455155091D
|
||||
:1003600030093B504C4159455220320D0A534554F7
|
||||
:1003700050094551550932093B4F50455241544FA0
|
||||
:10038000522053455454494E47530D0A5031495059
|
||||
:10039000094551550931093B504C415945522031CD
|
||||
:1003A0000D0A4D555031094551550935093B204D30
|
||||
:1003B0005553494320504F52540D0A4D5550320960
|
||||
:1003C0004551550936093B20222222222220222291
|
||||
:1003D00022220D0A57444F470945515509340D0A49
|
||||
:1003E0003B534F554E44530D0A43434E5452094517
|
||||
:1003F0005155093330480D0A4741534E4409455180
|
||||
:1004000055093130480D0A3B2054494D45530D0ADA
|
||||
:100410005442414C4C09455155095345432F380925
|
||||
:100420003B42414C4C20534F554E442054494D457E
|
||||
:100430000D0A5448495409455155095345432F362F
|
||||
:1004400030093B48495420534F554E442054494DA0
|
||||
:10045000450D0A544F555409455155095345430913
|
||||
:100460003B4F555420534F554E442054494D450D54
|
||||
:100470000A545354524B09455155095345432F32A1
|
||||
:10048000093B535452494B4520534F554E44205439
|
||||
:10049000494D450D0A5443524443094551550934C9
|
||||
:1004A0002A534543093B43524F574420534F554E1F
|
||||
:1004B000442054494D450D0A3B20504C415945526A
|
||||
:1004C00020504F534954494F4E530D0A585031094B
|
||||
:1004D00045515509304338480D0A595031094551A5
|
||||
:1004E00055093530480D0A585032094551550930E3
|
||||
:1004F0004130480D0A595032094551550932454895
|
||||
:100500000D0A58503309455155093538480D0A59D7
|
||||
:10051000503309455155095950320D0A5850340984
|
||||
:10052000455155092D5850312D3820414E44203029
|
||||
:100530004646480D0A59503409455155095950311C
|
||||
:100540000D0A58503509455155093831480D0A5999
|
||||
:10055000503509455155093741480D0A58504C0945
|
||||
:10056000455155093230480D0A59504C09455155ED
|
||||
:10057000093230480D0A5850430945515509383061
|
||||
:10058000480D0A5950430945515509310D0A585033
|
||||
:100590005209455155092D58504C20414E442030A8
|
||||
:1005A0004646480D0A595052094551550959504C73
|
||||
:1005B0000D0A3B204241534520504F534954494F67
|
||||
:1005C0004E530D0A584231094551550930433948B7
|
||||
:1005D0000D0A59423109455155093735480D0A5818
|
||||
:1005E000423209455155093831480D0A59423209FC
|
||||
:1005F000455155093343480D0A3B2042414C4C209C
|
||||
:10060000544F20504F534954494F4E0D0A584F46AE
|
||||
:1006100046094551550934093B58204F4646534534
|
||||
:100620005420464F522042414C4C0D0A594F4646E9
|
||||
:10063000094551550933093B59204F464653455406
|
||||
:1006400020464F522042414C4C0D0A58425031092D
|
||||
:10065000455155095850312D584F46460D0A5942BB
|
||||
:10066000503109455155095950312B594F46460DC6
|
||||
:100670000A5842503209455155095850322D584FA9
|
||||
:1006800046460D0A594250320945515509595032D2
|
||||
:100690002B594F46460D0A584250330945515509CA
|
||||
:1006A0005850332D584F46460D0A5942503309458C
|
||||
:1006B0005155095950332B594F46460D0A5842504F
|
||||
:1006C0003409455155095850342D584F46460D0AA6
|
||||
:1006D0005942503409455155095950342B594F4608
|
||||
:1006E000460D0A5842503509455155095850352D87
|
||||
:1006F000584F46460D0A594250350945515509593A
|
||||
:1007000050352B594F46460D0A5842504C09455119
|
||||
:10071000550958504C2D584F46460D0A5942504CD9
|
||||
:10072000094551550959504C2B594F46460D0A5809
|
||||
:1007300042504309455155095850432D584F46469C
|
||||
:100740000D0A5942504309455155095950432B59F7
|
||||
:100750004F46460D0A5842505209455155095850C6
|
||||
:10076000522D584F46460D0A59425052094551558F
|
||||
:10077000095950522B594F46460D0A3B2042414CD5
|
||||
:100780004C20504F534954494F4E530D0A58424242
|
||||
:100790003109455155095842312D584F46460D0AE9
|
||||
:1007A0005942423109455155095942312B594F4659
|
||||
:1007B000460D0A5842423209455155095842322DD8
|
||||
:1007C000584F46460D0A594242320945515509597A
|
||||
:1007D00042322B594F46460D0A584242350945517F
|
||||
:1007E00055095850352D584F46460D0A5942423545
|
||||
:1007F00009455155095950352B594F46460D0A3B6D
|
||||
:00000001FF
|
||||
Binary file not shown.
@@ -0,0 +1,129 @@
|
||||
:10000000AC1811000121CA3C3AE422F6A0CD281711
|
||||
:10001000193AE522F6A0CD2817193AE622F6A0C330
|
||||
:10002000281721B53C0106193EFFCDAC18CDA51708
|
||||
:1000300021D53D3ECDCD6A1721D53E3ECCCD6A17A8
|
||||
:1000400021B63D010401AFCDAC1821D53C111320E0
|
||||
:100050003E06CD891721D63D010410AFCDAC182145
|
||||
:10006000DA3D01010F3E7FCDAC1821BA3F360011B9
|
||||
:100070001A2021D63D3E05CD891711202021D63EDC
|
||||
:100080003E05CD891721B53E360021BA3E3600C95E
|
||||
:100090007EE6F0FEA07EC2A118E60FFE0AC2A118FD
|
||||
:1000A000AF812777E6F07EC0F6A077C91E2051E524
|
||||
:1000B00077230DC2B0184A1600E11905C2AE18C95F
|
||||
:1000C000CDF8173A08204F212520AE7977CAFF18BE
|
||||
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|
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:1005E000E5CD2013E1118F3E3E02C31E01002178AC
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:1007F00000C36212EB7EF64077CD7C15110000CD70
|
||||
:00000001FF
|
||||
Binary file not shown.
@@ -0,0 +1,129 @@
|
||||
:100000000000310024C31700FBC9000000000000FD
|
||||
:10001000F5C5D5E5C34C03DB0217DA2000C3660C37
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:1000D00024210C36E5210000110D010100041A1342
|
||||
:1000E00086D304230DC2E00005C2E0003CCAFA003A
|
||||
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|
||||
:1001000000E17DFE0CCA0000D304C30801004828AA
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:10025000663E7E66663E7E66667E3E3C7E66060640
|
||||
:100260000606667E3C3E7E6666666666667E3E7E08
|
||||
:100270007E06063E3E06067E7E7E7E06063E3E06E6
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:1002F0001C3E7E66667E3E766666663C7E66063E92
|
||||
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|
||||
:10031000666666666666667E3C66666666667E3CA1
|
||||
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|
||||
:100330003C18183C7E666666667E3C1818181818CD
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
Binary file not shown.
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Binary file not shown.
@@ -41,7 +41,7 @@
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Invaders_mist.sv
|
||||
@@ -49,13 +49,6 @@ set_global_assignment -name VHDL_FILE rtl/invaders.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/invaders_memory.sv
|
||||
set_global_assignment -name QIP_FILE rtl/pll.qip
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
|
||||
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/osd.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/keyboard.v
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/dac.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/spram.vhd
|
||||
@@ -177,4 +170,6 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
# -------------------------
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu8080.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/invaders_video.vhd
|
||||
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
|
||||
set_global_assignment -name VHDL_FILE rtl/pll.vhd
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
Binary file not shown.
@@ -1,6 +1,6 @@
|
||||
`define generic
|
||||
//`define noDIP
|
||||
`define invaders
|
||||
//`define invaders
|
||||
`ifdef invaders
|
||||
`define dip = 8'b00000000
|
||||
`endif
|
||||
@@ -15,18 +15,21 @@
|
||||
`define dip = 8'b00000000 //untested
|
||||
`endif
|
||||
|
||||
//`define blueshark Sync Problems
|
||||
//`define blueshark //TILT(IMPUTS) //60hz
|
||||
`ifdef blueshark
|
||||
`define dip = "00100100" //todo
|
||||
`endif
|
||||
|
||||
//TODO
|
||||
//`define lrescue
|
||||
`define dip = 8'b00000000
|
||||
`define lrescue
|
||||
|
||||
//`define zzzap280
|
||||
//`define gunfight
|
||||
//`define sflush
|
||||
//`define seawolf
|
||||
//`define seawolf //60hz
|
||||
//`define spacewalk //60hz
|
||||
//`define extrainning
|
||||
//`define dogpatch
|
||||
//`define jspecter
|
||||
//`define invadrev
|
||||
@@ -62,19 +65,25 @@ localparam CONF_STR = {
|
||||
`ifdef invaders "Space Inv.;;", `endif
|
||||
`ifdef supearth "SEarthInv.;;", `endif
|
||||
`ifdef slaser "Space Laser;;", `endif
|
||||
`ifdef blueshark "Blue Shark;;", `endif
|
||||
`ifdef noDIP "Midway 8080.;;", `endif
|
||||
"O2,Joystick Control,Upright,Normal;",
|
||||
"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
|
||||
`ifdef spacewalk "Space Walk;;", `endif
|
||||
`ifdef extrainning "Extra Inn.;;", `endif
|
||||
|
||||
`ifdef blueshark "Blue Shark;;", `endif//NW
|
||||
`ifdef seawolf "Sea Wolf;;", `endif//NW
|
||||
`ifdef noDIP "Midway 8080;;", `endif
|
||||
"O2,Rotate Controls,Off,On;",
|
||||
"O34,Scanlines,Off,25%,50%,75%;",
|
||||
"O5,Overlay, On, Off;",
|
||||
"T6,Reset;",
|
||||
"V,v1.00.",`BUILD_DATE
|
||||
"V,v1.10.",`BUILD_DATE
|
||||
};
|
||||
|
||||
assign LED = 1;
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
|
||||
|
||||
wire clk_sys, clk_mist;
|
||||
wire pll_locked;
|
||||
|
||||
pll pll
|
||||
(
|
||||
.inclk0(CLOCK_27),
|
||||
@@ -90,85 +99,16 @@ wire [31:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire [1:0] switches;
|
||||
wire [7:0] kbjoy;
|
||||
wire [7:0] joystick_0;
|
||||
wire [7:0] joystick_1;
|
||||
wire scandoubler_disable;
|
||||
wire [7:0] joystick_0,joystick_1;
|
||||
wire scandoublerD;
|
||||
wire ypbpr;
|
||||
wire ps2_kbd_clk, ps2_kbd_data;
|
||||
wire [7:0] audio;
|
||||
wire hsync,vsync;
|
||||
assign LED = 1;
|
||||
|
||||
wire hblank, vblank;
|
||||
wire ce_vid;
|
||||
wire hs, vs;
|
||||
wire r,g,b;
|
||||
|
||||
video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
|
||||
(
|
||||
.clk_sys(clk_mist),
|
||||
.ce_pix(clk_sys),
|
||||
.ce_pix_actual(clk_sys),
|
||||
.SPI_SCK(SPI_SCK),
|
||||
.SPI_SS3(SPI_SS3),
|
||||
.SPI_DI(SPI_DI),
|
||||
.R({r,r,r}),
|
||||
.G({g,g,g}),
|
||||
.B({b,b,b}),
|
||||
.HSync(hs),
|
||||
.VSync(vs),
|
||||
.VGA_R(VGA_R),
|
||||
.VGA_G(VGA_G),
|
||||
.VGA_B(VGA_B),
|
||||
.VGA_VS(VGA_VS),
|
||||
.VGA_HS(VGA_HS),
|
||||
.scandoubler_disable(scandoubler_disable),
|
||||
.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
|
||||
.hq2x(status[4:3]==1),
|
||||
.ypbpr_full(1),
|
||||
.line_start(0),
|
||||
.mono(0)
|
||||
);
|
||||
|
||||
mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
|
||||
(
|
||||
.clk_sys (clk_mist ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_SCK (SPI_SCK ),
|
||||
.CONF_DATA0 (CONF_DATA0 ),
|
||||
.SPI_SS2 (SPI_SS2 ),
|
||||
.SPI_DO (SPI_DO ),
|
||||
.SPI_DI (SPI_DI ),
|
||||
.buttons (buttons ),
|
||||
.switches (switches ),
|
||||
.scandoubler_disable(scandoubler_disable),
|
||||
.ypbpr (ypbpr ),
|
||||
.ps2_kbd_clk (ps2_kbd_clk ),
|
||||
.ps2_kbd_data (ps2_kbd_data ),
|
||||
.joystick_0 (joystick_0 ),
|
||||
.joystick_1 (joystick_1 ),
|
||||
.status (status )
|
||||
);
|
||||
|
||||
|
||||
|
||||
keyboard keyboard(
|
||||
.clk(clk_mist),
|
||||
.reset(),
|
||||
.ps2_kbd_clk(ps2_kbd_clk),
|
||||
.ps2_kbd_data(ps2_kbd_data),
|
||||
.joystick(kbjoy)
|
||||
);
|
||||
|
||||
//wire m_up = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3];
|
||||
//wire m_down = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2];
|
||||
wire m_left = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1];
|
||||
wire m_right = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0];
|
||||
|
||||
wire m_fire = kbjoy[0] | joystick_0[4] | joystick_1[4];
|
||||
wire m_start1 = kbjoy[1];
|
||||
wire m_start2 = kbjoy[2];
|
||||
wire m_coin = kbjoy[3];
|
||||
wire key_pressed;
|
||||
wire [7:0] key_code;
|
||||
wire key_strobe;
|
||||
wire [7:0] audio;
|
||||
wire hsync,vsync;
|
||||
wire hs, vs;
|
||||
wire r,g,b;
|
||||
|
||||
wire [15:0]RAB;
|
||||
wire [15:0]AD;
|
||||
@@ -187,9 +127,9 @@ invaderst invaderst(
|
||||
.Rst_n(~(status[0] | status[6] | buttons[1])),
|
||||
.Clk(clk_sys),
|
||||
.ENA(),
|
||||
.Coin(m_coin),
|
||||
.Sel1Player(~m_start1),
|
||||
.Sel2Player(~m_start2),
|
||||
.Coin(btn_coin),
|
||||
.Sel1Player(~btn_one_player),
|
||||
.Sel2Player(~btn_two_players),
|
||||
.Fire(~m_fire),
|
||||
.MoveLeft(~m_left),
|
||||
.MoveRight(~m_right),
|
||||
@@ -239,6 +179,48 @@ invaders_video invaders_video (
|
||||
.O_VSYNC(vs)
|
||||
);
|
||||
|
||||
mist_video #(.COLOR_DEPTH(3)) mist_video(
|
||||
.clk_sys(clk_mist),
|
||||
.SPI_SCK(SPI_SCK),
|
||||
.SPI_SS3(SPI_SS3),
|
||||
.SPI_DI(SPI_DI),
|
||||
.R({r,r,r}),
|
||||
.G({g,g,g}),
|
||||
.B({b,b,b}),
|
||||
.HSync(hs),
|
||||
.VSync(vs),
|
||||
.VGA_R(VGA_R),
|
||||
.VGA_G(VGA_G),
|
||||
.VGA_B(VGA_B),
|
||||
.VGA_VS(VGA_VS),
|
||||
.VGA_HS(VGA_HS),
|
||||
.rotate({1'b0,status[2]}),
|
||||
.scandoubler_disable(scandoublerD),
|
||||
.scanlines(status[4:3]),
|
||||
.ypbpr(ypbpr)
|
||||
);
|
||||
|
||||
user_io #(
|
||||
.STRLEN(($size(CONF_STR)>>3)))
|
||||
user_io(
|
||||
.clk_sys (clk_mist ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_CLK (SPI_SCK ),
|
||||
.SPI_SS_IO (CONF_DATA0 ),
|
||||
.SPI_MISO (SPI_DO ),
|
||||
.SPI_MOSI (SPI_DI ),
|
||||
.buttons (buttons ),
|
||||
.switches (switches ),
|
||||
.scandoubler_disable (scandoublerD ),
|
||||
.ypbpr (ypbpr ),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_code (key_code ),
|
||||
.joystick_0 (joystick_0 ),
|
||||
.joystick_1 (joystick_1 ),
|
||||
.status (status )
|
||||
);
|
||||
|
||||
dac dac (
|
||||
.clk_i(clk_mist),
|
||||
.res_n_i(1),
|
||||
@@ -246,6 +228,38 @@ dac dac (
|
||||
.dac_o(AUDIO_L)
|
||||
);
|
||||
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
wire m_up = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_up | joystick_0[3] | joystick_1[3];
|
||||
wire m_down = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_down | joystick_0[2] | joystick_1[2];
|
||||
wire m_left = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_left | joystick_0[1] | joystick_1[1];
|
||||
wire m_right = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_right | joystick_0[0] | joystick_1[0];
|
||||
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
|
||||
wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
|
||||
reg btn_one_player = 0;
|
||||
reg btn_two_players = 0;
|
||||
reg btn_left = 0;
|
||||
reg btn_right = 0;
|
||||
reg btn_down = 0;
|
||||
reg btn_up = 0;
|
||||
reg btn_fire1 = 0;
|
||||
reg btn_fire2 = 0;
|
||||
reg btn_fire3 = 0;
|
||||
reg btn_coin = 0;
|
||||
|
||||
always @(posedge clk_mist) begin
|
||||
if(key_strobe) begin
|
||||
case(key_code)
|
||||
'h75: btn_up <= key_pressed; // up
|
||||
'h72: btn_down <= key_pressed; // down
|
||||
'h6B: btn_left <= key_pressed; // left
|
||||
'h74: btn_right <= key_pressed; // right
|
||||
'h76: btn_coin <= key_pressed; // ESC
|
||||
'h05: btn_one_player <= key_pressed; // F1
|
||||
'h06: btn_two_players <= key_pressed; // F2
|
||||
'h14: btn_fire3 <= key_pressed; // ctrl
|
||||
'h11: btn_fire2 <= key_pressed; // alt
|
||||
'h29: btn_fire1 <= key_pressed; // Space
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,2 +1,2 @@
|
||||
`define BUILD_DATE "190102"
|
||||
`define BUILD_TIME "031130"
|
||||
`define BUILD_DATE "190604"
|
||||
`define BUILD_TIME "154728"
|
||||
|
||||
@@ -14,11 +14,11 @@
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2013 Altera Corporation
|
||||
--Copyright (C) 1991-2014 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
@@ -145,9 +145,9 @@ BEGIN
|
||||
clk0_duty_cycle => 50,
|
||||
clk0_multiply_by => 10,
|
||||
clk0_phase_shift => "0",
|
||||
clk1_divide_by => 27,
|
||||
clk1_divide_by => 9,
|
||||
clk1_duty_cycle => 50,
|
||||
clk1_multiply_by => 40,
|
||||
clk1_multiply_by => 8,
|
||||
clk1_phase_shift => "0",
|
||||
compensate_clock => "CLK0",
|
||||
inclk0_input_frequency => 37037,
|
||||
@@ -232,7 +232,7 @@ END SYN;
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "24.000000"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
@@ -261,9 +261,9 @@ END SYN;
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "24.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
@@ -311,9 +311,9 @@ END SYN;
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
|
||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
|
||||
|
Before Width: | Height: | Size: 39 KiB After Width: | Height: | Size: 39 KiB |
@@ -27,5 +27,4 @@ DATE = "14:32:28 October 06, 2018"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "Galaksija_Mist"
|
||||
PROJECT_REVISION = "AtomElectron_Mist"
|
||||
PROJECT_REVISION = "Galaksija_Mist"
|
||||
@@ -41,7 +41,7 @@
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:11:53 MARCH 09, 2017"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Galaksija_MiST.sv
|
||||
@@ -56,11 +56,6 @@ set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/spram.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
|
||||
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/osd.v
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
|
||||
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/pll.v
|
||||
set_global_assignment -name VHDL_FILE rtl/dac.vhd
|
||||
|
||||
@@ -218,7 +213,6 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
# end ENTITY(Galaksija_MiST)
|
||||
# --------------------------
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/galaksija_keyboard1.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/galaksija_keyboard2.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/keyboard.vhd
|
||||
set_global_assignment -name QIP_FILE ../../Mist_FPGA/common/mist/mist.qip
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/galaksija_keyboard.sv
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -23,6 +23,7 @@
|
||||
{ "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(307): case item expression covers a value already covered by a previous case item" { } { } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(321): case item expression covers a value already covered by a previous case item" { } { } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(318): case item expression covers a value already covered by a previous case item" { } { } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Inferred dual-clock RAM node \"mist_video:mist_video\|osd:osd\|osd_buffer_rtl_0\" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design." { } { } 0 276027 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10296 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10235 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
|
||||
@@ -0,0 +1,692 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2014 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
# Date created = 21:09:05 March 28, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Note:
|
||||
#
|
||||
# 1) Do not modify this file. This file was generated
|
||||
# automatically by the Quartus II software and is used
|
||||
# to preserve global assignments across Quartus II versions.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
|
||||
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
|
||||
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
|
||||
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
|
||||
set_global_assignment -name SMART_RECOMPILE Off
|
||||
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
|
||||
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
|
||||
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
|
||||
set_global_assignment -name HC_OUTPUT_DIR hc_output
|
||||
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
|
||||
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
|
||||
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
|
||||
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
|
||||
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
|
||||
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
|
||||
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
|
||||
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
|
||||
set_global_assignment -name REVISION_TYPE Base
|
||||
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
|
||||
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
|
||||
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
|
||||
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
|
||||
set_global_assignment -name DO_COMBINED_ANALYSIS Off
|
||||
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT On
|
||||
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
|
||||
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
|
||||
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
|
||||
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
|
||||
set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
|
||||
set_global_assignment -name MUX_RESTRUCTURE Auto
|
||||
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
|
||||
set_global_assignment -name ENABLE_IP_DEBUG Off
|
||||
set_global_assignment -name SAVE_DISK_SPACE On
|
||||
set_global_assignment -name DISABLE_OCP_HW_EVAL Off
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
|
||||
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
|
||||
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
|
||||
set_global_assignment -name FAMILY "Cyclone IV GX"
|
||||
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
|
||||
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
|
||||
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
|
||||
set_global_assignment -name SAFE_STATE_MACHINE Off
|
||||
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
|
||||
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
|
||||
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
|
||||
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
|
||||
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
|
||||
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
|
||||
set_global_assignment -name PARALLEL_SYNTHESIS On
|
||||
set_global_assignment -name DSP_BLOCK_BALANCING Auto
|
||||
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
|
||||
set_global_assignment -name NOT_GATE_PUSH_BACK On
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
|
||||
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
|
||||
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
|
||||
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
|
||||
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
|
||||
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
|
||||
set_global_assignment -name IGNORE_SOFT_BUFFERS On
|
||||
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
|
||||
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
|
||||
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
|
||||
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
|
||||
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
|
||||
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
|
||||
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
|
||||
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
|
||||
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
|
||||
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
|
||||
set_global_assignment -name AUTO_LCELL_INSERTION On
|
||||
set_global_assignment -name CARRY_CHAIN_LENGTH 48
|
||||
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
|
||||
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
|
||||
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
|
||||
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
|
||||
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
|
||||
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
|
||||
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
|
||||
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
|
||||
set_global_assignment -name AUTO_CARRY_CHAINS On
|
||||
set_global_assignment -name AUTO_CASCADE_CHAINS On
|
||||
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
|
||||
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
|
||||
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
|
||||
set_global_assignment -name AUTO_ROM_RECOGNITION On
|
||||
set_global_assignment -name AUTO_RAM_RECOGNITION On
|
||||
set_global_assignment -name AUTO_DSP_RECOGNITION On
|
||||
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
|
||||
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
||||
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
|
||||
set_global_assignment -name STRICT_RAM_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
|
||||
set_global_assignment -name FORCE_SYNCH_CLEAR Off
|
||||
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
|
||||
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
|
||||
set_global_assignment -name AUTO_RESOURCE_SHARING Off
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
|
||||
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
|
||||
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
|
||||
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
|
||||
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
|
||||
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
|
||||
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
|
||||
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
|
||||
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III"
|
||||
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
|
||||
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
|
||||
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
|
||||
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
|
||||
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
|
||||
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
|
||||
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
|
||||
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
|
||||
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
|
||||
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
|
||||
set_global_assignment -name SYNTHESIS_EFFORT Auto
|
||||
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
|
||||
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
|
||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
|
||||
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
|
||||
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
|
||||
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
|
||||
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
|
||||
set_global_assignment -name SYNTHESIS_SEED 1
|
||||
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
|
||||
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
|
||||
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
|
||||
set_global_assignment -name AUTO_MERGE_PLLS On
|
||||
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
|
||||
set_global_assignment -name TXPMA_SLEW_RATE Low
|
||||
set_global_assignment -name ADCE_ENABLED Auto
|
||||
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
|
||||
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
|
||||
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
|
||||
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
|
||||
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
|
||||
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
|
||||
set_global_assignment -name DEVICE AUTO
|
||||
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
|
||||
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
|
||||
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
|
||||
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
|
||||
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
|
||||
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
|
||||
set_global_assignment -name STRATIX_UPDATE_MODE Standard
|
||||
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE Standard
|
||||
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
|
||||
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
|
||||
set_global_assignment -name CVP_MODE Off
|
||||
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
|
||||
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
|
||||
set_global_assignment -name USER_START_UP_CLOCK Off
|
||||
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
|
||||
set_global_assignment -name ENABLE_VREFA_PIN Off
|
||||
set_global_assignment -name ENABLE_VREFB_PIN Off
|
||||
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
|
||||
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
|
||||
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
|
||||
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
|
||||
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
|
||||
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
|
||||
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
|
||||
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
|
||||
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
|
||||
set_global_assignment -name ENABLE_NCE_PIN On
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
|
||||
set_global_assignment -name CRC_ERROR_CHECKING Off
|
||||
set_global_assignment -name INTERNAL_SCRUBBING Off
|
||||
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
|
||||
set_global_assignment -name PR_READY_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_CVP_CONFDONE Off
|
||||
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
|
||||
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
|
||||
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
|
||||
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic
|
||||
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
|
||||
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
|
||||
set_global_assignment -name OPTIMIZE_SSN Off
|
||||
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
|
||||
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
|
||||
set_global_assignment -name ECO_REGENERATE_REPORT Off
|
||||
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
|
||||
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
|
||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
|
||||
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
|
||||
set_global_assignment -name SEED 1
|
||||
set_global_assignment -name SLOW_SLEW_RATE Off
|
||||
set_global_assignment -name PCI_IO Off
|
||||
set_global_assignment -name VREF_MODE EXTERNAL
|
||||
set_global_assignment -name TURBO_BIT On
|
||||
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
|
||||
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
|
||||
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
|
||||
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS Off
|
||||
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
|
||||
set_global_assignment -name NORMAL_LCELL_INSERT On
|
||||
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS On
|
||||
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
|
||||
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
|
||||
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
|
||||
set_global_assignment -name AUTO_TURBO_BIT ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
|
||||
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
|
||||
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
|
||||
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
|
||||
set_global_assignment -name FITTER_EFFORT "Auto Fit"
|
||||
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
|
||||
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
|
||||
set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
|
||||
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
|
||||
set_global_assignment -name AUTO_GLOBAL_CLOCK On
|
||||
set_global_assignment -name AUTO_GLOBAL_OE On
|
||||
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
|
||||
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
|
||||
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
|
||||
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
|
||||
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
|
||||
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
|
||||
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
|
||||
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
|
||||
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
|
||||
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
|
||||
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_LARGE_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
|
||||
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
|
||||
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
|
||||
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
|
||||
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
|
||||
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
|
||||
set_global_assignment -name PR_DONE_OPEN_DRAIN On
|
||||
set_global_assignment -name NCEO_OPEN_DRAIN On
|
||||
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
|
||||
set_global_assignment -name ENABLE_PR_PINS Off
|
||||
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
|
||||
set_global_assignment -name CLAMPING_DIODE Off
|
||||
set_global_assignment -name TRI_STATE_SPI_PINS Off
|
||||
set_global_assignment -name UNUSED_TSD_PINS_GND Off
|
||||
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
|
||||
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
|
||||
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
|
||||
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
|
||||
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
|
||||
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
|
||||
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
|
||||
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
|
||||
set_global_assignment -name COMPRESSION_MODE Off
|
||||
set_global_assignment -name CLOCK_SOURCE Internal
|
||||
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
|
||||
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
|
||||
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
||||
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
|
||||
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
|
||||
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
|
||||
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
|
||||
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
|
||||
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
|
||||
set_global_assignment -name SECURITY_BIT Off
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
|
||||
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
|
||||
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
|
||||
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
|
||||
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
|
||||
set_global_assignment -name GENERATE_TTF_FILE Off
|
||||
set_global_assignment -name GENERATE_RBF_FILE Off
|
||||
set_global_assignment -name GENERATE_HEX_FILE Off
|
||||
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
|
||||
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
|
||||
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
|
||||
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
|
||||
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
|
||||
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
|
||||
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
|
||||
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
|
||||
set_global_assignment -name ENABLE_OCT_DONE Off
|
||||
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
|
||||
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
|
||||
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
|
||||
set_global_assignment -name START_TIME 0ns
|
||||
set_global_assignment -name SIMULATION_MODE TIMING
|
||||
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
|
||||
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
|
||||
set_global_assignment -name SETUP_HOLD_DETECTION Off
|
||||
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
|
||||
set_global_assignment -name CHECK_OUTPUTS Off
|
||||
set_global_assignment -name SIMULATION_COVERAGE On
|
||||
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
|
||||
set_global_assignment -name GLITCH_DETECTION Off
|
||||
set_global_assignment -name GLITCH_INTERVAL 1ns
|
||||
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
|
||||
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
|
||||
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
|
||||
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
|
||||
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
|
||||
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
|
||||
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
|
||||
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
|
||||
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
|
||||
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
|
||||
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
|
||||
set_global_assignment -name DRC_TOP_FANOUT 50
|
||||
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
|
||||
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
|
||||
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
|
||||
set_global_assignment -name ENABLE_DRC_SETTINGS Off
|
||||
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
|
||||
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
|
||||
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
|
||||
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
|
||||
set_global_assignment -name MERGE_HEX_FILE Off
|
||||
set_global_assignment -name GENERATE_SVF_FILE Off
|
||||
set_global_assignment -name GENERATE_ISC_FILE Off
|
||||
set_global_assignment -name GENERATE_JAM_FILE Off
|
||||
set_global_assignment -name GENERATE_JBC_FILE Off
|
||||
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
|
||||
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
|
||||
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
|
||||
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
|
||||
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
|
||||
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
|
||||
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
|
||||
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
|
||||
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
|
||||
set_global_assignment -name POWER_USE_PVA On
|
||||
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
|
||||
set_global_assignment -name POWER_USE_INPUT_FILES Off
|
||||
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
|
||||
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
|
||||
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
|
||||
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
|
||||
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
|
||||
set_global_assignment -name POWER_TJ_VALUE 25
|
||||
set_global_assignment -name POWER_USE_TA_VALUE 25
|
||||
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
|
||||
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
|
||||
set_global_assignment -name POWER_HPS_ENABLE Off
|
||||
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
|
||||
set_global_assignment -name IGNORE_PARTITIONS Off
|
||||
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
|
||||
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
|
||||
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
|
||||
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
|
||||
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
|
||||
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
|
||||
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
|
||||
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
|
||||
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
|
||||
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
|
||||
set_global_assignment -name EQC_BBOX_MERGE On
|
||||
set_global_assignment -name EQC_LVDS_MERGE On
|
||||
set_global_assignment -name EQC_RAM_UNMERGING On
|
||||
set_global_assignment -name EQC_DFF_SS_EMULATION On
|
||||
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
|
||||
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
|
||||
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
|
||||
set_global_assignment -name EQC_STRUCTURE_MATCHING On
|
||||
set_global_assignment -name EQC_AUTO_BREAK_CONE On
|
||||
set_global_assignment -name EQC_POWER_UP_COMPARE Off
|
||||
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
|
||||
set_global_assignment -name EQC_AUTO_INVERSION On
|
||||
set_global_assignment -name EQC_AUTO_TERMINATE On
|
||||
set_global_assignment -name EQC_SUB_CONE_REPORT Off
|
||||
set_global_assignment -name EQC_RENAMING_RULES On
|
||||
set_global_assignment -name EQC_PARAMETER_CHECK On
|
||||
set_global_assignment -name EQC_AUTO_PORTSWAP On
|
||||
set_global_assignment -name EQC_DETECT_DONT_CARES On
|
||||
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
|
||||
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
|
||||
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
|
||||
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
|
||||
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
|
||||
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
|
||||
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
|
||||
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
|
||||
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
|
||||
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
|
||||
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
|
||||
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
|
||||
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
|
||||
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
|
||||
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
|
||||
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
|
||||
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
|
||||
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
|
||||
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
|
||||
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
|
||||
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
|
||||
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
|
||||
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
|
||||
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
|
||||
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
|
||||
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
|
||||
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
|
||||
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
|
||||
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
|
||||
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
|
||||
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
|
||||
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
|
||||
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
|
||||
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
|
||||
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
|
||||
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
|
||||
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
|
||||
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?
|
||||
Binary file not shown.
@@ -21,100 +21,90 @@ module Galaksija_MiST(
|
||||
`include "build_id.v"
|
||||
localparam CONF_STR = {
|
||||
"Galaksija;;",
|
||||
"O23,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
|
||||
"O23,Scanlines,Off,25%,50%,75%;",
|
||||
"T9,Reset;",
|
||||
"V,v1.00.",`BUILD_DATE
|
||||
};
|
||||
wire clk_1p7, clk_25, clk_6p25;
|
||||
wire ps2_kbd_clk, ps2_kbd_data;
|
||||
wire [2:0] r, g;
|
||||
wire [1:0] b;
|
||||
wire hs, vs;
|
||||
wire [1:0] buttons, switches;
|
||||
wire ypbpr;
|
||||
wire forced_scandoubler;
|
||||
wire [31:0] status;
|
||||
wire [7:0] audio;
|
||||
wire [10:0] ps2_key;
|
||||
wire ps2_clk;
|
||||
wire ps2_data;
|
||||
assign LED = 1'b1;
|
||||
|
||||
assign LED = 1'b1;
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
|
||||
wire clk_1p7, clk_25, clk_6p25;
|
||||
pll pll (
|
||||
.inclk0 ( CLOCK_27 ),
|
||||
.c0 ( clk_1p7 ),
|
||||
.c1 ( clk_25 ),
|
||||
.c2 ( clk_6p25 )
|
||||
);
|
||||
|
||||
|
||||
mist_io #(
|
||||
.STRLEN($size(CONF_STR)>>3))
|
||||
user_io (
|
||||
.clk_sys(clk_25),
|
||||
.CONF_DATA0(CONF_DATA0),
|
||||
.SPI_SCK(SPI_SCK),
|
||||
.SPI_DI(SPI_DI),
|
||||
.SPI_DO(SPI_DO),
|
||||
.SPI_SS2(SPI_SS2),
|
||||
.conf_str(CONF_STR),
|
||||
.ypbpr(ypbpr),
|
||||
.status(status),
|
||||
.scandoubler_disable(forced_scandoubler),
|
||||
.buttons(buttons),
|
||||
.switches(switches),
|
||||
.ps2_key(ps2_key),
|
||||
.ps2_kbd_clk(ps2_clk),
|
||||
.ps2_kbd_data(ps2_data)
|
||||
);
|
||||
|
||||
video_mixer #(
|
||||
.LINE_LENGTH(320),
|
||||
.HALF_DEPTH(0))
|
||||
video_mixer (
|
||||
.clk_sys ( clk_25 ),
|
||||
.ce_pix ( clk_6p25 ),
|
||||
.ce_pix_actual ( clk_6p25 ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS3 ( SPI_SS3 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
.R ( video[5:0] ),
|
||||
.G ( video[5:0] ),
|
||||
.B ( video[5:0] ),
|
||||
.HSync ( hs ),
|
||||
.VSync ( vs ),
|
||||
.VGA_R ( VGA_R ),
|
||||
.VGA_G ( VGA_G ),
|
||||
.VGA_B ( VGA_B ),
|
||||
.VGA_VS ( VGA_VS ),
|
||||
.VGA_HS ( VGA_HS ),
|
||||
.scanlines (forced_scandoubler ? 2'b00 : {status[3:2] == 3, status[3:2] == 2}),
|
||||
.scandoubler_disable(1'b1),
|
||||
.hq2x (status[3:2]==1),
|
||||
.ypbpr ( ypbpr ),
|
||||
.ypbpr_full ( 1 ),
|
||||
.line_start ( 0 ),
|
||||
.mono ( 1 )
|
||||
);
|
||||
|
||||
wire [7:0] video;
|
||||
wire [7:0] video;
|
||||
wire hs, vs, blank;
|
||||
wire [1:0] buttons, switches;
|
||||
wire ypbpr;
|
||||
wire scandoublerD;
|
||||
wire [31:0] status;
|
||||
wire [7:0] audio;
|
||||
wire key_pressed;
|
||||
wire [7:0] key_code;
|
||||
wire key_strobe;
|
||||
|
||||
|
||||
galaksija_top galaksija_top (
|
||||
.vidclk(clk_25),
|
||||
.cpuclk(clk_6p25),
|
||||
.audclk(clk_1p7),
|
||||
.reset_in(~(status[0] | status[9] | buttons[1])),
|
||||
.ps2_key(ps2_key),
|
||||
.ps2_clk(ps2_clk),
|
||||
.ps2_data(ps2_data),
|
||||
.key_code(key_code),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.audio(audio),
|
||||
.cass_in(UART_RXD),
|
||||
.cass_out(UART_TXD),
|
||||
.video_dat(video),
|
||||
.video_hs(hs),
|
||||
.video_vs(vs),
|
||||
.video_blank()
|
||||
.video_blank(blank)
|
||||
);
|
||||
|
||||
mist_video #(.COLOR_DEPTH(6)) mist_video(
|
||||
.clk_sys(clk_25),
|
||||
.SPI_SCK(SPI_SCK),
|
||||
.SPI_SS3(SPI_SS3),
|
||||
.SPI_DI(SPI_DI),
|
||||
.R(blank ? 0 :video[5:0]),
|
||||
.G(blank ? 0 :video[5:0]),
|
||||
.B(blank ? 0 :video[5:0]),
|
||||
.HSync(hs),
|
||||
.VSync(vs),
|
||||
.VGA_R(VGA_R),
|
||||
.VGA_G(VGA_G),
|
||||
.VGA_B(VGA_B),
|
||||
.VGA_VS(VGA_VS),
|
||||
.VGA_HS(VGA_HS),
|
||||
.scandoubler_disable(1'b1),//scandoublerD),
|
||||
.scanlines(scandoublerD ? 2'b00 : {status[3:2] == 3, status[3:2] == 2}),
|
||||
.ypbpr(ypbpr)
|
||||
);
|
||||
|
||||
user_io #(
|
||||
.STRLEN(($size(CONF_STR)>>3)))
|
||||
user_io(
|
||||
.clk_sys (clk_25 ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_CLK (SPI_SCK ),
|
||||
.SPI_SS_IO (CONF_DATA0 ),
|
||||
.SPI_MISO (SPI_DO ),
|
||||
.SPI_MOSI (SPI_DI ),
|
||||
.buttons (buttons ),
|
||||
.switches (switches ),
|
||||
.scandoubler_disable (scandoublerD ),
|
||||
.ypbpr (ypbpr ),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_code (key_code ),
|
||||
.status (status )
|
||||
);
|
||||
|
||||
dac #(
|
||||
.msbi_g(7))
|
||||
dac (
|
||||
@@ -123,6 +113,4 @@ dac (
|
||||
.dac_i(audio),
|
||||
.dac_o(AUDIO_L)
|
||||
);
|
||||
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
endmodule
|
||||
|
||||
@@ -1,2 +1,2 @@
|
||||
`define BUILD_DATE "181202"
|
||||
`define BUILD_TIME "164146"
|
||||
`define BUILD_DATE "190604"
|
||||
`define BUILD_TIME "171020"
|
||||
|
||||
@@ -1,8 +1,10 @@
|
||||
module galaksija_keyboard1(
|
||||
module galaksija_keyboard(
|
||||
input clk,
|
||||
input reset,
|
||||
input [5:0]addr,
|
||||
input [7:0]ps2_key,
|
||||
input [7:0] key_code,
|
||||
input key_strobe,
|
||||
input key_pressed,
|
||||
output [7:0]key_out,
|
||||
input rd_key
|
||||
);
|
||||
@@ -23,7 +25,7 @@ always @(posedge clk) begin
|
||||
begin
|
||||
keys[num] = 1'b0;
|
||||
end
|
||||
case (ps2_key[7:0])
|
||||
case (key_code[7:0])
|
||||
//nix 00
|
||||
8'h1C : keys[8'd01] = 1'b1; // A
|
||||
8'h32 : keys[8'd02] = 1'b1; // B
|
||||
@@ -93,7 +95,7 @@ always @(posedge clk) begin
|
||||
|
||||
endcase
|
||||
if (keys[8'd53] == 1'b1) begin//shift
|
||||
case (ps2_key[7:0])
|
||||
case (key_code[7:0])
|
||||
8'h1C : keys[8'd01] = 1'b1; // a
|
||||
8'h32 : keys[8'd02] = 1'b1; // b
|
||||
8'h21 : keys[8'd03] = 1'b1; // c
|
||||
@@ -1,256 +0,0 @@
|
||||
module galaksija_keyboard2(
|
||||
input clk,
|
||||
input reset_n,
|
||||
input [5:0]addr,
|
||||
input rd_key,
|
||||
input RD_n,
|
||||
input ps2_clk,
|
||||
input ps2_data,
|
||||
input LINE_IN,
|
||||
output [7:0]KDatout
|
||||
);
|
||||
|
||||
|
||||
wire [2:0]KSsel = addr[2:0];
|
||||
wire [2:0]KRsel = addr[5:3];
|
||||
wire [7:0]KS;
|
||||
wire [2:0]KR_bin;
|
||||
//wire KSout;
|
||||
wire [7:0]scan_code, scan_code_int;
|
||||
wire scan_ready, scan_ready_int;
|
||||
wire [2:0]row, col;
|
||||
wire set, clr;
|
||||
typedef reg [0:63] arr;
|
||||
arr key_array = 8'hFF;
|
||||
wire special, special_set, special_clr;
|
||||
typedef enum {WAIT_CODE, RELEASE} STATES;
|
||||
STATES CState, NState = WAIT_CODE;
|
||||
wire kbd_rd;
|
||||
|
||||
// Select keyboard row or select latch
|
||||
always @(KRsel, rd_key)
|
||||
begin
|
||||
if (rd_key == 1'b1) begin
|
||||
case (KRsel)//spalte
|
||||
3'b000 : KR_bin <= 3'b000;
|
||||
3'b001 : KR_bin <= 3'b001;
|
||||
3'b010 : KR_bin <= 3'b010;
|
||||
3'b011 : KR_bin <= 3'b011;
|
||||
3'b100 : KR_bin <= 3'b100;
|
||||
3'b101 : KR_bin <= 3'b101;
|
||||
3'b110 : KR_bin <= 3'b110;
|
||||
3'b111 : KR_bin <= 3'b111;
|
||||
default : KR_bin <= 3'b000;
|
||||
endcase
|
||||
end else
|
||||
KR_bin <= 3'b000;
|
||||
end
|
||||
|
||||
// Multiplex the keyboard scanlines
|
||||
always @(KSsel, rd_key, KS, RD_n)
|
||||
begin
|
||||
KDatout <= 8'b00000000;
|
||||
case (KSsel)//reihe
|
||||
3'b000 : KDatout[0] <= KS[0];
|
||||
3'b001 : KDatout[1] <= KS[1];
|
||||
3'b010 : KDatout[2] <= KS[2];
|
||||
3'b011 : KDatout[3] <= KS[3];
|
||||
3'b100 : KDatout[4] <= KS[4];
|
||||
3'b101 : KDatout[5] <= KS[5];
|
||||
3'b110 : KDatout[6] <= KS[6];
|
||||
3'b111 : KDatout[7] <= KS[7];
|
||||
default : KDatout <= 8'b11111111;
|
||||
endcase
|
||||
end
|
||||
|
||||
// scan_ready_int has asynchronous reset
|
||||
always @(scan_ready_int, clk) begin
|
||||
if (clk == 1'b1) begin
|
||||
scan_ready = scan_ready_int;
|
||||
scan_code = scan_code_int;
|
||||
end
|
||||
end
|
||||
|
||||
// Galaksija keyboard array
|
||||
always @(KR_bin, row, col, set, clr, clk, LINE_IN, key_array) begin
|
||||
{row,col} = 6'b000000;
|
||||
if (LINE_IN == 1'b1) begin
|
||||
if (KR_bin == ~3'b000)
|
||||
KS[0] = {3'b000,KR_bin};
|
||||
else
|
||||
KS[0] = 1'b1;
|
||||
end else
|
||||
KS[0] = 1'b0;
|
||||
|
||||
KS[1] = {3'b001,KR_bin};
|
||||
KS[2] = {3'b010,KR_bin};
|
||||
KS[3] = {3'b011,KR_bin};
|
||||
KS[4] = {3'b100,KR_bin};
|
||||
KS[5] = {3'b101,KR_bin};
|
||||
KS[6] = {3'b110,KR_bin};
|
||||
KS[7] = {3'b111,KR_bin};
|
||||
|
||||
if (clk == 1'b1) begin
|
||||
if (set == 1'b1)
|
||||
{row,col} = 6'b111111;
|
||||
else if (clr == 1'b1) begin
|
||||
{row,col} = 6'b000000;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Bit for special characters
|
||||
always @(special_set, special_clr, clk) begin
|
||||
if (clk == 1'b1) begin
|
||||
if (special_clr == 1'b1)
|
||||
special = 1'b0;
|
||||
if (special_set == 1'b1)
|
||||
special = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// Capture special codes
|
||||
always @(scan_code, scan_ready) begin
|
||||
if (scan_ready == 1'b1) begin
|
||||
if (scan_code == 8'hE0)
|
||||
special_set = 1'b1;
|
||||
else
|
||||
special_set = 1'b0;
|
||||
end else
|
||||
special_set = 1'b0;
|
||||
end
|
||||
|
||||
// State machine state propagation
|
||||
always @(clk, NState, reset_n) begin
|
||||
if (reset_n == 1'b0)
|
||||
CState = WAIT_CODE;
|
||||
else
|
||||
if (clk == 1'b1)
|
||||
CState = NState;
|
||||
end
|
||||
|
||||
// State machine
|
||||
always @(CState, scan_code, scan_ready) begin
|
||||
case (CState)
|
||||
WAIT_CODE : begin
|
||||
set = 1'b0;
|
||||
special_clr = 1'b0;
|
||||
if (scan_ready == 1'b1) begin
|
||||
kbd_rd <= 1'b1;
|
||||
if (scan_code == 8'hF0) begin
|
||||
NState = RELEASE;
|
||||
clr = 1'b0;
|
||||
end else begin
|
||||
NState = WAIT_CODE;
|
||||
clr = 1'b1;
|
||||
end
|
||||
end else begin
|
||||
kbd_rd = 1'b0;
|
||||
clr = 1'b0;
|
||||
NState = WAIT_CODE;
|
||||
end
|
||||
end
|
||||
RELEASE : begin
|
||||
clr = 1'b0;
|
||||
if (scan_ready == 1'b1) begin
|
||||
kbd_rd = 1'b1;
|
||||
set = 1'b1;
|
||||
NState = WAIT_CODE;
|
||||
special_clr = 1'b1;
|
||||
end else begin
|
||||
kbd_rd = 1'b0;
|
||||
set = 1'b0;
|
||||
NState = RELEASE;
|
||||
special_clr = 1'b0;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(special, scan_code) begin
|
||||
if (special == 1'b0)
|
||||
case (scan_code)
|
||||
8'h1C : begin row = "001"; row = "000"; end// A
|
||||
8'h32 : begin row = "010"; row = "000"; end// B
|
||||
8'h21 : begin row = "011"; row = "000"; end// C
|
||||
8'h23 : begin row = "100"; row = "000"; end// D
|
||||
8'h24 : begin row = "101"; row = "000"; end// E
|
||||
8'h2B : begin row = "110"; row = "000"; end// F
|
||||
8'h34 : begin row = "111"; row = "000"; end// G
|
||||
|
||||
8'h33 : begin row = "000"; row = "001"; end// H
|
||||
8'h43 : begin row = "001"; row = "001"; end// I
|
||||
8'h3B : begin row = "010"; row = "001"; end// J
|
||||
8'h42 : begin row = "011"; row = "001"; end// K
|
||||
8'h4B : begin row = "100"; row = "001"; end// L
|
||||
8'h3A : begin row = "101"; row = "001"; end// M
|
||||
8'h31 : begin row = "110"; row = "001"; end// N
|
||||
8'h44 : begin row = "111"; row = "001"; end// O
|
||||
|
||||
8'h4D : begin row = "000"; row = "010"; end// P
|
||||
8'h15 : begin row = "001"; row = "010"; end// Q
|
||||
8'h2D : begin row = "010"; row = "010"; end// R
|
||||
8'h1B : begin row = "011"; row = "010"; end// S
|
||||
8'h2C : begin row = "100"; row = "010"; end// T
|
||||
8'h3C : begin row = "101"; row = "010"; end// U
|
||||
8'h2A : begin row = "110"; row = "010"; end// V
|
||||
8'h1D : begin row = "111"; row = "010"; end// W
|
||||
|
||||
8'h22 : begin row = "000"; row = "011"; end// X
|
||||
8'h35 : begin row = "001"; row = "011"; end// Y
|
||||
8'h1A : begin row = "010"; row = "011"; end// Z
|
||||
8'h29 : begin row = "111"; row = "011"; end// SPACE
|
||||
|
||||
8'h45 : begin row = "000"; row = "100"; end// 0
|
||||
8'h16 : begin row = "001"; row = "100"; end// 1
|
||||
8'h1E : begin row = "010"; row = "100"; end// 2
|
||||
8'h26 : begin row = "011"; row = "100"; end// 3
|
||||
8'h25 : begin row = "100"; row = "100"; end// 4
|
||||
8'h2E : begin row = "101"; row = "100"; end// 5
|
||||
8'h36 : begin row = "110"; row = "100"; end// 6
|
||||
8'h3D : begin row = "111"; row = "100"; end// 7
|
||||
|
||||
|
||||
8'h3E : begin row = "000"; row = "101"; end// 8
|
||||
8'h46 : begin row = "001"; row = "101"; end// 9
|
||||
8'h4C : begin row = "010"; row = "101"; end// ;
|
||||
8'h54 : begin row = "011"; row = "101"; end// : (PS2 equ = [)
|
||||
8'h41 : begin row = "100"; row = "101"; end// ,
|
||||
8'h55 : begin row = "101"; row = "101"; end// =
|
||||
8'h71 : begin row = "110"; row = "101"; end// .
|
||||
8'h49 : begin row = "110"; row = "101"; end// .
|
||||
8'h4A : begin row = "111"; row = "101"; end// /
|
||||
|
||||
8'h5A : begin row = "000"; row = "110"; end// ret
|
||||
8'h12 : begin row = "101"; row = "110"; end// shift (left)
|
||||
8'h59 : begin row = "101"; row = "110"; end// shift (right)
|
||||
default : begin row = "111"; col = "111"; end
|
||||
endcase
|
||||
else
|
||||
case (scan_code)
|
||||
8'h75 : begin row = "011"; row = "011"; end// UP
|
||||
8'h72 : begin row = "100"; row = "011"; end// DOWN
|
||||
8'h6B : begin row = "101"; row = "011"; end// LEFT
|
||||
8'h74 : begin row = "110"; row = "011"; end// RIGHT
|
||||
|
||||
8'h4A : begin row = "111"; row = "101"; end// /
|
||||
|
||||
8'h69 : begin row = "001"; row = "110"; end// brk = end
|
||||
8'h6C : begin row = "010"; row = "110"; end// rpt = home
|
||||
8'h71 : begin row = "011"; row = "110"; end// del
|
||||
8'h7D : begin row = "100"; row = "110"; end// lst = page up
|
||||
default : begin row = "111"; col = "111"; end
|
||||
endcase
|
||||
end
|
||||
|
||||
keyboard keyboard(
|
||||
.keyboard_clk(ps2_clk),
|
||||
.keyboard_data(ps2_data),
|
||||
.clock(clk),
|
||||
.reset(reset_n),
|
||||
.reads(kbd_rd),
|
||||
.scan_code(scan_code_int),
|
||||
.scan_ready(scan_ready_int)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -3,7 +3,9 @@ module galaksija_top(
|
||||
input cpuclk,
|
||||
input audclk,
|
||||
input reset_in,
|
||||
input [10:0] ps2_key,
|
||||
input [7:0] key_code,
|
||||
input key_strobe,
|
||||
input key_pressed,
|
||||
input ps2_clk,
|
||||
input ps2_data,
|
||||
output [7:0] audio,
|
||||
@@ -256,27 +258,16 @@ galaksija_video(
|
||||
|
||||
wire [7:0]key_out;
|
||||
wire rd_key;
|
||||
galaksija_keyboard1 galaksija_keyboard1(
|
||||
galaksija_keyboard galaksija_keyboard(
|
||||
.clk(vidclk),
|
||||
.addr(addr[5:0]),
|
||||
.reset(~reset_in),
|
||||
.ps2_key(ps2_key),
|
||||
.key_code(key_code),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_out(key_out),
|
||||
.rd_key(rd_key)
|
||||
);
|
||||
/*
|
||||
galaksija_keyboard2 galaksija_keyboard2(
|
||||
.clk(vidclk),
|
||||
.reset_n(reset_in),
|
||||
.addr(addr[5:0]),
|
||||
.rd_key(rd_key),
|
||||
.RD_n(rd_n),
|
||||
.ps2_clk(ps2_clk),
|
||||
.ps2_data(ps2_data),
|
||||
.LINE_IN(1'b0),
|
||||
.KDatout(key_out)
|
||||
);*/
|
||||
|
||||
|
||||
wire PIN_A = (1'b1 & 1'b1 & wr_n);
|
||||
wire [7:0]chan_A, chan_B, chan_C;
|
||||
@@ -297,7 +288,7 @@ AY8912 AY8912(
|
||||
.CHANNEL_A(chan_A),
|
||||
.CHANNEL_B(chan_B),
|
||||
.CHANNEL_C(chan_C),
|
||||
.SEL(1'b1),//divider?
|
||||
.SEL(1'b1),//
|
||||
.IO_in(),//not used
|
||||
.IO_out()//not used
|
||||
);
|
||||
|
||||
@@ -1,454 +0,0 @@
|
||||
//
|
||||
//
|
||||
// Copyright (c) 2012-2013 Ludvig Strigeus
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
//
|
||||
// This program is GPL Licensed. See COPYING for the full license.
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
|
||||
`define BITS_TO_FIT(N) ( \
|
||||
N <= 2 ? 0 : \
|
||||
N <= 4 ? 1 : \
|
||||
N <= 8 ? 2 : \
|
||||
N <= 16 ? 3 : \
|
||||
N <= 32 ? 4 : \
|
||||
N <= 64 ? 5 : \
|
||||
N <= 128 ? 6 : \
|
||||
N <= 256 ? 7 : \
|
||||
N <= 512 ? 8 : \
|
||||
N <=1024 ? 9 : 10 )
|
||||
|
||||
module hq2x_in #(parameter LENGTH, parameter DWIDTH)
|
||||
(
|
||||
input clk,
|
||||
|
||||
input [AWIDTH:0] rdaddr,
|
||||
input rdbuf,
|
||||
output[DWIDTH:0] q,
|
||||
|
||||
input [AWIDTH:0] wraddr,
|
||||
input wrbuf,
|
||||
input [DWIDTH:0] data,
|
||||
input wren
|
||||
);
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
wire [DWIDTH:0] out[2];
|
||||
assign q = out[rdbuf];
|
||||
|
||||
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
|
||||
endmodule
|
||||
|
||||
|
||||
module hq2x_out #(parameter LENGTH, parameter DWIDTH)
|
||||
(
|
||||
input clk,
|
||||
|
||||
input [AWIDTH:0] rdaddr,
|
||||
input [1:0] rdbuf,
|
||||
output[DWIDTH:0] q,
|
||||
|
||||
input [AWIDTH:0] wraddr,
|
||||
input [1:0] wrbuf,
|
||||
input [DWIDTH:0] data,
|
||||
input wren
|
||||
);
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
|
||||
wire [DWIDTH:0] out[4];
|
||||
assign q = out[rdbuf];
|
||||
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
|
||||
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
|
||||
endmodule
|
||||
|
||||
|
||||
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
|
||||
(
|
||||
input clock,
|
||||
input [DWIDTH:0] data,
|
||||
input [AWIDTH:0] rdaddress,
|
||||
input [AWIDTH:0] wraddress,
|
||||
input wren,
|
||||
output [DWIDTH:0] q
|
||||
);
|
||||
|
||||
altsyncram altsyncram_component (
|
||||
.address_a (wraddress),
|
||||
.clock0 (clock),
|
||||
.data_a (data),
|
||||
.wren_a (wren),
|
||||
.address_b (rdaddress),
|
||||
.q_b(q),
|
||||
.aclr0 (1'b0),
|
||||
.aclr1 (1'b0),
|
||||
.addressstall_a (1'b0),
|
||||
.addressstall_b (1'b0),
|
||||
.byteena_a (1'b1),
|
||||
.byteena_b (1'b1),
|
||||
.clock1 (1'b1),
|
||||
.clocken0 (1'b1),
|
||||
.clocken1 (1'b1),
|
||||
.clocken2 (1'b1),
|
||||
.clocken3 (1'b1),
|
||||
.data_b ({(DWIDTH+1){1'b1}}),
|
||||
.eccstatus (),
|
||||
.q_a (),
|
||||
.rden_a (1'b1),
|
||||
.rden_b (1'b1),
|
||||
.wren_b (1'b0));
|
||||
defparam
|
||||
altsyncram_component.address_aclr_b = "NONE",
|
||||
altsyncram_component.address_reg_b = "CLOCK0",
|
||||
altsyncram_component.clock_enable_input_a = "BYPASS",
|
||||
altsyncram_component.clock_enable_input_b = "BYPASS",
|
||||
altsyncram_component.clock_enable_output_b = "BYPASS",
|
||||
altsyncram_component.intended_device_family = "Cyclone III",
|
||||
altsyncram_component.lpm_type = "altsyncram",
|
||||
altsyncram_component.numwords_a = NUMWORDS,
|
||||
altsyncram_component.numwords_b = NUMWORDS,
|
||||
altsyncram_component.operation_mode = "DUAL_PORT",
|
||||
altsyncram_component.outdata_aclr_b = "NONE",
|
||||
altsyncram_component.outdata_reg_b = "UNREGISTERED",
|
||||
altsyncram_component.power_up_uninitialized = "FALSE",
|
||||
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
|
||||
altsyncram_component.widthad_a = AWIDTH+1,
|
||||
altsyncram_component.widthad_b = AWIDTH+1,
|
||||
altsyncram_component.width_a = DWIDTH+1,
|
||||
altsyncram_component.width_b = DWIDTH+1,
|
||||
altsyncram_component.width_byteena_a = 1;
|
||||
|
||||
endmodule
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module DiffCheck
|
||||
(
|
||||
input [17:0] rgb1,
|
||||
input [17:0] rgb2,
|
||||
output result
|
||||
);
|
||||
|
||||
wire [5:0] r = rgb1[5:1] - rgb2[5:1];
|
||||
wire [5:0] g = rgb1[11:7] - rgb2[11:7];
|
||||
wire [5:0] b = rgb1[17:13] - rgb2[17:13];
|
||||
wire [6:0] t = $signed(r) + $signed(b);
|
||||
wire [6:0] gx = {g[5], g};
|
||||
wire [7:0] y = $signed(t) + $signed(gx);
|
||||
wire [6:0] u = $signed(r) - $signed(b);
|
||||
wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
|
||||
|
||||
// if y is inside (-24..24)
|
||||
wire y_inside = (y < 8'h18 || y >= 8'he8);
|
||||
|
||||
// if u is inside (-4, 4)
|
||||
wire u_inside = (u < 7'h4 || u >= 7'h7c);
|
||||
|
||||
// if v is inside (-6, 6)
|
||||
wire v_inside = (v < 8'h6 || v >= 8'hfA);
|
||||
assign result = !(y_inside && u_inside && v_inside);
|
||||
endmodule
|
||||
|
||||
module InnerBlend
|
||||
(
|
||||
input [8:0] Op,
|
||||
input [5:0] A,
|
||||
input [5:0] B,
|
||||
input [5:0] C,
|
||||
output [5:0] O
|
||||
);
|
||||
|
||||
function [8:0] mul6x3;
|
||||
input [5:0] op1;
|
||||
input [2:0] op2;
|
||||
begin
|
||||
mul6x3 = 9'd0;
|
||||
if(op2[0]) mul6x3 = mul6x3 + op1;
|
||||
if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
|
||||
if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
|
||||
end
|
||||
endfunction
|
||||
|
||||
wire OpOnes = Op[4];
|
||||
wire [8:0] Amul = mul6x3(A, Op[7:5]);
|
||||
wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
|
||||
wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
|
||||
wire [8:0] At = Amul;
|
||||
wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
|
||||
wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
|
||||
wire [9:0] Res = {At, 1'b0} + Bt + Ct;
|
||||
assign O = Op[8] ? A : Res[9:4];
|
||||
endmodule
|
||||
|
||||
module Blend
|
||||
(
|
||||
input [5:0] rule,
|
||||
input disable_hq2x,
|
||||
input [17:0] E,
|
||||
input [17:0] A,
|
||||
input [17:0] B,
|
||||
input [17:0] D,
|
||||
input [17:0] F,
|
||||
input [17:0] H,
|
||||
output [17:0] Result
|
||||
);
|
||||
|
||||
reg [1:0] input_ctrl;
|
||||
reg [8:0] op;
|
||||
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
|
||||
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
|
||||
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
|
||||
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
|
||||
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
|
||||
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
|
||||
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
|
||||
localparam AB = 2'b00;
|
||||
localparam AD = 2'b01;
|
||||
localparam DB = 2'b10;
|
||||
localparam BD = 2'b11;
|
||||
wire is_diff;
|
||||
DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
|
||||
|
||||
always @* begin
|
||||
case({!is_diff, rule[5:2]})
|
||||
1,17: {op, input_ctrl} = {BLEND1, AB};
|
||||
2,18: {op, input_ctrl} = {BLEND1, DB};
|
||||
3,19: {op, input_ctrl} = {BLEND1, BD};
|
||||
4,20: {op, input_ctrl} = {BLEND2, DB};
|
||||
5,21: {op, input_ctrl} = {BLEND2, AB};
|
||||
6,22: {op, input_ctrl} = {BLEND2, AD};
|
||||
|
||||
8: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
9: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
10: {op, input_ctrl} = {BLEND0, 2'bxx};
|
||||
11: {op, input_ctrl} = {BLEND1, AB};
|
||||
12: {op, input_ctrl} = {BLEND1, AB};
|
||||
13: {op, input_ctrl} = {BLEND1, AB};
|
||||
14: {op, input_ctrl} = {BLEND1, DB};
|
||||
15: {op, input_ctrl} = {BLEND1, BD};
|
||||
|
||||
24: {op, input_ctrl} = {BLEND2, DB};
|
||||
25: {op, input_ctrl} = {BLEND5, DB};
|
||||
26: {op, input_ctrl} = {BLEND6, DB};
|
||||
27: {op, input_ctrl} = {BLEND2, DB};
|
||||
28: {op, input_ctrl} = {BLEND4, DB};
|
||||
29: {op, input_ctrl} = {BLEND5, DB};
|
||||
30: {op, input_ctrl} = {BLEND3, BD};
|
||||
31: {op, input_ctrl} = {BLEND3, DB};
|
||||
default: {op, input_ctrl} = 11'bx;
|
||||
endcase
|
||||
|
||||
// Setting op[8] effectively disables HQ2X because blend will always return E.
|
||||
if (disable_hq2x) op[8] = 1;
|
||||
end
|
||||
|
||||
// Generate inputs to the inner blender. Valid combinations.
|
||||
// 00: E A B
|
||||
// 01: E A D
|
||||
// 10: E D B
|
||||
// 11: E B D
|
||||
wire [17:0] Input1 = E;
|
||||
wire [17:0] Input2 = !input_ctrl[1] ? A :
|
||||
!input_ctrl[0] ? D : B;
|
||||
|
||||
wire [17:0] Input3 = !input_ctrl[0] ? B : D;
|
||||
InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]);
|
||||
InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]);
|
||||
InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
|
||||
endmodule
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
|
||||
(
|
||||
input clk,
|
||||
input ce_x4,
|
||||
input [DWIDTH:0] inputpixel,
|
||||
input mono,
|
||||
input disable_hq2x,
|
||||
input reset_frame,
|
||||
input reset_line,
|
||||
input [1:0] read_y,
|
||||
input [AWIDTH+1:0] read_x,
|
||||
output [DWIDTH:0] outpixel
|
||||
);
|
||||
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
localparam DWIDTH = HALF_DEPTH ? 8 : 17;
|
||||
|
||||
wire [5:0] hqTable[256] = '{
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
|
||||
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
|
||||
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
|
||||
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
|
||||
};
|
||||
|
||||
reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
|
||||
reg [17:0] A, B, D, F, G, H;
|
||||
reg [7:0] pattern, nextpatt;
|
||||
reg [1:0] i;
|
||||
reg [7:0] y;
|
||||
|
||||
wire curbuf = y[0];
|
||||
reg prevbuf = 0;
|
||||
wire iobuf = !curbuf;
|
||||
|
||||
wire diff0, diff1;
|
||||
DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
|
||||
DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
|
||||
|
||||
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
|
||||
|
||||
wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
|
||||
wire [17:0] blend_result;
|
||||
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
|
||||
|
||||
reg Curr2_addr1;
|
||||
reg [AWIDTH:0] Curr2_addr2;
|
||||
wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
|
||||
wire [DWIDTH:0] Curr2tmp;
|
||||
|
||||
reg [AWIDTH:0] wrin_addr2;
|
||||
reg [DWIDTH:0] wrpix;
|
||||
reg wrin_en;
|
||||
|
||||
function [17:0] h2rgb;
|
||||
input [8:0] v;
|
||||
begin
|
||||
h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [8:0] rgb2h;
|
||||
input [17:0] v;
|
||||
begin
|
||||
rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
|
||||
(
|
||||
.clk(clk),
|
||||
|
||||
.rdaddr(Curr2_addr2),
|
||||
.rdbuf(Curr2_addr1),
|
||||
.q(Curr2tmp),
|
||||
|
||||
.wraddr(wrin_addr2),
|
||||
.wrbuf(iobuf),
|
||||
.data(wrpix),
|
||||
.wren(wrin_en)
|
||||
);
|
||||
|
||||
reg [1:0] wrout_addr1;
|
||||
reg [AWIDTH+1:0] wrout_addr2;
|
||||
reg wrout_en;
|
||||
reg [DWIDTH:0] wrdata;
|
||||
|
||||
hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
|
||||
(
|
||||
.clk(clk),
|
||||
|
||||
.rdaddr(read_x),
|
||||
.rdbuf(read_y),
|
||||
.q(outpixel),
|
||||
|
||||
.wraddr(wrout_addr2),
|
||||
.wrbuf(wrout_addr1),
|
||||
.data(wrdata),
|
||||
.wren(wrout_en)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
reg [AWIDTH:0] offs;
|
||||
reg old_reset_line;
|
||||
reg old_reset_frame;
|
||||
|
||||
wrout_en <= 0;
|
||||
wrin_en <= 0;
|
||||
|
||||
if(ce_x4) begin
|
||||
|
||||
pattern <= new_pattern;
|
||||
|
||||
if(~&offs) begin
|
||||
if (i == 0) begin
|
||||
Curr2_addr1 <= prevbuf;
|
||||
Curr2_addr2 <= offs;
|
||||
end
|
||||
if (i == 1) begin
|
||||
Prev2 <= Curr2;
|
||||
Curr2_addr1 <= curbuf;
|
||||
Curr2_addr2 <= offs;
|
||||
end
|
||||
if (i == 2) begin
|
||||
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
|
||||
wrpix <= inputpixel;
|
||||
wrin_addr2 <= offs;
|
||||
wrin_en <= 1;
|
||||
end
|
||||
if (i == 3) begin
|
||||
offs <= offs + 1'd1;
|
||||
end
|
||||
|
||||
if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
|
||||
else wrdata <= blend_result;
|
||||
|
||||
wrout_addr1 <= {curbuf, i[1]};
|
||||
wrout_addr2 <= {offs, i[1]^i[0]};
|
||||
wrout_en <= 1;
|
||||
end
|
||||
|
||||
if(i==3) begin
|
||||
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
|
||||
{A, G} <= {Prev0, Next0};
|
||||
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
|
||||
{Prev0, Prev1} <= {Prev1, Prev2};
|
||||
{Curr0, Curr1} <= {Curr1, Curr2};
|
||||
{Next0, Next1} <= {Next1, Next2};
|
||||
end else begin
|
||||
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
|
||||
{B, F, H, D} <= {F, H, D, B};
|
||||
end
|
||||
|
||||
i <= i + 1'b1;
|
||||
if(old_reset_line && ~reset_line) begin
|
||||
old_reset_frame <= reset_frame;
|
||||
offs <= 0;
|
||||
i <= 0;
|
||||
y <= y + 1'd1;
|
||||
prevbuf <= curbuf;
|
||||
if(old_reset_frame & ~reset_frame) begin
|
||||
y <= 0;
|
||||
prevbuf <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
old_reset_line <= reset_line;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // Hq2x
|
||||
@@ -1,81 +0,0 @@
|
||||
--
|
||||
-- PS2 keyboard
|
||||
--
|
||||
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.all;
|
||||
USE IEEE.STD_LOGIC_ARITH.all;
|
||||
USE IEEE.STD_LOGIC_UNSIGNED.all;
|
||||
|
||||
ENTITY keyboard IS
|
||||
PORT( keyboard_clk, keyboard_data, clock ,
|
||||
reset, reads : IN STD_LOGIC;
|
||||
scan_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
scan_ready : OUT STD_LOGIC);
|
||||
END keyboard;
|
||||
|
||||
ARCHITECTURE rtl OF keyboard IS
|
||||
SIGNAL INCNT : std_logic_vector(3 downto 0);
|
||||
SIGNAL SHIFTIN : std_logic_vector(8 downto 0);
|
||||
SIGNAL READ_CHAR, clock_enable : std_logic;
|
||||
SIGNAL ready_set : std_logic;
|
||||
SIGNAL keyboard_clk_filtered : std_logic;
|
||||
SIGNAL filter : std_logic_vector(7 downto 0);
|
||||
BEGIN
|
||||
|
||||
PROCESS (reads, ready_set)
|
||||
BEGIN
|
||||
IF reads = '1' THEN scan_ready <= '0';
|
||||
ELSIF ready_set'EVENT and ready_set = '1' THEN
|
||||
scan_ready <= '1';
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
--This process filters the raw clock signal coming from the keyboard using a shift register and two AND gates
|
||||
Clock_filter: PROCESS
|
||||
BEGIN
|
||||
WAIT UNTIL clock'EVENT AND clock= '1';
|
||||
clock_enable <= NOT clock_enable;
|
||||
IF clock_enable = '1' THEN
|
||||
filter (6 DOWNTO 0) <= filter(7 DOWNTO 1) ;
|
||||
filter(7) <= keyboard_clk;
|
||||
IF filter = "11111111" THEN keyboard_clk_filtered <= '1';
|
||||
ELSIF filter= "00000000" THEN keyboard_clk_filtered <= '0';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS Clock_filter;
|
||||
|
||||
|
||||
--This process reads in serial data coming from the terminal
|
||||
PROCESS
|
||||
BEGIN
|
||||
WAIT UNTIL (KEYBOARD_CLK_filtered'EVENT AND KEYBOARD_CLK_filtered='1');
|
||||
IF RESET='0' THEN
|
||||
INCNT <= "0000";
|
||||
READ_CHAR <= '0';
|
||||
ready_set<= '0';
|
||||
ELSE
|
||||
IF KEYBOARD_DATA='0' AND READ_CHAR='0' THEN
|
||||
READ_CHAR<= '1';
|
||||
ready_set<= '0';
|
||||
ELSE
|
||||
-- Shift in next 8 data bits to assemble a scan code
|
||||
IF READ_CHAR = '1' THEN
|
||||
IF INCNT < "1001" THEN
|
||||
INCNT <= INCNT + 1;
|
||||
SHIFTIN(7 DOWNTO 0) <= SHIFTIN(8 DOWNTO 1);
|
||||
SHIFTIN(8) <= KEYBOARD_DATA;
|
||||
-- End of scan code character, so set flags and exit loop
|
||||
ELSE
|
||||
scan_code <= SHIFTIN(7 DOWNTO 0);
|
||||
READ_CHAR <= '0';
|
||||
ready_set <= '1';
|
||||
INCNT <= "0000";
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END rtl;
|
||||
|
||||
|
||||
@@ -1,496 +0,0 @@
|
||||
//
|
||||
// mist_io.v
|
||||
//
|
||||
// mist_io for the MiST board
|
||||
// http://code.google.com/p/mist-board/
|
||||
//
|
||||
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2015-2017 Sorgelig
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////
|
||||
|
||||
//
|
||||
// Use buffer to access SD card. It's time-critical part.
|
||||
// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
|
||||
// (Sorgelig)
|
||||
//
|
||||
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
|
||||
// clk_ps2 = clk_sys/(PS2DIV*2)
|
||||
//
|
||||
|
||||
module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
|
||||
(
|
||||
|
||||
// parameter STRLEN and the actual length of conf_str have to match
|
||||
input [(8*STRLEN)-1:0] conf_str,
|
||||
|
||||
// Global clock. It should be around 100MHz (higher is better).
|
||||
input clk_sys,
|
||||
|
||||
// Global SPI clock from ARM. 24MHz
|
||||
input SPI_SCK,
|
||||
|
||||
input CONF_DATA0,
|
||||
input SPI_SS2,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
|
||||
output reg [7:0] joystick_0,
|
||||
output reg [7:0] joystick_1,
|
||||
output reg [15:0] joystick_analog_0,
|
||||
output reg [15:0] joystick_analog_1,
|
||||
output [1:0] buttons,
|
||||
output [1:0] switches,
|
||||
output scandoubler_disable,
|
||||
output ypbpr,
|
||||
|
||||
output reg [31:0] status,
|
||||
|
||||
// SD config
|
||||
input sd_conf,
|
||||
input sd_sdhc,
|
||||
output [1:0] img_mounted, // signaling that new image has been mounted
|
||||
output reg [31:0] img_size, // size of image in bytes
|
||||
|
||||
// SD block level access
|
||||
input [31:0] sd_lba,
|
||||
input [1:0] sd_rd,
|
||||
input [1:0] sd_wr,
|
||||
output reg sd_ack,
|
||||
output reg sd_ack_conf,
|
||||
|
||||
// SD byte level access. Signals for 2-PORT altsyncram.
|
||||
output reg [8:0] sd_buff_addr,
|
||||
output reg [7:0] sd_buff_dout,
|
||||
input [7:0] sd_buff_din,
|
||||
output reg sd_buff_wr,
|
||||
|
||||
// ps2 keyboard emulation
|
||||
output ps2_kbd_clk,
|
||||
output reg ps2_kbd_data,
|
||||
output ps2_mouse_clk,
|
||||
output reg ps2_mouse_data,
|
||||
|
||||
// ps2 alternative interface.
|
||||
|
||||
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
|
||||
output reg [10:0] ps2_key = 0,
|
||||
|
||||
// [24] - toggles with every event
|
||||
output reg [24:0] ps2_mouse = 0,
|
||||
|
||||
// ARM -> FPGA download
|
||||
input ioctl_ce,
|
||||
input ioctl_wait,
|
||||
output reg ioctl_download = 0, // signal indicating an active download
|
||||
output reg [7:0] ioctl_index, // menu index used to upload the file
|
||||
output reg ioctl_wr = 0,
|
||||
output reg [13:0] ioctl_addr,
|
||||
output reg [7:0] ioctl_dout
|
||||
);
|
||||
|
||||
reg [7:0] but_sw;
|
||||
reg [2:0] stick_idx;
|
||||
|
||||
reg [1:0] mount_strobe = 0;
|
||||
assign img_mounted = mount_strobe;
|
||||
|
||||
assign buttons = but_sw[1:0];
|
||||
assign switches = but_sw[3:2];
|
||||
assign scandoubler_disable = but_sw[4];
|
||||
assign ypbpr = but_sw[5];
|
||||
|
||||
// this variant of user_io is for 8 bit cores (type == a4) only
|
||||
wire [7:0] core_type = 8'ha4;
|
||||
|
||||
// command byte read by the io controller
|
||||
wire drive_sel = sd_rd[1] | sd_wr[1];
|
||||
wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
|
||||
|
||||
reg [7:0] cmd;
|
||||
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
|
||||
reg [9:0] byte_cnt; // counts bytes
|
||||
|
||||
reg spi_do;
|
||||
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
|
||||
|
||||
reg [7:0] spi_data_out;
|
||||
|
||||
// SPI transmitter
|
||||
always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
|
||||
|
||||
reg [7:0] spi_data_in;
|
||||
reg spi_data_ready = 0;
|
||||
|
||||
// SPI receiver
|
||||
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
|
||||
reg [6:0] sbuf;
|
||||
reg [31:0] sd_lba_r;
|
||||
reg drive_sel_r;
|
||||
|
||||
if(CONF_DATA0) begin
|
||||
bit_cnt <= 0;
|
||||
byte_cnt <= 0;
|
||||
spi_data_out <= core_type;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bit_cnt <= bit_cnt + 1'd1;
|
||||
sbuf <= {sbuf[5:0], SPI_DI};
|
||||
|
||||
// finished reading command byte
|
||||
if(bit_cnt == 7) begin
|
||||
if(!byte_cnt) cmd <= {sbuf, SPI_DI};
|
||||
|
||||
spi_data_in <= {sbuf, SPI_DI};
|
||||
spi_data_ready <= ~spi_data_ready;
|
||||
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
|
||||
|
||||
spi_data_out <= 0;
|
||||
case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
|
||||
// reading config string
|
||||
8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
|
||||
|
||||
// reading sd card status
|
||||
8'h16: if(byte_cnt == 0) begin
|
||||
spi_data_out <= sd_cmd;
|
||||
sd_lba_r <= sd_lba;
|
||||
drive_sel_r <= drive_sel;
|
||||
end else if (byte_cnt == 1) begin
|
||||
spi_data_out <= drive_sel_r;
|
||||
end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
|
||||
|
||||
// reading sd card write data
|
||||
8'h18: spi_data_out <= sd_buff_din;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [31:0] ps2_key_raw = 0;
|
||||
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
|
||||
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
|
||||
|
||||
// transfer to clk_sys domain
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_ss1, old_ss2;
|
||||
reg old_ready1, old_ready2;
|
||||
reg [2:0] b_wr;
|
||||
reg got_ps2 = 0;
|
||||
|
||||
old_ss1 <= CONF_DATA0;
|
||||
old_ss2 <= old_ss1;
|
||||
old_ready1 <= spi_data_ready;
|
||||
old_ready2 <= old_ready1;
|
||||
|
||||
sd_buff_wr <= b_wr[0];
|
||||
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
b_wr <= (b_wr<<1);
|
||||
|
||||
if(old_ss2) begin
|
||||
got_ps2 <= 0;
|
||||
sd_ack <= 0;
|
||||
sd_ack_conf <= 0;
|
||||
sd_buff_addr <= 0;
|
||||
if(got_ps2) begin
|
||||
if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24];
|
||||
if(cmd == 5) begin
|
||||
ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
|
||||
if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
|
||||
if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
|
||||
if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed
|
||||
end
|
||||
end
|
||||
end
|
||||
else
|
||||
if(old_ready2 ^ old_ready1) begin
|
||||
|
||||
if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
|
||||
|
||||
if(byte_cnt < 2) begin
|
||||
|
||||
if (cmd == 8'h19) sd_ack_conf <= 1;
|
||||
if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
|
||||
mount_strobe <= 0;
|
||||
|
||||
if(cmd == 5) ps2_key_raw <= 0;
|
||||
end else begin
|
||||
|
||||
case(cmd)
|
||||
// buttons and switches
|
||||
8'h01: but_sw <= spi_data_in;
|
||||
8'h02: joystick_0 <= spi_data_in;
|
||||
8'h03: joystick_1 <= spi_data_in;
|
||||
|
||||
// store incoming ps2 mouse bytes
|
||||
8'h04: begin
|
||||
got_ps2 <= 1;
|
||||
case(byte_cnt)
|
||||
2: ps2_mouse[7:0] <= spi_data_in;
|
||||
3: ps2_mouse[15:8] <= spi_data_in;
|
||||
4: ps2_mouse[23:16] <= spi_data_in;
|
||||
endcase
|
||||
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in;
|
||||
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
|
||||
end
|
||||
|
||||
// store incoming ps2 keyboard bytes
|
||||
8'h05: begin
|
||||
got_ps2 <= 1;
|
||||
ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in};
|
||||
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in;
|
||||
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
|
||||
end
|
||||
|
||||
8'h15: status[7:0] <= spi_data_in;
|
||||
|
||||
// send SD config IO -> FPGA
|
||||
// flag that download begins
|
||||
// sd card knows data is config if sd_dout_strobe is asserted
|
||||
// with sd_ack still being inactive (low)
|
||||
8'h19,
|
||||
// send sector IO -> FPGA
|
||||
// flag that download begins
|
||||
8'h17: begin
|
||||
sd_buff_dout <= spi_data_in;
|
||||
b_wr <= 1;
|
||||
end
|
||||
|
||||
// joystick analog
|
||||
8'h1a: begin
|
||||
// first byte is joystick index
|
||||
if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
|
||||
else if(byte_cnt == 3) begin
|
||||
// second byte is x axis
|
||||
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
|
||||
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
|
||||
end else if(byte_cnt == 4) begin
|
||||
// third byte is y axis
|
||||
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
|
||||
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
|
||||
end
|
||||
end
|
||||
|
||||
// notify image selection
|
||||
8'h1c: mount_strobe[spi_data_in[0]] <= 1;
|
||||
|
||||
// send image info
|
||||
8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
|
||||
|
||||
// status, 32bit version
|
||||
8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////// PS2 ///////////////////////////////
|
||||
// 8 byte fifos to store ps2 bytes
|
||||
localparam PS2_FIFO_BITS = 3;
|
||||
|
||||
reg clk_ps2;
|
||||
always @(negedge clk_sys) begin
|
||||
integer cnt;
|
||||
cnt <= cnt + 1'd1;
|
||||
if(cnt == PS2DIV) begin
|
||||
clk_ps2 <= ~clk_ps2;
|
||||
cnt <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// keyboard
|
||||
reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
|
||||
|
||||
// ps2 transmitter state machine
|
||||
reg [3:0] ps2_kbd_tx_state;
|
||||
reg [7:0] ps2_kbd_tx_byte;
|
||||
reg ps2_kbd_parity;
|
||||
|
||||
assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
|
||||
|
||||
// ps2 transmitter
|
||||
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
|
||||
reg ps2_kbd_r_inc;
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_clk;
|
||||
old_clk <= clk_ps2;
|
||||
if(~old_clk & clk_ps2) begin
|
||||
ps2_kbd_r_inc <= 0;
|
||||
|
||||
if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
|
||||
|
||||
// transmitter is idle?
|
||||
if(ps2_kbd_tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
|
||||
// load tx register from fifo
|
||||
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
|
||||
ps2_kbd_r_inc <= 1;
|
||||
|
||||
// reset parity
|
||||
ps2_kbd_parity <= 1;
|
||||
|
||||
// start transmitter
|
||||
ps2_kbd_tx_state <= 1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_kbd_data <= 0; // start bit is 0
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
|
||||
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
|
||||
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
|
||||
if(ps2_kbd_tx_byte[0])
|
||||
ps2_kbd_parity <= !ps2_kbd_parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
|
||||
else ps2_kbd_tx_state <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// mouse
|
||||
reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
|
||||
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
|
||||
|
||||
// ps2 transmitter state machine
|
||||
reg [3:0] ps2_mouse_tx_state;
|
||||
reg [7:0] ps2_mouse_tx_byte;
|
||||
reg ps2_mouse_parity;
|
||||
|
||||
assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
|
||||
|
||||
// ps2 transmitter
|
||||
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
|
||||
reg ps2_mouse_r_inc;
|
||||
always@(posedge clk_sys) begin
|
||||
reg old_clk;
|
||||
old_clk <= clk_ps2;
|
||||
if(~old_clk & clk_ps2) begin
|
||||
ps2_mouse_r_inc <= 0;
|
||||
|
||||
if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
|
||||
|
||||
// transmitter is idle?
|
||||
if(ps2_mouse_tx_state == 0) begin
|
||||
// data in fifo present?
|
||||
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
|
||||
// load tx register from fifo
|
||||
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
|
||||
ps2_mouse_r_inc <= 1;
|
||||
|
||||
// reset parity
|
||||
ps2_mouse_parity <= 1;
|
||||
|
||||
// start transmitter
|
||||
ps2_mouse_tx_state <= 1;
|
||||
|
||||
// put start bit on data line
|
||||
ps2_mouse_data <= 0; // start bit is 0
|
||||
end
|
||||
end else begin
|
||||
|
||||
// transmission of 8 data bits
|
||||
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
|
||||
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
|
||||
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
|
||||
if(ps2_mouse_tx_byte[0])
|
||||
ps2_mouse_parity <= !ps2_mouse_parity;
|
||||
end
|
||||
|
||||
// transmission of parity
|
||||
if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
|
||||
|
||||
// transmission of stop bit
|
||||
if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
|
||||
|
||||
// advance state machine
|
||||
if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
|
||||
else ps2_mouse_tx_state <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////// DOWNLOADING ///////////////////////////////
|
||||
|
||||
localparam UIO_FILE_TX = 8'h53;
|
||||
localparam UIO_FILE_TX_DAT = 8'h54;
|
||||
localparam UIO_FILE_INDEX = 8'h55;
|
||||
|
||||
// data_io has its own SPI interface to the io controller
|
||||
always@(posedge SPI_SCK, posedge SPI_SS2) begin
|
||||
reg [6:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
reg [4:0] cnt;
|
||||
reg [13:0] addr;
|
||||
|
||||
if(SPI_SS2) cnt <= 0;
|
||||
else begin
|
||||
// don't shift in last bit. It is evaluated directly
|
||||
// when writing to ram
|
||||
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
|
||||
|
||||
// count 0-7 8-15 8-15 ...
|
||||
if(cnt < 15) cnt <= cnt + 1'd1;
|
||||
else cnt <= 8;
|
||||
|
||||
// finished command byte
|
||||
if(cnt == 7) cmd <= {sbuf, SPI_DI};
|
||||
|
||||
// prepare/end transmission
|
||||
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
|
||||
// prepare
|
||||
if(SPI_DI) begin
|
||||
// addr <= ioctl_index ? 14'd9 : 14'd0; //.p files loaded at $4009, ROM is at 0
|
||||
addr <= 14'd0;
|
||||
ioctl_download <= 1;
|
||||
end else begin
|
||||
ioctl_addr <= addr;
|
||||
ioctl_download <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// command 0x54: UIO_FILE_TX
|
||||
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
|
||||
ioctl_addr <= addr;
|
||||
ioctl_dout <= {sbuf, SPI_DI};
|
||||
addr <= addr + 1'd1;
|
||||
ioctl_wr <= 1;
|
||||
end else
|
||||
ioctl_wr <= 0;
|
||||
|
||||
// expose file (menu) index
|
||||
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,179 +0,0 @@
|
||||
// A simple OSD implementation. Can be hooked up between a cores
|
||||
// VGA output and the physical VGA pins
|
||||
|
||||
module osd (
|
||||
// OSDs pixel clock, should be synchronous to cores pixel clock to
|
||||
// avoid jitter.
|
||||
input clk_sys,
|
||||
|
||||
// SPI interface
|
||||
input SPI_SCK,
|
||||
input SPI_SS3,
|
||||
input SPI_DI,
|
||||
|
||||
// VGA signals coming from core
|
||||
input [5:0] R_in,
|
||||
input [5:0] G_in,
|
||||
input [5:0] B_in,
|
||||
input HSync,
|
||||
input VSync,
|
||||
|
||||
// VGA signals going to video connector
|
||||
output [5:0] R_out,
|
||||
output [5:0] G_out,
|
||||
output [5:0] B_out
|
||||
);
|
||||
|
||||
parameter OSD_X_OFFSET = 10'd0;
|
||||
parameter OSD_Y_OFFSET = 10'd0;
|
||||
parameter OSD_COLOR = 3'd0;
|
||||
|
||||
localparam OSD_WIDTH = 10'd256;
|
||||
localparam OSD_HEIGHT = 10'd128;
|
||||
|
||||
// *********************************************************************************
|
||||
// spi client
|
||||
// *********************************************************************************
|
||||
|
||||
// this core supports only the display related OSD commands
|
||||
// of the minimig
|
||||
reg osd_enable;
|
||||
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
|
||||
|
||||
// the OSD has its own SPI interface to the io controller
|
||||
always@(posedge SPI_SCK, posedge SPI_SS3) begin
|
||||
reg [4:0] cnt;
|
||||
reg [10:0] bcnt;
|
||||
reg [7:0] sbuf;
|
||||
reg [7:0] cmd;
|
||||
|
||||
if(SPI_SS3) begin
|
||||
cnt <= 0;
|
||||
bcnt <= 0;
|
||||
end else begin
|
||||
sbuf <= {sbuf[6:0], SPI_DI};
|
||||
|
||||
// 0:7 is command, rest payload
|
||||
if(cnt < 15) cnt <= cnt + 1'd1;
|
||||
else cnt <= 8;
|
||||
|
||||
if(cnt == 7) begin
|
||||
cmd <= {sbuf[6:0], SPI_DI};
|
||||
|
||||
// lower three command bits are line address
|
||||
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
|
||||
|
||||
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
|
||||
if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
|
||||
end
|
||||
|
||||
// command 0x20: OSDCMDWRITE
|
||||
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
|
||||
osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
|
||||
bcnt <= bcnt + 1'd1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// *********************************************************************************
|
||||
// video timing and sync polarity anaylsis
|
||||
// *********************************************************************************
|
||||
|
||||
// horizontal counter
|
||||
reg [9:0] h_cnt;
|
||||
reg [9:0] hs_low, hs_high;
|
||||
wire hs_pol = hs_high < hs_low;
|
||||
wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
|
||||
|
||||
// vertical counter
|
||||
reg [9:0] v_cnt;
|
||||
reg [9:0] vs_low, vs_high;
|
||||
wire vs_pol = vs_high < vs_low;
|
||||
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
|
||||
|
||||
wire doublescan = (dsp_height>350);
|
||||
|
||||
reg ce_pix;
|
||||
always @(negedge clk_sys) begin
|
||||
integer cnt = 0;
|
||||
integer pixsz, pixcnt;
|
||||
reg hs;
|
||||
|
||||
cnt <= cnt + 1;
|
||||
hs <= HSync;
|
||||
|
||||
pixcnt <= pixcnt + 1;
|
||||
if(pixcnt == pixsz) pixcnt <= 0;
|
||||
ce_pix <= !pixcnt;
|
||||
|
||||
if(hs && ~HSync) begin
|
||||
cnt <= 0;
|
||||
pixsz <= (cnt >> 9) - 1;
|
||||
pixcnt <= 0;
|
||||
ce_pix <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
reg hsD, hsD2;
|
||||
reg vsD, vsD2;
|
||||
|
||||
if(ce_pix) begin
|
||||
// bring hsync into local clock domain
|
||||
hsD <= HSync;
|
||||
hsD2 <= hsD;
|
||||
|
||||
// falling edge of HSync
|
||||
if(!hsD && hsD2) begin
|
||||
h_cnt <= 0;
|
||||
hs_high <= h_cnt;
|
||||
end
|
||||
|
||||
// rising edge of HSync
|
||||
else if(hsD && !hsD2) begin
|
||||
h_cnt <= 0;
|
||||
hs_low <= h_cnt;
|
||||
v_cnt <= v_cnt + 1'd1;
|
||||
end else begin
|
||||
h_cnt <= h_cnt + 1'd1;
|
||||
end
|
||||
|
||||
vsD <= VSync;
|
||||
vsD2 <= vsD;
|
||||
|
||||
// falling edge of VSync
|
||||
if(!vsD && vsD2) begin
|
||||
v_cnt <= 0;
|
||||
vs_high <= v_cnt;
|
||||
end
|
||||
|
||||
// rising edge of VSync
|
||||
else if(vsD && !vsD2) begin
|
||||
v_cnt <= 0;
|
||||
vs_low <= v_cnt;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// area in which OSD is being displayed
|
||||
wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
|
||||
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
|
||||
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
|
||||
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
|
||||
wire [9:0] osd_hcnt = h_cnt - h_osd_start + 1'd1; // one pixel offset for osd_byte register
|
||||
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
|
||||
|
||||
wire osd_de = osd_enable &&
|
||||
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
|
||||
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
|
||||
|
||||
reg [7:0] osd_byte;
|
||||
always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
|
||||
|
||||
wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
|
||||
|
||||
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
|
||||
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
|
||||
assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
|
||||
|
||||
endmodule
|
||||
@@ -1,183 +0,0 @@
|
||||
//
|
||||
// scandoubler.v
|
||||
//
|
||||
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
// TODO: Delay vsync one line
|
||||
|
||||
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
|
||||
(
|
||||
// system interface
|
||||
input clk_sys,
|
||||
input ce_pix,
|
||||
input ce_pix_actual,
|
||||
|
||||
input hq2x,
|
||||
|
||||
// shifter video interface
|
||||
input hs_in,
|
||||
input vs_in,
|
||||
input line_start,
|
||||
|
||||
input [DWIDTH:0] r_in,
|
||||
input [DWIDTH:0] g_in,
|
||||
input [DWIDTH:0] b_in,
|
||||
input mono,
|
||||
|
||||
// output interface
|
||||
output reg hs_out,
|
||||
output vs_out,
|
||||
output [DWIDTH:0] r_out,
|
||||
output [DWIDTH:0] g_out,
|
||||
output [DWIDTH:0] b_out
|
||||
);
|
||||
|
||||
|
||||
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
|
||||
|
||||
assign vs_out = vs_in;
|
||||
|
||||
reg [2:0] phase;
|
||||
reg [2:0] ce_div;
|
||||
reg [7:0] pix_len = 0;
|
||||
wire [7:0] pl = pix_len + 1'b1;
|
||||
|
||||
reg ce_x1, ce_x4;
|
||||
reg req_line_reset;
|
||||
wire ls_in = hs_in | line_start;
|
||||
always @(negedge clk_sys) begin
|
||||
reg old_ce;
|
||||
reg [2:0] ce_cnt;
|
||||
|
||||
reg [7:0] pixsz2, pixsz4 = 0;
|
||||
|
||||
old_ce <= ce_pix;
|
||||
if(~&pix_len) pix_len <= pix_len + 1'd1;
|
||||
|
||||
ce_x4 <= 0;
|
||||
ce_x1 <= 0;
|
||||
|
||||
// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
|
||||
if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
|
||||
phase <= phase + 1'd1;
|
||||
ce_x4 <= 1;
|
||||
end
|
||||
|
||||
if(~old_ce & ce_pix) begin
|
||||
pixsz2 <= {1'b0, pl[7:1]};
|
||||
pixsz4 <= {2'b00, pl[7:2]};
|
||||
ce_x1 <= 1;
|
||||
ce_x4 <= 1;
|
||||
pix_len <= 0;
|
||||
phase <= phase + 1'd1;
|
||||
|
||||
ce_cnt <= ce_cnt + 1'd1;
|
||||
if(ce_pix_actual) begin
|
||||
phase <= 0;
|
||||
ce_div <= ce_cnt + 1'd1;
|
||||
ce_cnt <= 0;
|
||||
req_line_reset <= 0;
|
||||
end
|
||||
|
||||
if(ls_in) req_line_reset <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
reg ce_sd;
|
||||
always @(*) begin
|
||||
case(ce_div)
|
||||
2: ce_sd = !phase[0];
|
||||
4: ce_sd = !phase[1:0];
|
||||
default: ce_sd <= 1;
|
||||
endcase
|
||||
end
|
||||
|
||||
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
|
||||
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
|
||||
(
|
||||
.clk(clk_sys),
|
||||
.ce_x4(ce_x4 & ce_sd),
|
||||
.inputpixel({b_in,g_in,r_in}),
|
||||
.mono(mono),
|
||||
.disable_hq2x(~hq2x),
|
||||
.reset_frame(vs_in),
|
||||
.reset_line(req_line_reset),
|
||||
.read_y(sd_line),
|
||||
.read_x(sd_h_actual),
|
||||
.outpixel({b_out,g_out,r_out})
|
||||
);
|
||||
|
||||
reg [10:0] sd_h_actual;
|
||||
always @(*) begin
|
||||
case(ce_div)
|
||||
2: sd_h_actual = sd_h[10:1];
|
||||
4: sd_h_actual = sd_h[10:2];
|
||||
default: sd_h_actual = sd_h;
|
||||
endcase
|
||||
end
|
||||
|
||||
reg [10:0] sd_h;
|
||||
reg [1:0] sd_line;
|
||||
always @(posedge clk_sys) begin
|
||||
|
||||
reg [11:0] hs_max,hs_rise,hs_ls;
|
||||
reg [10:0] hcnt;
|
||||
reg [11:0] sd_hcnt;
|
||||
|
||||
reg hs, hs2, vs, ls;
|
||||
|
||||
if(ce_x1) begin
|
||||
hs <= hs_in;
|
||||
ls <= ls_in;
|
||||
|
||||
if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
|
||||
|
||||
// falling edge of hsync indicates start of line
|
||||
if(hs && !hs_in) begin
|
||||
hs_max <= {hcnt,1'b1};
|
||||
hcnt <= 0;
|
||||
if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
|
||||
end else begin
|
||||
hcnt <= hcnt + 1'd1;
|
||||
end
|
||||
|
||||
// save position of rising edge
|
||||
if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
|
||||
|
||||
vs <= vs_in;
|
||||
if(vs && ~vs_in) sd_line <= 0;
|
||||
end
|
||||
|
||||
if(ce_x4) begin
|
||||
hs2 <= hs_in;
|
||||
|
||||
// output counter synchronous to input and at twice the rate
|
||||
sd_hcnt <= sd_hcnt + 1'd1;
|
||||
sd_h <= sd_h + 1'd1;
|
||||
if(hs2 && !hs_in) sd_hcnt <= hs_max;
|
||||
if(sd_hcnt == hs_max) sd_hcnt <= 0;
|
||||
|
||||
// replicate horizontal sync at twice the speed
|
||||
if(sd_hcnt == hs_max) hs_out <= 0;
|
||||
if(sd_hcnt == hs_rise) hs_out <= 1;
|
||||
|
||||
if(sd_hcnt == hs_ls) sd_h <= 0;
|
||||
if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,242 +0,0 @@
|
||||
//
|
||||
//
|
||||
// Copyright (c) 2017 Sorgelig
|
||||
//
|
||||
// This program is GPL Licensed. See COPYING for the full license.
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
//
|
||||
// LINE_LENGTH: Length of display line in pixels
|
||||
// Usually it's length from HSync to HSync.
|
||||
// May be less if line_start is used.
|
||||
//
|
||||
// HALF_DEPTH: If =1 then color dept is 3 bits per component
|
||||
// For half depth 6 bits monochrome is available with
|
||||
// mono signal enabled and color = {G, R}
|
||||
|
||||
module video_mixer
|
||||
#(
|
||||
parameter LINE_LENGTH = 768,
|
||||
parameter HALF_DEPTH = 0,
|
||||
|
||||
parameter OSD_COLOR = 3'd4,
|
||||
parameter OSD_X_OFFSET = 10'd0,
|
||||
parameter OSD_Y_OFFSET = 10'd0
|
||||
)
|
||||
(
|
||||
// master clock
|
||||
// it should be multiple by (ce_pix*4).
|
||||
input clk_sys,
|
||||
|
||||
// Pixel clock or clock_enable (both are accepted).
|
||||
input ce_pix,
|
||||
|
||||
// Some systems have multiple resolutions.
|
||||
// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
|
||||
// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
|
||||
// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
|
||||
input ce_pix_actual,
|
||||
|
||||
// OSD SPI interface
|
||||
input SPI_SCK,
|
||||
input SPI_SS3,
|
||||
input SPI_DI,
|
||||
|
||||
// scanlines (00-none 01-25% 10-50% 11-75%)
|
||||
input [1:0] scanlines,
|
||||
|
||||
// 0 = HVSync 31KHz, 1 = CSync 15KHz
|
||||
input scandoubler_disable,
|
||||
|
||||
// High quality 2x scaling
|
||||
input hq2x,
|
||||
|
||||
// YPbPr always uses composite sync
|
||||
input ypbpr,
|
||||
|
||||
// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
|
||||
input ypbpr_full,
|
||||
|
||||
// color
|
||||
input [DWIDTH:0] R,
|
||||
input [DWIDTH:0] G,
|
||||
input [DWIDTH:0] B,
|
||||
|
||||
// Monochrome mode (for HALF_DEPTH only)
|
||||
input mono,
|
||||
|
||||
// interlace sync. Positive pulses.
|
||||
input HSync,
|
||||
input VSync,
|
||||
|
||||
// Falling of this signal means start of informative part of line.
|
||||
// It can be horizontal blank signal.
|
||||
// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
|
||||
// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
|
||||
// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
|
||||
// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel
|
||||
// before first informative pixel.
|
||||
input line_start,
|
||||
|
||||
// MiST video output signals
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_VS,
|
||||
output VGA_HS
|
||||
);
|
||||
|
||||
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
|
||||
|
||||
wire [DWIDTH:0] R_sd;
|
||||
wire [DWIDTH:0] G_sd;
|
||||
wire [DWIDTH:0] B_sd;
|
||||
wire hs_sd, vs_sd;
|
||||
|
||||
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
|
||||
(
|
||||
.*,
|
||||
.hs_in(HSync),
|
||||
.vs_in(VSync),
|
||||
.r_in(R),
|
||||
.g_in(G),
|
||||
.b_in(B),
|
||||
|
||||
.hs_out(hs_sd),
|
||||
.vs_out(vs_sd),
|
||||
.r_out(R_sd),
|
||||
.g_out(G_sd),
|
||||
.b_out(B_sd)
|
||||
);
|
||||
|
||||
wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd);
|
||||
wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd);
|
||||
wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd);
|
||||
|
||||
generate
|
||||
if(HALF_DEPTH) begin
|
||||
wire [5:0] r = mono ? {gt,rt} : {rt,rt};
|
||||
wire [5:0] g = mono ? {gt,rt} : {gt,gt};
|
||||
wire [5:0] b = mono ? {gt,rt} : {bt,bt};
|
||||
end else begin
|
||||
wire [5:0] r = rt;
|
||||
wire [5:0] g = gt;
|
||||
wire [5:0] b = bt;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
wire hs = (scandoubler_disable ? HSync : hs_sd);
|
||||
wire vs = (scandoubler_disable ? VSync : vs_sd);
|
||||
|
||||
reg scanline = 0;
|
||||
always @(posedge clk_sys) begin
|
||||
reg old_hs, old_vs;
|
||||
|
||||
old_hs <= hs;
|
||||
old_vs <= vs;
|
||||
|
||||
if(old_hs && ~hs) scanline <= ~scanline;
|
||||
if(old_vs && ~vs) scanline <= 0;
|
||||
end
|
||||
|
||||
wire [5:0] r_out, g_out, b_out;
|
||||
always @(*) begin
|
||||
case(scanlines & {scanline, scanline})
|
||||
1: begin // reduce 25% = 1/2 + 1/4
|
||||
r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
|
||||
g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
|
||||
b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
|
||||
end
|
||||
|
||||
2: begin // reduce 50% = 1/2
|
||||
r_out = {1'b0, r[5:1]};
|
||||
g_out = {1'b0, g[5:1]};
|
||||
b_out = {1'b0, b[5:1]};
|
||||
end
|
||||
|
||||
3: begin // reduce 75% = 1/4
|
||||
r_out = {2'b00, r[5:2]};
|
||||
g_out = {2'b00, g[5:2]};
|
||||
b_out = {2'b00, b[5:2]};
|
||||
end
|
||||
|
||||
default: begin
|
||||
r_out = r;
|
||||
g_out = g;
|
||||
b_out = b;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
wire [5:0] red, green, blue;
|
||||
osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
|
||||
(
|
||||
.*,
|
||||
|
||||
.R_in(r_out),
|
||||
.G_in(g_out),
|
||||
.B_in(b_out),
|
||||
.HSync(hs),
|
||||
.VSync(vs),
|
||||
|
||||
.R_out(red),
|
||||
.G_out(green),
|
||||
.B_out(blue)
|
||||
);
|
||||
|
||||
wire [5:0] yuv_full[225] = '{
|
||||
6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
|
||||
6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
|
||||
6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
|
||||
6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
|
||||
6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
|
||||
6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
|
||||
6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
|
||||
6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
|
||||
6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
|
||||
6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
|
||||
6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
|
||||
6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
|
||||
6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
|
||||
6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
|
||||
6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
|
||||
6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
|
||||
6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
|
||||
6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
|
||||
6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
|
||||
6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
|
||||
6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
|
||||
6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
|
||||
6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
|
||||
6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
|
||||
6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
|
||||
6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
|
||||
6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
|
||||
6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
|
||||
6'd63
|
||||
};
|
||||
|
||||
// http://marsee101.blog19.fc2.com/blog-entry-2311.html
|
||||
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
|
||||
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
|
||||
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
|
||||
|
||||
wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
|
||||
wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
|
||||
wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
|
||||
|
||||
wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
|
||||
wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
|
||||
wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
|
||||
|
||||
assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red;
|
||||
assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green;
|
||||
assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue;
|
||||
assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd;
|
||||
assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
|
||||
|
||||
endmodule
|
||||
30
Computer_MiST/Laser310_MiST/Laser310_MiST.qpf
Normal file
30
Computer_MiST/Laser310_MiST/Laser310_MiST.qpf
Normal file
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2014 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
# Date created = 12:11:46 March 17, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.1"
|
||||
DATE = "12:11:46 March 17, 2019"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "Laser310_MiST"
|
||||
433
Computer_MiST/Laser310_MiST/Laser310_MiST.qsf
Normal file
433
Computer_MiST/Laser310_MiST/Laser310_MiST.qsf
Normal file
@@ -0,0 +1,433 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2014 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
# Date created = 17:28:40 June 04, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# Laser310_MiST_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:40:24 MAY 17, 2014"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Laser310_MiST.sv
|
||||
set_global_assignment -name VERILOG_FILE rtl/LASER310_TOP.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/mc6847_vga.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/PIXEL_DISPLAY.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/CHAR_GEN.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/PIXEL_GEN.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/VIDEO_OUT.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/SVGA_DEFINES.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/SVGA_TIMING_GENERATION.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/ps2_keyboard_glb.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/tv80/tv80s.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/tv80/tv80n.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_reg.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_mcode.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_core.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_alu.v
|
||||
set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_top.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_tone.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_noise.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_latch_ctrl.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_clock_div.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_attenuator.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/spram.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/pll.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/dac.vhd
|
||||
set_global_assignment -name VERILOG_FILE rtl/reset_de.v
|
||||
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
|
||||
set_global_assignment -name TEXT_FILE rtl/tv80/Text1.txt
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/LaserKeyboard.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/LaserCassEmu.sv
|
||||
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_location_assignment PIN_7 -to LED
|
||||
set_location_assignment PIN_54 -to CLOCK_27
|
||||
set_location_assignment PIN_144 -to VGA_R[5]
|
||||
set_location_assignment PIN_143 -to VGA_R[4]
|
||||
set_location_assignment PIN_142 -to VGA_R[3]
|
||||
set_location_assignment PIN_141 -to VGA_R[2]
|
||||
set_location_assignment PIN_137 -to VGA_R[1]
|
||||
set_location_assignment PIN_135 -to VGA_R[0]
|
||||
set_location_assignment PIN_133 -to VGA_B[5]
|
||||
set_location_assignment PIN_132 -to VGA_B[4]
|
||||
set_location_assignment PIN_125 -to VGA_B[3]
|
||||
set_location_assignment PIN_121 -to VGA_B[2]
|
||||
set_location_assignment PIN_120 -to VGA_B[1]
|
||||
set_location_assignment PIN_115 -to VGA_B[0]
|
||||
set_location_assignment PIN_114 -to VGA_G[5]
|
||||
set_location_assignment PIN_113 -to VGA_G[4]
|
||||
set_location_assignment PIN_112 -to VGA_G[3]
|
||||
set_location_assignment PIN_111 -to VGA_G[2]
|
||||
set_location_assignment PIN_110 -to VGA_G[1]
|
||||
set_location_assignment PIN_106 -to VGA_G[0]
|
||||
set_location_assignment PIN_136 -to VGA_VS
|
||||
set_location_assignment PIN_119 -to VGA_HS
|
||||
set_location_assignment PIN_65 -to AUDIO_L
|
||||
set_location_assignment PIN_80 -to AUDIO_R
|
||||
set_location_assignment PIN_105 -to SPI_DO
|
||||
set_location_assignment PIN_88 -to SPI_DI
|
||||
set_location_assignment PIN_126 -to SPI_SCK
|
||||
set_location_assignment PIN_127 -to SPI_SS2
|
||||
set_location_assignment PIN_91 -to SPI_SS3
|
||||
set_location_assignment PIN_13 -to CONF_DATA0
|
||||
set_location_assignment PIN_49 -to SDRAM_A[0]
|
||||
set_location_assignment PIN_44 -to SDRAM_A[1]
|
||||
set_location_assignment PIN_42 -to SDRAM_A[2]
|
||||
set_location_assignment PIN_39 -to SDRAM_A[3]
|
||||
set_location_assignment PIN_4 -to SDRAM_A[4]
|
||||
set_location_assignment PIN_6 -to SDRAM_A[5]
|
||||
set_location_assignment PIN_8 -to SDRAM_A[6]
|
||||
set_location_assignment PIN_10 -to SDRAM_A[7]
|
||||
set_location_assignment PIN_11 -to SDRAM_A[8]
|
||||
set_location_assignment PIN_28 -to SDRAM_A[9]
|
||||
set_location_assignment PIN_50 -to SDRAM_A[10]
|
||||
set_location_assignment PIN_30 -to SDRAM_A[11]
|
||||
set_location_assignment PIN_32 -to SDRAM_A[12]
|
||||
set_location_assignment PIN_83 -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_79 -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_77 -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_76 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_72 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_71 -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_69 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_68 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_86 -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_87 -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_98 -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_99 -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_100 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_101 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_103 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_104 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_58 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_51 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_85 -to SDRAM_DQMH
|
||||
set_location_assignment PIN_67 -to SDRAM_DQML
|
||||
set_location_assignment PIN_60 -to SDRAM_nRAS
|
||||
set_location_assignment PIN_64 -to SDRAM_nCAS
|
||||
set_location_assignment PIN_66 -to SDRAM_nWE
|
||||
set_location_assignment PIN_59 -to SDRAM_nCS
|
||||
set_location_assignment PIN_33 -to SDRAM_CKE
|
||||
set_location_assignment PIN_43 -to SDRAM_CLK
|
||||
set_location_assignment PLL_1 -to "pll27:pll|altpll:altpll_component"
|
||||
|
||||
# Classic Timing Assignments
|
||||
# ==========================
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name SAVE_DISK_SPACE OFF
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY Laser310_MiST
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
|
||||
# SignalTap II Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
|
||||
|
||||
# Power Estimation Assignments
|
||||
# ============================
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
# Advanced I/O Timing Assignments
|
||||
# ===============================
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
|
||||
# ---------------------------
|
||||
# start ENTITY(Laser310_MiST)
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[8]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[9]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[10]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[11]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[12]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[15]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_BA[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_BA[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQML
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQMH
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nRAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nCAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nWE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nCS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_CKE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_CLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_HS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_VS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to LED
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_DO
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to CONF_DATA0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_L
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_R
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CONF_DATA0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQMH
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQML
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nRAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nCAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nWE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nCS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to CLOCK_27
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_DI
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SCK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SS2
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SS3
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
# end ENTITY(Laser310_MiST)
|
||||
# -------------------------
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
33
Computer_MiST/Laser310_MiST/Laser310_MiST.sdc
Normal file
33
Computer_MiST/Laser310_MiST/Laser310_MiST.sdc
Normal file
@@ -0,0 +1,33 @@
|
||||
#************************************************************
|
||||
# THIS IS A WIZARD-GENERATED FILE.
|
||||
#
|
||||
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
|
||||
#
|
||||
#************************************************************
|
||||
|
||||
# Copyright (C) 1991-2014 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
# Clock constraints
|
||||
|
||||
create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27}]
|
||||
create_clock -name {SPI_SCK} -period 10.000 -waveform { 0.000 0.500 } [get_ports {SPI_SCK}]
|
||||
|
||||
# Automatically constrain PLL and other generated clocks
|
||||
derive_pll_clocks -create_base_clocks
|
||||
|
||||
# Automatically calculate clock uncertainty to jitter and other effects.
|
||||
derive_clock_uncertainty
|
||||
11
Computer_MiST/Laser310_MiST/Laser310_MiST.srf
Normal file
11
Computer_MiST/Laser310_MiST/Laser310_MiST.srf
Normal file
@@ -0,0 +1,11 @@
|
||||
{ "" "" "" "Verilog HDL warning at hq2x.sv(247): extended using \"x\" or \"z\"" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL warning at tv80_core.v(300): extended using \"x\" or \"z\"" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL macro warning at hq2x.sv(26): overriding existing definition for macro \"BITS_TO_FIT\", which was defined in \"rtl/scandoubler.v\", line 109" { } { } 0 10274 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10090 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 332060 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10259 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10030 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
BIN
Computer_MiST/Laser310_MiST/Snapshot/Laser310_MiST.rbf
Normal file
BIN
Computer_MiST/Laser310_MiST/Snapshot/Laser310_MiST.rbf
Normal file
Binary file not shown.
15
Computer_MiST/Laser310_MiST/clean.bat
Normal file
15
Computer_MiST/Laser310_MiST/clean.bat
Normal file
@@ -0,0 +1,15 @@
|
||||
@echo off
|
||||
del /s *.bak
|
||||
del /s *.orig
|
||||
del /s *.rej
|
||||
rmdir /s /q db
|
||||
rmdir /s /q incremental_db
|
||||
rmdir /s /q output_files
|
||||
rmdir /s /q simulation
|
||||
rmdir /s /q greybox_tmp
|
||||
del PLLJ_PLLSPE_INFO.txt
|
||||
del *.qws
|
||||
del *.ppf
|
||||
del *.qip
|
||||
del *.ddb
|
||||
pause
|
||||
BIN
Computer_MiST/Laser310_MiST/compumuse.pdf
Normal file
BIN
Computer_MiST/Laser310_MiST/compumuse.pdf
Normal file
Binary file not shown.
68
Computer_MiST/Laser310_MiST/rtl/CHAR_GEN.v
Normal file
68
Computer_MiST/Laser310_MiST/rtl/CHAR_GEN.v
Normal file
@@ -0,0 +1,68 @@
|
||||
module CHAR_GEN(
|
||||
// control
|
||||
reset,
|
||||
|
||||
char_code,
|
||||
subchar_line,
|
||||
subchar_pixel,
|
||||
|
||||
pixel_clock,
|
||||
pixel_on
|
||||
);
|
||||
|
||||
input pixel_clock;
|
||||
input reset;
|
||||
|
||||
input [7:0] char_code;
|
||||
input [4:0] subchar_line; // line number within 12 line block
|
||||
input [3:0] subchar_pixel; // pixel position within 8 pixel block
|
||||
|
||||
output pixel_on;
|
||||
|
||||
reg [7:0] latched_data;
|
||||
reg pixel_on;
|
||||
|
||||
wire [11:0] rom_addr = {char_code[7:0], subchar_line[4:1]};
|
||||
wire [7:0] rom_data;
|
||||
|
||||
|
||||
// instantiate the character generator ROM
|
||||
//CHAR_GEN_ROM CHAR_GEN_ROM
|
||||
//(
|
||||
// pixel_clock,
|
||||
// rom_addr,
|
||||
// rom_data
|
||||
//);
|
||||
|
||||
sprom #(
|
||||
.init_file("./roms/charrom_4k.mif"),
|
||||
.widthad_a(12),
|
||||
.width_a(8))
|
||||
CHAR_GEN_ROM(
|
||||
.address(rom_addr),
|
||||
.clock(pixel_clock),
|
||||
.q(rom_data)
|
||||
);
|
||||
|
||||
|
||||
// serialize the CHARACTER MODE data
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
pixel_on = 1'b0;
|
||||
latched_data = 8'h00;
|
||||
end
|
||||
|
||||
else begin
|
||||
case(subchar_pixel)
|
||||
4'b0101:
|
||||
latched_data [7:0] = {rom_data[0],rom_data[1],rom_data[2],rom_data[3],rom_data[4],rom_data[5],rom_data[6],rom_data[7]};
|
||||
default:
|
||||
if(subchar_pixel[0]==1'b0)
|
||||
{pixel_on,latched_data [7:1]} <= latched_data [7:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endmodule //CHAR_GEN
|
||||
19
Computer_MiST/Laser310_MiST/rtl/CHAR_GEN_ROM.v
Normal file
19
Computer_MiST/Laser310_MiST/rtl/CHAR_GEN_ROM.v
Normal file
@@ -0,0 +1,19 @@
|
||||
module CHAR_GEN_ROM
|
||||
(
|
||||
pixel_clock,
|
||||
address,
|
||||
data
|
||||
);
|
||||
|
||||
input pixel_clock;
|
||||
input [11:0] address;
|
||||
output wire [7:0] data;
|
||||
|
||||
// Character generator
|
||||
char_rom_4k_altera char_rom(
|
||||
.address(address),
|
||||
.clock(pixel_clock),
|
||||
.q(data)
|
||||
);
|
||||
|
||||
endmodule //CHAR_GEN_ROM
|
||||
1100
Computer_MiST/Laser310_MiST/rtl/LASER310_TOP.v
Normal file
1100
Computer_MiST/Laser310_MiST/rtl/LASER310_TOP.v
Normal file
File diff suppressed because it is too large
Load Diff
134
Computer_MiST/Laser310_MiST/rtl/Laser310_MiST.sv
Normal file
134
Computer_MiST/Laser310_MiST/rtl/Laser310_MiST.sv
Normal file
@@ -0,0 +1,134 @@
|
||||
|
||||
module Laser310_MiST
|
||||
(
|
||||
output LED,
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_HS,
|
||||
output VGA_VS,
|
||||
output AUDIO_L,
|
||||
output AUDIO_R,
|
||||
input SPI_SCK,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
input SPI_SS2,
|
||||
input SPI_SS3,
|
||||
input CONF_DATA0,
|
||||
input CLOCK_27
|
||||
);
|
||||
|
||||
`include "rtl\build_id.v"
|
||||
|
||||
localparam CONF_STR = {
|
||||
"Laser310;;",
|
||||
"O1,Turbo,Off,On;",
|
||||
"O2,Dos Rom,Off,On;",
|
||||
"O34,Scanlines,Off,25%,50%,75%;",
|
||||
"O5,SHRG,Off,On;",
|
||||
"T6,Reset;",
|
||||
"V,v1.00.",`BUILD_DATE
|
||||
};
|
||||
|
||||
assign LED = 1;
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
|
||||
wire clk_50, clk_25, clk_10, clk_6p25;
|
||||
wire pll_locked;
|
||||
pll pll(
|
||||
.inclk0(CLOCK_27),
|
||||
.areset(0),
|
||||
.c0(clk_50),
|
||||
.c1(clk_25),
|
||||
.c2(clk_10),
|
||||
.c3(clk_6p25)
|
||||
);
|
||||
|
||||
wire [31:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire [1:0] switches;
|
||||
wire [7:0] joystick_0;
|
||||
wire [7:0] joystick_1;
|
||||
wire scandoublerD;
|
||||
wire ypbpr;
|
||||
wire key_pressed;
|
||||
wire [7:0] key_code;
|
||||
wire key_strobe;
|
||||
reg [1:0] audio;
|
||||
wire [7:0] audio_s;
|
||||
wire ce_pix;
|
||||
wire hs, vs;
|
||||
wire [7:0] r,g,b;
|
||||
|
||||
LASER310_TOP LASER310_TOP(
|
||||
.CLK50MHZ(clk_50),
|
||||
.CLK25MHZ(clk_25),
|
||||
.CLK10MHZ(clk_10),
|
||||
.RESET(~(status[0] | status[6] | buttons[1])),
|
||||
.VGA_RED(r),
|
||||
.VGA_GREEN(g),
|
||||
.VGA_BLUE(b),
|
||||
.VGA_HS(hs),
|
||||
.VGA_VS(vs),
|
||||
.AUD_ADCDAT(audio),
|
||||
.audio_s(audio_s),
|
||||
// .PS2_KBCLK(ps2_kbd_clk),
|
||||
// .PS2_KBDAT(ps2_kbd_data),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_code (key_code ),
|
||||
.SWITCH({"00000",!status[5],!status[2],!status[1]}),
|
||||
.UART_RXD(),
|
||||
.UART_TXD()
|
||||
);
|
||||
|
||||
mist_video #(.COLOR_DEPTH(6)) mist_video(
|
||||
.clk_sys(clk_25),
|
||||
.SPI_SCK(SPI_SCK),
|
||||
.SPI_SS3(SPI_SS3),
|
||||
.SPI_DI(SPI_DI),
|
||||
.R(r[5:0]),
|
||||
.G(g[5:0]),
|
||||
.B(b[5:0]),
|
||||
.HSync(hs),
|
||||
.VSync(vs),
|
||||
.VGA_R(VGA_R),
|
||||
.VGA_G(VGA_G),
|
||||
.VGA_B(VGA_B),
|
||||
.VGA_VS(VGA_VS),
|
||||
.VGA_HS(VGA_HS),
|
||||
.scandoubler_disable(1'b1),//scandoublerD),
|
||||
.scanlines(scandoublerD ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
|
||||
.ypbpr(ypbpr)
|
||||
);
|
||||
|
||||
user_io #(
|
||||
.STRLEN(($size(CONF_STR)>>3)))
|
||||
user_io(
|
||||
.clk_sys (clk_25 ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_CLK (SPI_SCK ),
|
||||
.SPI_SS_IO (CONF_DATA0 ),
|
||||
.SPI_MISO (SPI_DO ),
|
||||
.SPI_MOSI (SPI_DI ),
|
||||
.buttons (buttons ),
|
||||
.switches (switches ),
|
||||
.scandoubler_disable (scandoublerD ),
|
||||
.ypbpr (ypbpr ),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_code (key_code ),
|
||||
.status (status )
|
||||
);
|
||||
|
||||
dac #(
|
||||
.C_bits(15))
|
||||
dac(
|
||||
.clk_i(clk_25),
|
||||
.res_n_i(1),
|
||||
// .dac_i({~audio_s[7],audio_s[6:0],{4{audio}}}),
|
||||
.dac_i({8{audio}}),
|
||||
.dac_o(AUDIO_L)
|
||||
);
|
||||
|
||||
endmodule
|
||||
122
Computer_MiST/Laser310_MiST/rtl/LaserCassEmu.sv
Normal file
122
Computer_MiST/Laser310_MiST/rtl/LaserCassEmu.sv
Normal file
@@ -0,0 +1,122 @@
|
||||
module LaserCassEmu(
|
||||
input wire [15:0] CPU_A,
|
||||
input wire CPU_RD,
|
||||
input wire CPU_WR
|
||||
);
|
||||
// cassette
|
||||
|
||||
(*keep*)wire [1:0] CASS_OUT;
|
||||
(*keep*)wire CASS_IN;
|
||||
(*keep*)wire CASS_IN_L;
|
||||
(*keep*)wire CASS_IN_R;
|
||||
|
||||
reg [7:0] LATCHED_IO_DATA_WR;
|
||||
// 用于外部磁带仿真计数
|
||||
//(*keep*)reg EMU_CASS_CLK;
|
||||
|
||||
(*keep*)wire EMU_CASS_EN;
|
||||
(*keep*)wire [1:0] EMU_CASS_DAT;
|
||||
|
||||
`ifdef CASS_EMU
|
||||
|
||||
wire CASS_BUF_RD;
|
||||
wire [15:0] CASS_BUF_A;
|
||||
wire CASS_BUF_WR;
|
||||
wire [7:0] CASS_BUF_DAT;
|
||||
wire [7:0] CASS_BUF_Q;
|
||||
|
||||
// F9 CASS PLAY
|
||||
// F10 CASS STOP
|
||||
|
||||
EMU_CASS_KEY EMU_CASS_KEY(
|
||||
KEY_Fxx[8],
|
||||
KEY_Fxx[9],
|
||||
// cass emu
|
||||
CASS_BUF_RD,
|
||||
//
|
||||
CASS_BUF_A,
|
||||
CASS_BUF_WR,
|
||||
CASS_BUF_DAT,
|
||||
CASS_BUF_Q,
|
||||
// Control Signals
|
||||
EMU_CASS_EN,
|
||||
EMU_CASS_DAT,
|
||||
|
||||
// key emu
|
||||
EMU_KEY,
|
||||
EMU_KEY_EX,
|
||||
EMU_KEY_EN,
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
UART_RXD,
|
||||
UART_TXD,
|
||||
|
||||
// System
|
||||
TURBO_SPEED,
|
||||
// Clock: 10MHz
|
||||
CLK10MHZ,
|
||||
RESET_N
|
||||
);
|
||||
|
||||
|
||||
`ifdef CASS_EMU_16K
|
||||
|
||||
cass_ram_16k_altera cass_buf(
|
||||
.address(CASS_BUF_A[13:0]),
|
||||
.clock(CLK10MHZ),
|
||||
.data(CASS_BUF_DI),
|
||||
.wren(CASS_BUF_WR),
|
||||
.q(CASS_BUF_Q)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
`ifdef CASS_EMU_8K
|
||||
|
||||
cass_ram_8k_altera cass_buf(
|
||||
.address(CASS_BUF_A[12:0]),
|
||||
.clock(CLK10MHZ),
|
||||
.data(CASS_BUF_DI),
|
||||
.wren(CASS_BUF_WR),
|
||||
.q(CASS_BUF_Q)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
`ifdef CASS_EMU_4K
|
||||
|
||||
cass_ram_4k_altera cass_buf(
|
||||
.address(CASS_BUF_A[11:0]),
|
||||
.clock(CLK10MHZ),
|
||||
.data(CASS_BUF_DAT),
|
||||
.wren(CASS_BUF_WR),
|
||||
.q(CASS_BUF_Q)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
`ifdef CASS_EMU_2K
|
||||
|
||||
cass_ram_2k_altera cass_buf(
|
||||
.address(CASS_BUF_A[10:0]),
|
||||
.clock(CLK10MHZ),
|
||||
.data(CASS_BUF_DAT),
|
||||
.wren(CASS_BUF_WR),
|
||||
.q(CASS_BUF_Q)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
|
||||
assign CASS_OUT = EMU_CASS_EN ? EMU_CASS_DAT : {LATCHED_IO_DATA_WR[2], 1'b0};
|
||||
|
||||
(*keep*)wire trap = (CPU_RD|CPU_WR) && (CPU_A[15:12] == 4'h0);
|
||||
|
||||
endmodule
|
||||
414
Computer_MiST/Laser310_MiST/rtl/LaserKeyboard.sv
Normal file
414
Computer_MiST/Laser310_MiST/rtl/LaserKeyboard.sv
Normal file
@@ -0,0 +1,414 @@
|
||||
module LaserKeyboard(
|
||||
input wire CLK50MHZ,
|
||||
input wire [15:0] CPU_A,
|
||||
input wire RESET,
|
||||
input wire CASS_IN,
|
||||
input wire PS2_KBCLK,
|
||||
input wire PS2_KBDAT
|
||||
);
|
||||
|
||||
|
||||
// keyboard
|
||||
reg [4:0] KB_CLK;
|
||||
reg [16:0] RESET_KEY_COUNT;
|
||||
wire [7:0] SCAN;
|
||||
wire PRESS;
|
||||
wire PRESS_N;
|
||||
wire EXTENDED;
|
||||
reg BOOTROM_EN;
|
||||
reg [7:0] BOOTROM_BANK;
|
||||
reg AUTOSTARTROM_EN;
|
||||
reg [7:0] AUTOSTARTROM_BANK;
|
||||
reg [63:0] KEY;
|
||||
reg [9:0] KEY_EX;
|
||||
reg [11:0] KEY_Fxx;
|
||||
wire [7:0] KEY_DATA;
|
||||
//reg [63:0] LAST_KEY;
|
||||
//reg CAPS_CLK;
|
||||
//reg CAPS;
|
||||
wire A_KEY_PRESSED;
|
||||
|
||||
reg [7:0] LATCHED_KEY_DATA;
|
||||
|
||||
// emu keyboard
|
||||
wire [63:0] EMU_KEY;
|
||||
wire [9:0] EMU_KEY_EX;
|
||||
wire EMU_KEY_EN;
|
||||
// keyboard
|
||||
|
||||
/*****************************************************************************
|
||||
* Convert PS/2 keyboard to ASCII keyboard
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
KD5 KD4 KD3 KD2 KD1 KD0 扫描用地址
|
||||
A0 R Q E W T 68FEH 0
|
||||
A1 F A D CTRL S G 68FDH 8
|
||||
A2 V Z C SHFT X B 68FBH 16
|
||||
A3 4 1 3 2 5 68F7H 24
|
||||
A4 M 空格 ， . N 68EFH 32
|
||||
A5 7 0 8 - 9 6 68DFH 40
|
||||
A6 U P I RETN O Y 68BFH 48
|
||||
A7 J ； K : L H 687FH 56
|
||||
*/
|
||||
|
||||
// 7: 0
|
||||
// 15: 8
|
||||
// 23:16
|
||||
// 31:24
|
||||
// 39:32
|
||||
// 47:40
|
||||
// 55:48
|
||||
// 63:56
|
||||
|
||||
|
||||
|
||||
// 键盘检测的方法，就是循环地问每一行线发送低电平信号，也就是用该地址线为“0”的地址去读取数据。
|
||||
// 例如，检测第一行时，使A0为0，其余为1；加上选通IC4的高五位地址01101，成为01101***11111110B（A8~A10不起作用，
|
||||
// 可为任意值，故68FEH，69FEH，6AFEH，6BFEH，6CFEH，6DFEH，6EFEH，6FFEH均可）。
|
||||
// 读 6800H 判断是否有按键按下。
|
||||
|
||||
// The method of keyboard detection is to cyclically ask each line to send a low level signal,
|
||||
// that is, to read the data with the address line "0".
|
||||
// For example, when detecting the first line, make A0 0 and the rest 1; plus the high five-bit address 01101 of the strobe IC4,
|
||||
// become 01101***11111110B (A8~A10 does not work,
|
||||
// It can be any value, so 68FEH, 69FEH, 6AFEH, 6BFEH, 6CFEH, 6DFEH, 6EFEH, 6FFEH can be).
|
||||
// Read 6800H to determine if there is a button press.
|
||||
|
||||
// 键盘选通，整个竖列有一个选通的位置被按下，对应值为0。
|
||||
// The keyboard is strobed, and a strobe position is pressed in the entire vertical column, and the corresponding value is 0.
|
||||
|
||||
// 键盘扩展
|
||||
// 加入方向键盘
|
||||
// Keyboard extension
|
||||
|
||||
// left: ctrl M 37 KEY_EX[5]
|
||||
// right: ctrl , 35 KEY_EX[6]
|
||||
// up: ctrl . 33 KEY_EX[4]
|
||||
// down: ctrl space 36 KEY_EX[7]
|
||||
// esc: ctrl - 42 KEY_EX[3]
|
||||
// backspace: ctrl M 37 KEY_EX[8]
|
||||
|
||||
// R-Shift
|
||||
|
||||
|
||||
wire [63:0] KEY_C = EMU_KEY_EN?EMU_KEY:KEY;
|
||||
wire [9:0] KEY_EX_C = EMU_KEY_EN?EMU_KEY_EX:KEY_EX;
|
||||
|
||||
//wire KEY_CTRL_ULRD = (KEY_EX[7:4]==4'b1111);
|
||||
wire KEY_CTRL_ULRD_BRK = (KEY_EX[8:3]==6'b111111);
|
||||
|
||||
wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY_C[61], KEY_C[53], KEY_C[45], KEY_C[37]&KEY_EX_C[5]&KEY_EX_C[8], KEY_C[29], KEY_C[21], KEY_C[13], KEY_C[ 5]})==8'hff;
|
||||
wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY_C[60], KEY_C[52], KEY_C[44], KEY_C[36]&KEY_EX_C[7], KEY_C[28], KEY_C[20], KEY_C[12], KEY_C[ 4]})==8'hff;
|
||||
wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY_C[59], KEY_C[51], KEY_C[43], KEY_C[35]&KEY_EX_C[6], KEY_C[27], KEY_C[19], KEY_C[11], KEY_C[ 3]})==8'hff;
|
||||
wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY_C[58], KEY_C[50], KEY_C[42]&KEY_EX_C[3], KEY_C[34], KEY_C[26], KEY_C[18]&KEY_EX_C[0], KEY_C[10]&KEY_CTRL_ULRD_BRK, KEY_C[ 2]})==8'hff;
|
||||
wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY_C[57], KEY_C[49], KEY_C[41], KEY_C[33]&KEY_EX_C[4], KEY_C[25], KEY_C[17], KEY_C[ 9], KEY_C[ 1]})==8'hff;
|
||||
wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY_C[56], KEY_C[48], KEY_C[40], KEY_C[32], KEY_C[24], KEY_C[16], KEY_C[ 8], KEY_C[ 0]})==8'hff;
|
||||
|
||||
/*
|
||||
wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY[61], KEY[53], KEY[45], KEY[37], KEY[29], KEY[21], KEY[13], KEY[ 5]})==8'hff;
|
||||
wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY[60], KEY[52], KEY[44], KEY[36], KEY[28], KEY[20], KEY[12], KEY[ 4]})==8'hff;
|
||||
wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY[59], KEY[51], KEY[43], KEY[35], KEY[27], KEY[19], KEY[11], KEY[ 3]})==8'hff;
|
||||
wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY[58], KEY[50], KEY[42], KEY[34], KEY[26], KEY[18], KEY[10], KEY[ 2]})==8'hff;
|
||||
wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY[57], KEY[49], KEY[41], KEY[33], KEY[25], KEY[17], KEY[ 9], KEY[ 1]})==8'hff;
|
||||
wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY[56], KEY[48], KEY[40], KEY[32], KEY[24], KEY[16], KEY[ 8], KEY[ 0]})==8'hff;
|
||||
*/
|
||||
|
||||
wire KEY_DATA_BIT7 = 1'b1; // 没有空置，具体用途没有理解
|
||||
//wire KEY_DATA_BIT6 = CASS_IN;
|
||||
wire KEY_DATA_BIT6 = ~CASS_IN;
|
||||
|
||||
assign KEY_DATA = { KEY_DATA_BIT7, KEY_DATA_BIT6, KEY_DATA_BIT5, KEY_DATA_BIT4, KEY_DATA_BIT3, KEY_DATA_BIT2, KEY_DATA_BIT1, KEY_DATA_BIT0 };
|
||||
|
||||
/*
|
||||
assign KEY_DATA = (CPU_A[0]==1'b0) ? KEY[ 7: 0] :
|
||||
(CPU_A[1]==1'b0) ? KEY[15: 8] :
|
||||
(CPU_A[2]==1'b0) ? KEY[23:16] :
|
||||
(CPU_A[3]==1'b0) ? KEY[31:24] :
|
||||
(CPU_A[4]==1'b0) ? KEY[39:32] :
|
||||
(CPU_A[5]==1'b0) ? KEY[47:40] :
|
||||
(CPU_A[6]==1'b0) ? KEY[55:48] :
|
||||
(CPU_A[7]==1'b0) ? KEY[63:56] :
|
||||
8'hff;
|
||||
|
||||
assign KEY_DATA =
|
||||
(CPU_A[7]==1'b0) ? KEY[63:56] :
|
||||
(CPU_A[6]==1'b0) ? KEY[55:48] :
|
||||
(CPU_A[5]==1'b0) ? KEY[47:40] :
|
||||
(CPU_A[4]==1'b0) ? KEY[39:32] :
|
||||
(CPU_A[3]==1'b0) ? KEY[31:24] :
|
||||
(CPU_A[2]==1'b0) ? KEY[23:16] :
|
||||
(CPU_A[1]==1'b0) ? KEY[15: 8] :
|
||||
(CPU_A[0]==1'b0) ? KEY[ 7: 0] :
|
||||
8'hff;
|
||||
*/
|
||||
|
||||
|
||||
assign A_KEY_PRESSED = (KEY[63:0] == 64'hFFFFFFFFFFFFFFFF) ? 1'b0:1'b1;
|
||||
|
||||
always @(posedge KB_CLK[3] or negedge RESET)
|
||||
begin
|
||||
if(~RESET)
|
||||
begin
|
||||
KEY <= 64'hFFFFFFFFFFFFFFFF;
|
||||
KEY_EX <= 10'h3FF;
|
||||
KEY_Fxx <= 12'h000;
|
||||
// CAPS_CLK <= 1'b0;
|
||||
RESET_KEY_COUNT <= 17'h1FFFF;
|
||||
|
||||
BOOTROM_BANK <= 0;
|
||||
BOOTROM_EN <= 1'b0;
|
||||
|
||||
AUTOSTARTROM_BANK <= 0;
|
||||
AUTOSTARTROM_EN <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
//KEY[?] <= CAPS;
|
||||
if(RESET_KEY_COUNT[16]==1'b0)
|
||||
RESET_KEY_COUNT <= RESET_KEY_COUNT+1;
|
||||
|
||||
case(SCAN)
|
||||
/*8'h07:
|
||||
begin
|
||||
KEY_Fxx[11] <= PRESS; // F12 RESET
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b0;
|
||||
BOOTROM_BANK <= 0;
|
||||
AUTOSTARTROM_EN <= 1'b0;
|
||||
AUTOSTARTROM_BANK <= 0;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h78: KEY_Fxx[10] <= PRESS; // F11
|
||||
8'h09: KEY_Fxx[ 9] <= PRESS; // F10 CASS STOP
|
||||
8'h01: KEY_Fxx[ 8] <= PRESS; // F9 CASS PLAY
|
||||
8'h0A:
|
||||
begin
|
||||
KEY_Fxx[ 7] <= PRESS; // F8 Ctrl or L-Shift BOOT 8
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 39;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 23;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h83:
|
||||
begin
|
||||
KEY_Fxx[ 6] <= PRESS; // F7 Ctrl or L-Shift BOOT 7
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 38;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 22;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h0B:
|
||||
begin
|
||||
KEY_Fxx[ 5] <= PRESS; // F6 Ctrl or L-Shift BOOT 6
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 37;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 21;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h03:
|
||||
begin
|
||||
KEY_Fxx[ 4] <= PRESS; // F5 Ctrl or L-Shift BOOT 5
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 36;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 20;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h0C:
|
||||
begin
|
||||
KEY_Fxx[ 3] <= PRESS; // F4 Ctrl or L-Shift BOOT 4
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 35;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 19;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h04:
|
||||
begin
|
||||
KEY_Fxx[ 2] <= PRESS; // F3 Ctrl or L-Shift BOOT 3
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 34;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 18;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h06:
|
||||
begin
|
||||
KEY_Fxx[ 1] <= PRESS; // F2 Ctrl or L-Shift BOOT 2
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 33;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 17;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h05:
|
||||
begin
|
||||
KEY_Fxx[ 0] <= PRESS; // F1 Ctrl or L-Shift BOOT 1
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 32;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 16;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end*/
|
||||
|
||||
8'h16: KEY[28] <= PRESS_N; // 1 !
|
||||
8'h1E: KEY[25] <= PRESS_N; // 2 @
|
||||
8'h26: KEY[27] <= PRESS_N; // 3 #
|
||||
8'h25: KEY[29] <= PRESS_N; // 4 $
|
||||
8'h2E: KEY[24] <= PRESS_N; // 5 %
|
||||
8'h36: KEY[40] <= PRESS_N; // 6 ^
|
||||
8'h3D: KEY[45] <= PRESS_N; // 7 &
|
||||
// 8'h0D: KEY[?] <= PRESS_N; // TAB
|
||||
8'h3E: KEY[43] <= PRESS_N; // 8 *
|
||||
8'h46: KEY[41] <= PRESS_N; // 9 (
|
||||
8'h45: KEY[44] <= PRESS_N; // 0 )
|
||||
8'h4E: KEY[42] <= PRESS_N; // - _
|
||||
// 8'h55: KEY[?] <= PRESS_N; // = +
|
||||
8'h66: KEY_EX[8] <= PRESS_N; // backspace
|
||||
// 8'h0E: KEY[?] <= PRESS_N; // ` ~
|
||||
// 8'h5D: KEY[?] <= PRESS_N; // \ |
|
||||
8'h49: KEY[33] <= PRESS_N; // . >
|
||||
8'h4b: KEY[57] <= PRESS_N; // L
|
||||
8'h44: KEY[49] <= PRESS_N; // O
|
||||
// 8'h11 KEY[?] <= PRESS_N; // line feed (really right ALT (Extended) see below
|
||||
8'h5A: KEY[50] <= PRESS_N; // CR
|
||||
// 8'h54: KEY[?] <= PRESS_N; // [ {
|
||||
// 8'h5B: KEY[?] <= PRESS_N; // ] }
|
||||
8'h52: KEY[58] <= PRESS_N; // ' "
|
||||
8'h1D: KEY[ 1] <= PRESS_N; // W
|
||||
8'h24: KEY[ 3] <= PRESS_N; // E
|
||||
8'h2D: KEY[ 5] <= PRESS_N; // R
|
||||
8'h2C: KEY[ 0] <= PRESS_N; // T
|
||||
8'h35: KEY[48] <= PRESS_N; // Y
|
||||
8'h3C: KEY[53] <= PRESS_N; // U
|
||||
8'h43: KEY[51] <= PRESS_N; // I
|
||||
8'h1B: KEY[ 9] <= PRESS_N; // S
|
||||
8'h23: KEY[11] <= PRESS_N; // D
|
||||
8'h2B: KEY[13] <= PRESS_N; // F
|
||||
8'h34: KEY[ 8] <= PRESS_N; // G
|
||||
8'h33: KEY[56] <= PRESS_N; // H
|
||||
8'h3B: KEY[61] <= PRESS_N; // J
|
||||
8'h42: KEY[59] <= PRESS_N; // K
|
||||
8'h22: KEY[17] <= PRESS_N; // X
|
||||
8'h21: KEY[19] <= PRESS_N; // C
|
||||
8'h2a: KEY[21] <= PRESS_N; // V
|
||||
8'h32: KEY[16] <= PRESS_N; // B
|
||||
8'h31: KEY[32] <= PRESS_N; // N
|
||||
8'h3a: KEY[37] <= PRESS_N; // M
|
||||
8'h41: KEY[35] <= PRESS_N; // , <
|
||||
8'h15: KEY[ 4] <= PRESS_N; // Q
|
||||
8'h1C: KEY[12] <= PRESS_N; // A
|
||||
8'h1A: KEY[20] <= PRESS_N; // Z
|
||||
8'h29: KEY[36] <= PRESS_N; // Space
|
||||
// 8'h4A: KEY[?] <= PRESS_N; // / ?
|
||||
8'h4C: KEY[60] <= PRESS_N; // ; :
|
||||
8'h4D: KEY[52] <= PRESS_N; // P
|
||||
8'h14: KEY[10] <= PRESS_N; // Ctrl either left or right
|
||||
8'h12: KEY[18] <= PRESS_N; // L-Shift
|
||||
8'h59: KEY_EX[0] <= PRESS_N; // R-Shift
|
||||
8'h11:
|
||||
begin
|
||||
if(~EXTENDED)
|
||||
KEY_EX[1] <= PRESS_N; // Repeat really left ALT
|
||||
else
|
||||
KEY_EX[2] <= PRESS_N; // LF really right ALT
|
||||
end
|
||||
8'h76: KEY_EX[3] <= PRESS_N; // Esc
|
||||
8'h75: KEY_EX[4] <= PRESS_N; // up
|
||||
8'h6B: KEY_EX[5] <= PRESS_N; // left
|
||||
8'h74: KEY_EX[6] <= PRESS_N; // right
|
||||
8'h72: KEY_EX[7] <= PRESS_N; // down
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
always @ (posedge CLK50MHZ) // 50MHz
|
||||
KB_CLK <= KB_CLK + 1'b1; // 50/32 = 1.5625 MHz
|
||||
|
||||
ps2_keyboard KEYBOARD(
|
||||
.RESET_N(~RESET),
|
||||
.CLK(KB_CLK[4]),
|
||||
.PS2_CLK(PS2_KBCLK),
|
||||
.PS2_DATA(PS2_KBDAT),
|
||||
.RX_SCAN(SCAN),
|
||||
.RX_PRESSED(PRESS),
|
||||
.RX_EXTENDED(EXTENDED)
|
||||
);
|
||||
|
||||
assign PRESS_N = ~PRESS;
|
||||
|
||||
|
||||
endmodule
|
||||
372
Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80ALU.v
Normal file
372
Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80ALU.v
Normal file
@@ -0,0 +1,372 @@
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// This file is part of the NextZ80 project
|
||||
// http://www.opencores.org/cores/nextz80/
|
||||
//
|
||||
// Filename: NextZ80ALU.v
|
||||
// Description: Implementation of Z80 compatible CPU - ALU
|
||||
// Version 1.0
|
||||
// Creation date: 28Jan2011 - 18Mar2011
|
||||
//
|
||||
// Author: Nicolae Dumitrache
|
||||
// e-mail: ndumitrache@opencores.org
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2011 Nicolae Dumitrache
|
||||
//
|
||||
// This source file may be used and distributed without
|
||||
// restriction provided that this copyright statement is not
|
||||
// removed from the file and that any derivative work contains
|
||||
// the original copyright notice and the associated disclaimer.
|
||||
//
|
||||
// This source file is free software; you can redistribute it
|
||||
// and/or modify it under the terms of the GNU Lesser General
|
||||
// Public License as published by the Free Software Foundation;
|
||||
// either version 2.1 of the License, or (at your option) any
|
||||
// later version.
|
||||
//
|
||||
// This source is distributed in the hope that it will be
|
||||
// useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
// PURPOSE. See the GNU Lesser General Public License for more
|
||||
// details.
|
||||
//
|
||||
// You should have received a copy of the GNU Lesser General
|
||||
// Public License along with this source; if not, download it
|
||||
// from http://www.opencores.org/lgpl.shtml
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//FLAGS: S Z X1 N X2 PV N C
|
||||
// OP[4:0]
|
||||
// 00000 - ADD D0,D1
|
||||
// 00001 - ADC D0,D1
|
||||
// 00010 - SUB D0,D1
|
||||
// 00011 - SBC D0,D1
|
||||
// 00100 - AND D0,D1
|
||||
// 00101 - XOR D0,D1
|
||||
// 00110 - OR D0,D1
|
||||
// 00111 - CP D0,D1
|
||||
// 01000 - INC D0
|
||||
// 01001 - CPL D0
|
||||
// 01010 - DEC D0
|
||||
// 01011 - RRD
|
||||
// 01100 - RLD
|
||||
// 01101 - DAA
|
||||
// 01110 - INC16
|
||||
// 01111 - DEC16
|
||||
// 10000 - ADD16LO
|
||||
// 10001 - ADD16HI
|
||||
// 10010 -
|
||||
// 10011 -
|
||||
// 10100 - CCF, pass D0
|
||||
// 10101 - SCF, pass D0
|
||||
// 10110 -
|
||||
// 10111 -
|
||||
// 11000 - RLCA D0
|
||||
// 11001 - RRCA D0
|
||||
// 11010 - RLA D0
|
||||
// 11011 - RRA D0
|
||||
// 11100 - {ROT, BIT, SET, RES} D0,EXOP
|
||||
// RLC D0 C <-- D0 <-- D0[7]
|
||||
// RRC D0 D0[0] --> D0 --> C
|
||||
// RL D0 C <-- D0 <-- C
|
||||
// RR D0 C --> D0 --> C
|
||||
// SLA D0 C <-- D0 <-- 0
|
||||
// SRA D0 D0[7] --> D0 --> C
|
||||
// SLL D0 C <-- D0 <-- 1
|
||||
// SRL D0 0 --> D0 --> C
|
||||
// 11101 - IN, pass D1
|
||||
// 11110 - FLAGS <- D0
|
||||
// 11111 - NEG D1
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module ALU8(
|
||||
input [7:0] D0,
|
||||
input [7:0] D1,
|
||||
input [7:0] FIN,
|
||||
output reg[7:0] FOUT,
|
||||
output reg [15:0] ALU8DOUT,
|
||||
input [4:0] OP,
|
||||
input [5:0] EXOP, // EXOP[5:4] = 2'b11 for CPI/D/R
|
||||
input LDIFLAGS, // zero HF and NF on inc/dec16
|
||||
input DSTHI // destination lo
|
||||
);
|
||||
|
||||
wire [7:0] daaadjust;
|
||||
wire cdaa, hdaa;
|
||||
daa daa_adjust(.flags(FIN), .val(D0), .adjust(daaadjust), .cdaa(cdaa), .hdaa(hdaa));
|
||||
|
||||
wire parity = ~^ALU8DOUT[15:8];
|
||||
wire zero = ALU8DOUT[15:8] == 0;
|
||||
reg csin, cin;
|
||||
wire [7:0]d0mux = OP[4:1] == 4'b1111 ? 0 : D0;
|
||||
reg [7:0]_d1mux;
|
||||
wire [7:0]d1mux = OP[1] ? ~_d1mux : _d1mux;
|
||||
wire [8:0]sum;
|
||||
wire hf;
|
||||
assign {hf, sum[3:0]} = d0mux[3:0] + d1mux[3:0] + cin;
|
||||
assign sum[8:4] = d0mux[7:4] + d1mux[7:4] + hf;
|
||||
wire overflow = (d0mux[7] & d1mux[7] & !sum[7]) | (!d0mux[7] & !d1mux[7] & sum[7]);
|
||||
reg [7:0]dbit;
|
||||
|
||||
always @* begin
|
||||
ALU8DOUT = 16'hxxxx;
|
||||
FOUT = 8'hxx;
|
||||
case({OP[4:2]})
|
||||
0,1,4,7: _d1mux = D1;
|
||||
2: _d1mux = 1;
|
||||
3: _d1mux = daaadjust; // DAA
|
||||
6,5: _d1mux = 8'hxx;
|
||||
endcase
|
||||
case({OP[2:0], FIN[0]})
|
||||
0,1,2,7,8,9,10,11,12,13: cin = 0;
|
||||
3,4,5,6,14,15: cin = 1;
|
||||
endcase
|
||||
case(EXOP[3:0])
|
||||
0: dbit = 8'b11111110;
|
||||
1: dbit = 8'b11111101;
|
||||
2: dbit = 8'b11111011;
|
||||
3: dbit = 8'b11110111;
|
||||
4: dbit = 8'b11101111;
|
||||
5: dbit = 8'b11011111;
|
||||
6: dbit = 8'b10111111;
|
||||
7: dbit = 8'b01111111;
|
||||
8: dbit = 8'b00000001;
|
||||
9: dbit = 8'b00000010;
|
||||
10: dbit = 8'b00000100;
|
||||
11: dbit = 8'b00001000;
|
||||
12: dbit = 8'b00010000;
|
||||
13: dbit = 8'b00100000;
|
||||
14: dbit = 8'b01000000;
|
||||
15: dbit = 8'b10000000;
|
||||
endcase
|
||||
case(OP[3] ? EXOP[2:0] : OP[2:0])
|
||||
0,5: csin = D0[7];
|
||||
1: csin = D0[0];
|
||||
2,3: csin = FIN[0];
|
||||
4,7: csin = 0;
|
||||
6: csin = 1;
|
||||
endcase
|
||||
case(OP[4:0])
|
||||
0,1,2,3,8,10: begin // ADD, ADC, SUB, SBC, INC, DEC
|
||||
ALU8DOUT[15:8] = sum[7:0];
|
||||
ALU8DOUT[7:0] = sum[7:0];
|
||||
FOUT[0] = OP[3] ? FIN[0] : (sum[8] ^ OP[1]); // inc/dec
|
||||
FOUT[1] = OP[1];
|
||||
FOUT[2] = overflow;
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = hf ^ OP[1];
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = zero & (FIN[6] | ~EXOP[5] | ~DSTHI | OP[3]); //(EXOP[5] & DSTHI) ? (zero & FIN[6]) : zero; // adc16/sbc16
|
||||
FOUT[7] = ALU8DOUT[15];
|
||||
end
|
||||
16,17: begin // ADD16LO, ADD16HI
|
||||
ALU8DOUT[15:8] = sum[7:0];
|
||||
ALU8DOUT[7:0] = sum[7:0];
|
||||
FOUT[0] = sum[8];
|
||||
FOUT[1] = OP[1];
|
||||
FOUT[2] = FIN[2];
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = hf ^ OP[1];
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = FIN[6];
|
||||
FOUT[7] = FIN[7];
|
||||
end
|
||||
7: begin // CP
|
||||
ALU8DOUT[15:8] = sum[7:0];
|
||||
FOUT[0] = EXOP[5] ? FIN[0] : !sum[8]; // CPI/D/R
|
||||
FOUT[1] = OP[1];
|
||||
FOUT[2] = overflow;
|
||||
FOUT[3] = D1[3];
|
||||
FOUT[4] = !hf;
|
||||
FOUT[5] = D1[5];
|
||||
FOUT[6] = zero;
|
||||
FOUT[7] = ALU8DOUT[15];
|
||||
end
|
||||
31: begin // NEG
|
||||
ALU8DOUT[15:8] = sum[7:0];
|
||||
FOUT[0] = !sum[8];
|
||||
FOUT[1] = OP[1];
|
||||
FOUT[2] = overflow;
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = !hf;
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = zero;
|
||||
FOUT[7] = ALU8DOUT[15];
|
||||
end
|
||||
4: begin // AND
|
||||
ALU8DOUT[15:8] = D0 & D1;
|
||||
FOUT[0] = 0;
|
||||
FOUT[1] = 0;
|
||||
FOUT[2] = parity;
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = 1;
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = zero;
|
||||
FOUT[7] = ALU8DOUT[15];
|
||||
end
|
||||
5,6: begin //XOR, OR
|
||||
ALU8DOUT[15:8] = OP[0] ? (D0 ^ D1) : (D0 | D1);
|
||||
FOUT[0] = 0;
|
||||
FOUT[1] = 0;
|
||||
FOUT[2] = parity;
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = 0;
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = zero;
|
||||
FOUT[7] = ALU8DOUT[15];
|
||||
end
|
||||
9: begin // CPL
|
||||
ALU8DOUT[15:8] = ~D0;
|
||||
FOUT[0] = FIN[0];
|
||||
FOUT[1] = 1;
|
||||
FOUT[2] = FIN[2];
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = 1;
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[7:6] = FIN[7:6];
|
||||
end
|
||||
11,12: begin // RLD, RRD
|
||||
if(OP[0]) ALU8DOUT = {D0[7:4], D1[3:0], D0[3:0], D1[7:4]};
|
||||
else ALU8DOUT = {D0[7:4], D1[7:0], D0[3:0]};
|
||||
FOUT[0] = FIN[0];
|
||||
FOUT[1] = 0;
|
||||
FOUT[2] = parity;
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = 0;
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = zero;
|
||||
FOUT[7] = ALU8DOUT[15];
|
||||
end
|
||||
13: begin // DAA
|
||||
ALU8DOUT[15:8] = sum[7:0];
|
||||
FOUT[0] = cdaa;
|
||||
FOUT[1] = FIN[1];
|
||||
FOUT[2] = parity;
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = hdaa;
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = zero;
|
||||
FOUT[7] = ALU8DOUT[15];
|
||||
end
|
||||
14,15: begin // inc/dec 16
|
||||
ALU8DOUT = {D0, D1} + (OP[0] ? 16'hffff : 16'h0001);
|
||||
FOUT[0] = FIN[0];
|
||||
FOUT[1] = LDIFLAGS ? 1'b0 : FIN[1];
|
||||
FOUT[2] = ALU8DOUT != 0;
|
||||
FOUT[3] = FIN[3];
|
||||
FOUT[4] = LDIFLAGS ? 1'b0 : FIN[4];
|
||||
FOUT[5] = FIN[5];
|
||||
FOUT[6] = FIN[6];
|
||||
FOUT[7] = FIN[7];
|
||||
end
|
||||
20,21: begin // CCF, SCF
|
||||
ALU8DOUT[15:8] = D0;
|
||||
FOUT[0] = OP[0] ? 1'b1 : !FIN[0];
|
||||
FOUT[1] = 1'b0;
|
||||
FOUT[2] = FIN[2];
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = OP[0] ? 1'b0 : FIN[0];
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = FIN[6];
|
||||
FOUT[7] = FIN[7];
|
||||
end
|
||||
24,25,26,27, 28: begin // ROT, BIT, RES, SET
|
||||
case({OP[2], EXOP[4:3]})
|
||||
0,1,2,3,4: // rot - shift
|
||||
if(OP[2] ? EXOP[0] : OP[0]){ALU8DOUT[15:8], FOUT[0]} = {csin, D0}; // right
|
||||
else {FOUT[0], ALU8DOUT[15:8]} = {D0, csin}; // left
|
||||
5,6: begin // BIT, RES
|
||||
FOUT[0] = FIN[0];
|
||||
ALU8DOUT[15:8] = D0 & dbit;
|
||||
end
|
||||
7: begin // SET
|
||||
FOUT[0] = FIN[0];
|
||||
ALU8DOUT[15:8] = D0 | dbit;
|
||||
end
|
||||
endcase
|
||||
ALU8DOUT[7:0] = ALU8DOUT[15:8];
|
||||
FOUT[1] = 0;
|
||||
FOUT[2] = OP[2] ? (EXOP[3] ? zero : parity) : FIN[2];
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = OP[2] & EXOP[3];
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = OP[2] ? zero : FIN[6];
|
||||
FOUT[7] = OP[2] ? ALU8DOUT[15] : FIN[7];
|
||||
end
|
||||
29: begin // IN, pass D1
|
||||
ALU8DOUT = {D1, D1};
|
||||
FOUT[0] = FIN[0];
|
||||
FOUT[1] = 0;
|
||||
FOUT[2] = parity;
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = 0;
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = zero;
|
||||
FOUT[7] = ALU8DOUT[15];
|
||||
end
|
||||
30: FOUT = D0; // FLAGS <- D0
|
||||
default:;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
||||
module daa (
|
||||
input [7:0]flags,
|
||||
input [7:0]val,
|
||||
output wire [7:0]adjust,
|
||||
output reg cdaa,
|
||||
output reg hdaa
|
||||
);
|
||||
|
||||
wire h08 = val[7:4] < 9;
|
||||
wire h09 = val[7:4] < 10;
|
||||
wire l05 = val[3:0] < 6;
|
||||
wire l09 = val[3:0] < 10;
|
||||
reg [1:0]aa;
|
||||
assign adjust = ({1'b0, aa[1], aa[1], 2'b0, aa[0], aa[0], 1'b0} ^ {8{flags[1]}}) + flags[1];
|
||||
|
||||
always @* begin
|
||||
case({flags[0], h08, h09, flags[4], l09})
|
||||
5'b00101, 5'b01101: aa = 0;
|
||||
5'b00111, 5'b01111, 5'b01000, 5'b01010, 5'b01100, 5'b01110: aa = 1;
|
||||
5'b00001, 5'b01001, 5'b10001, 5'b10101, 5'b11001, 5'b11101: aa = 2;
|
||||
default: aa = 3;
|
||||
endcase
|
||||
case({flags[0], h08, h09, l09})
|
||||
4'b0011, 4'b0111, 4'b0100, 4'b0110: cdaa = 0;
|
||||
default: cdaa = 1;
|
||||
endcase
|
||||
case({flags[1], flags[4], l05, l09})
|
||||
4'b0000, 4'b0010, 4'b0100, 4'b0110, 4'b1110, 4'b1111: hdaa = 1;
|
||||
default: hdaa = 0;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
module ALU16(
|
||||
input [15:0] D0,
|
||||
input [7:0] D1,
|
||||
output wire[15:0] DOUT,
|
||||
input [2:0]OP // 0-NOP, 1-INC, 2-INC2, 3-ADD, 4-NOP, 5-DEC, 6-DEC2
|
||||
);
|
||||
|
||||
reg [15:0] mux;
|
||||
always @*
|
||||
case(OP)
|
||||
0: mux = 0; // post inc
|
||||
1: mux = 1; // post inc
|
||||
2: mux = 2; // post inc
|
||||
3: mux = {D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7:0]}; // post inc
|
||||
4: mux = 0; // no post inc
|
||||
5: mux = 16'hffff; // no post inc
|
||||
6: mux = 16'hfffe; // no post inc
|
||||
default: mux = 16'hxxxx;
|
||||
endcase
|
||||
|
||||
assign DOUT = D0 + mux;
|
||||
endmodule
|
||||
1499
Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80CPU.v
Normal file
1499
Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80CPU.v
Normal file
File diff suppressed because it is too large
Load Diff
199
Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80Reg.v
Normal file
199
Computer_MiST/Laser310_MiST/rtl/NextZ80/NextZ80Reg.v
Normal file
@@ -0,0 +1,199 @@
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// This file is part of the NextZ80 project
|
||||
// http://www.opencores.org/cores/nextz80/
|
||||
//
|
||||
// Filename: NextZ80Regs.v
|
||||
// Description: Implementation of Z80 compatible CPU - registers
|
||||
// Version 1.0
|
||||
// Creation date: 28Jan2011 - 18Mar2011
|
||||
//
|
||||
// Author: Nicolae Dumitrache
|
||||
// e-mail: ndumitrache@opencores.org
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2011 Nicolae Dumitrache
|
||||
//
|
||||
// This source file may be used and distributed without
|
||||
// restriction provided that this copyright statement is not
|
||||
// removed from the file and that any derivative work contains
|
||||
// the original copyright notice and the associated disclaimer.
|
||||
//
|
||||
// This source file is free software; you can redistribute it
|
||||
// and/or modify it under the terms of the GNU Lesser General
|
||||
// Public License as published by the Free Software Foundation;
|
||||
// either version 2.1 of the License, or (at your option) any
|
||||
// later version.
|
||||
//
|
||||
// This source is distributed in the hope that it will be
|
||||
// useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
// PURPOSE. See the GNU Lesser General Public License for more
|
||||
// details.
|
||||
//
|
||||
// You should have received a copy of the GNU Lesser General
|
||||
// Public License along with this source; if not, download it
|
||||
// from http://www.opencores.org/lgpl.shtml
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module Z80Reg(
|
||||
input wire [7:0]rstatus, // 0=af-af', 1=exx, 2=hl-de, 3=hl'-de',4=hl-ixy, 5=ix-iy, 6=IFF1, 7=IFF2
|
||||
input wire M1,
|
||||
input wire [5:0]WE, // 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo
|
||||
input wire CLK,
|
||||
input wire [15:0]ALU8OUT, // CPU data out bus (output of alu8)
|
||||
input wire [7:0]DI, // CPU data in bus
|
||||
output reg [7:0]DO, // CPU data out bus
|
||||
input wire [15:0]ADDR, // CPU addr bus
|
||||
input wire [7:0]CONST,
|
||||
output reg [7:0]ALU80,
|
||||
output reg [7:0]ALU81,
|
||||
output reg [15:0]ALU160,
|
||||
output wire[7:0]ALU161,
|
||||
input wire [7:0]ALU8FLAGS,
|
||||
output wire [7:0]FLAGS,
|
||||
|
||||
input wire [1:0]DO_SEL, // select DO betwen ALU8OUT lo and th register
|
||||
input wire ALU160_sel, // 0=REG_RSEL, 1=PC
|
||||
input wire [3:0]REG_WSEL, // rdow: [3:1] 0=BC, 1=DE, 2=HL, 3=A-TL, 4=I-x ----- [0] = 0HI,1LO
|
||||
input wire [3:0]REG_RSEL, // mux_rdor: [3:1] 0=BC, 1=DE, 2=HL, 3=A-TL, 4=I-R, 5=SP, 7=tmpSP ----- [0] = 0HI, 1LO
|
||||
input wire DINW_SEL, // select RAM write data between (0)ALU8OUT, and 1(DI)
|
||||
input wire XMASK, // 0 if REG_WSEL should not use IX, IY, even if rstatus[4] == 1
|
||||
input wire [2:0]ALU16OP, // ALU16OP
|
||||
input wire WAIT // wait
|
||||
);
|
||||
|
||||
// latch registers
|
||||
reg [15:0]pc=0; // program counter
|
||||
reg [15:0]sp; // stack pointer
|
||||
reg [7:0]r; // refresh
|
||||
reg [15:0]flg = 0;
|
||||
reg [7:0]th; // temp high
|
||||
|
||||
// internal wires
|
||||
wire [15:0]rdor; // R out from RAM
|
||||
wire [15:0]rdow; // W out from RAM
|
||||
wire [3:0]SELW; // RAM W port sel
|
||||
wire [3:0]SELR; // RAM R port sel
|
||||
reg [15:0]DIN; // RAM W in data
|
||||
reg [15:0]mux_rdor; // (3)A reversed mixed with TL, (4)I mixed with R (5)SP
|
||||
|
||||
//------------------------------------ RAM block registers ----------------------------------
|
||||
// 0:BC, 1:DE, 2:HL, 3:A-x, 4:I-x, 5:IX, 6:IY, 7:x-x, 8:BC', 9:DE', 10:HL', 11:A'-x, 12: tmpSP, 13:zero
|
||||
RAM16X8D_regs regs_lo (
|
||||
.DPO(rdor[7:0]), // Read-only data output
|
||||
.SPO(rdow[7:0]), // R/W data output
|
||||
.A(SELW), // R/W address
|
||||
.D(DIN[7:0]), // Write data input
|
||||
.DPRA(SELR), // Read-only address
|
||||
.WCLK(CLK), // Write clock input
|
||||
.WE(WE[0] & !WAIT) // Write enable input
|
||||
);
|
||||
|
||||
RAM16X8D_regs regs_hi (
|
||||
.DPO(rdor[15:8]), // Read-only data output
|
||||
.SPO(rdow[15:8]), // R/W data output
|
||||
.A(SELW), // R/W address
|
||||
.D(DIN[15:8]), // Write data input
|
||||
.DPRA(SELR), // Read-only address
|
||||
.WCLK(CLK), // Write clock input
|
||||
.WE(WE[1] & !WAIT) // Write enable input
|
||||
);
|
||||
|
||||
wire [15:0]ADDR1 = ADDR + !ALU16OP[2]; // address post increment
|
||||
wire [7:0]flgmux = {ALU8FLAGS[7:3], SELR[3:0] == 4'b0100 ? rstatus[7] : ALU8FLAGS[2], ALU8FLAGS[1:0]}; // LD A, I/R IFF2 flag on parity
|
||||
always @(posedge CLK)
|
||||
if(!WAIT) begin
|
||||
if(WE[2]) th <= DI;
|
||||
if(WE[3]) sp <= ADDR1;
|
||||
if(WE[4]) pc <= ADDR1;
|
||||
if({REG_WSEL, WE[0]} == 5'b10011) r <= ALU8OUT[7:0];
|
||||
else if(M1) r[6:0] <= r[6:0] + 1;
|
||||
if(WE[5])
|
||||
if(rstatus[0]) flg[15:8] <= flgmux;
|
||||
else flg[7:0] <= flgmux;
|
||||
end
|
||||
|
||||
assign ALU161 = th;
|
||||
assign FLAGS = rstatus[0] ? flg[15:8] : flg[7:0];
|
||||
|
||||
always @* begin
|
||||
DIN = DINW_SEL ? {DI, DI} : ALU8OUT;
|
||||
ALU80 = REG_WSEL[0] ? rdow[7:0] : rdow[15:8];
|
||||
ALU81 = REG_RSEL[0] ? mux_rdor[7:0] : mux_rdor[15:8];
|
||||
ALU160 = ALU160_sel ? pc : mux_rdor;
|
||||
|
||||
case({REG_WSEL[3], DO_SEL})
|
||||
0: DO = ALU80;
|
||||
1: DO = th;
|
||||
2: DO = FLAGS;
|
||||
3: DO = ALU8OUT[7:0];
|
||||
4: DO = pc[15:8];
|
||||
5: DO = pc[7:0];
|
||||
6: DO = sp[15:8];
|
||||
7: DO = sp[7:0];
|
||||
endcase
|
||||
case({ALU16OP == 4, REG_RSEL[3:0]})
|
||||
5'b01001, 5'b11001: mux_rdor = {rdor[15:8], r};
|
||||
5'b01010, 5'b01011: mux_rdor = sp;
|
||||
5'b01100, 5'b01101, 5'b11100, 5'b11101: mux_rdor = {8'b0, CONST};
|
||||
default: mux_rdor = rdor;
|
||||
endcase
|
||||
end
|
||||
|
||||
RegSelect WSelectW(.SEL(REG_WSEL[3:1]), .RAMSEL(SELW), .rstatus({rstatus[5], rstatus[4] & XMASK, rstatus[3:0]}));
|
||||
RegSelect WSelectR(.SEL(REG_RSEL[3:1]), .RAMSEL(SELR), .rstatus(rstatus[5:0]));
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module RegSelect(
|
||||
input [2:0]SEL,
|
||||
output reg [3:0]RAMSEL,
|
||||
input [5:0]rstatus // 0=af-af', 1=exx, 2=hl-de, 3=hl'-de',4=hl-ixy, 5=ix-iy
|
||||
);
|
||||
|
||||
always @* begin
|
||||
RAMSEL = 4'bxxxx;
|
||||
case(SEL)
|
||||
0: RAMSEL = {rstatus[1], 3'b000}; // BC
|
||||
1: //DE
|
||||
if(rstatus[{1'b1, rstatus[1]}]) RAMSEL = {rstatus[1], 3'b010}; // HL
|
||||
else RAMSEL = {rstatus[1], 3'b001}; // DE
|
||||
2: // HL
|
||||
case({rstatus[5:4], rstatus[{1'b1, rstatus[1]}]})
|
||||
0,4: RAMSEL = {rstatus[1], 3'b010}; // HL
|
||||
1,5: RAMSEL = {rstatus[1], 3'b001}; // DE
|
||||
2,3: RAMSEL = 4'b0101; // IX
|
||||
6,7: RAMSEL = 4'b0110; // IY
|
||||
endcase
|
||||
3: RAMSEL = {rstatus[0], 3'b011}; // A-TL
|
||||
4: RAMSEL = 4; // I-R
|
||||
5: RAMSEL = 12; // tmp SP
|
||||
6: RAMSEL = 13; // zero
|
||||
7: RAMSEL = 7; // temp reg for BIT/SET/RES
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
||||
module RAM16X8D_regs(
|
||||
output [7:0]DPO, // Read-only data output
|
||||
output [7:0]SPO, // R/W data output
|
||||
input [3:0]A, // R/W address
|
||||
input [7:0]D, // Write data input
|
||||
input [3:0]DPRA, // Read-only address
|
||||
input WCLK, // Write clock
|
||||
input WE // Write enable
|
||||
);
|
||||
|
||||
reg [7:0]data[15:0];
|
||||
assign DPO = data[DPRA];
|
||||
assign SPO = data[A];
|
||||
|
||||
always @(posedge WCLK)
|
||||
if(WE) data[A] <= D;
|
||||
|
||||
endmodule
|
||||
296
Computer_MiST/Laser310_MiST/rtl/PIXEL_DISPLAY.v
Normal file
296
Computer_MiST/Laser310_MiST/rtl/PIXEL_DISPLAY.v
Normal file
@@ -0,0 +1,296 @@
|
||||
module PIXEL_DISPLAY (
|
||||
pixel_clock,
|
||||
reset,
|
||||
|
||||
show_border,
|
||||
|
||||
// mode
|
||||
ag,
|
||||
gm,
|
||||
css,
|
||||
|
||||
// text
|
||||
char_column,
|
||||
char_line,
|
||||
subchar_line,
|
||||
subchar_pixel,
|
||||
|
||||
// graph
|
||||
graph_pixel,
|
||||
graph_line_2x,
|
||||
graph_line_3x,
|
||||
|
||||
// vram
|
||||
vram_rd_enable,
|
||||
vram_addr,
|
||||
vram_data,
|
||||
|
||||
// vga
|
||||
vga_red,
|
||||
vga_green,
|
||||
vga_blue
|
||||
);
|
||||
|
||||
input pixel_clock;
|
||||
input reset;
|
||||
|
||||
input show_border;
|
||||
|
||||
// mode
|
||||
input ag;
|
||||
input [2:0] gm;
|
||||
input css;
|
||||
|
||||
// text
|
||||
input [6:0] char_column; // character number on the current line
|
||||
input [6:0] char_line; // line number on the screen
|
||||
input [4:0] subchar_line; // the line number within a character block 0-8
|
||||
input [3:0] subchar_pixel; // the pixel number within a character block 0-8
|
||||
|
||||
// graph
|
||||
input [8:0] graph_pixel; // pixel number on the current line
|
||||
input [9:0] graph_line_2x; // line number on the screen
|
||||
input [9:0] graph_line_3x; // line number on the screen
|
||||
|
||||
output vram_rd_enable;
|
||||
output reg [12:0] vram_addr;
|
||||
input [7:0] vram_data;
|
||||
|
||||
output [7:0] vga_red;
|
||||
output [7:0] vga_green;
|
||||
output [7:0] vga_blue;
|
||||
|
||||
|
||||
//// Label Definitions ////
|
||||
|
||||
// Note: all labels must match their defined length--shorter labels will be padded with solid blocks,
|
||||
// and longer labels will be truncated
|
||||
|
||||
// 48 character label for the example text
|
||||
|
||||
wire pixel_on; // high => output foreground color, low => output background color
|
||||
|
||||
|
||||
// 8p 代表每个点占用VGA水平 8 pixel
|
||||
// 2bit 代表每个点取2位值
|
||||
|
||||
wire [1:0] pixel_8p_2bit; // high => output foreground color, low => output background color
|
||||
wire [1:0] pixel_4p_2bit; // high => output foreground color, low => output background color
|
||||
wire pixel_4p_1bit; // high => output foreground color, low => output background color
|
||||
wire pixel_2p_1bit; // high => output foreground color, low => output background color
|
||||
|
||||
reg [7:0] latched_vram_data; // the data that will be written to character memory at the clock rise
|
||||
|
||||
// 锁存数据用于选择调色板
|
||||
reg [7:0] latched_palette_data;
|
||||
|
||||
assign vram_rd_enable = pixel_clock;
|
||||
|
||||
reg [23:0] latched_vga_rgb;
|
||||
wire [23:0] vga_rgb;
|
||||
|
||||
// write the appropriate character data to memory
|
||||
|
||||
always @ (posedge pixel_clock) begin
|
||||
if(ag==1'b0)
|
||||
begin
|
||||
if(subchar_pixel==4'b0001)
|
||||
vram_addr <= {4'b0,char_line[3:0], char_column[4:0]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(subchar_pixel==4'b0011)
|
||||
latched_vram_data <= vram_data;
|
||||
if(graph_pixel[3:0]==4'b0110)
|
||||
latched_palette_data <= latched_vram_data;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case(gm)
|
||||
3'b000:
|
||||
begin
|
||||
// 64 x 64 x 4 gm: 000
|
||||
if(graph_pixel[4:0]==5'b00001)
|
||||
vram_addr <= {3'b0, graph_line_3x[9:4], graph_pixel[8:5]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(graph_pixel[4:0]==5'b00011)
|
||||
latched_vram_data <= vram_data;
|
||||
end
|
||||
3'b001:
|
||||
begin
|
||||
// 128 x 64 x 2 gm: 001
|
||||
if(graph_pixel[4:0]==5'b00001)
|
||||
vram_addr <= {3'b0, graph_line_3x[9:4], graph_pixel[8:5]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(graph_pixel[4:0]==5'b00011)
|
||||
latched_vram_data <= vram_data;
|
||||
end
|
||||
3'b011:
|
||||
begin
|
||||
// 128 x 96 x 2 gm: 011
|
||||
if(graph_pixel[4:0]==5'b00001)
|
||||
vram_addr <= {2'b0, graph_line_2x[9:3], graph_pixel[8:5]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(graph_pixel[4:0]==5'b00011)
|
||||
latched_vram_data <= vram_data;
|
||||
end
|
||||
3'b100:
|
||||
begin
|
||||
// 128 x 96 x 4 gm: 100
|
||||
if(graph_pixel[3:0]==4'b0001)
|
||||
vram_addr <= {1'b0, graph_line_2x[8:1], graph_pixel[8:4]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(graph_pixel[3:0]==4'b0011)
|
||||
latched_vram_data <= vram_data;
|
||||
end
|
||||
3'b101:
|
||||
begin
|
||||
// 128 x 192 x 2 gm: 101
|
||||
if(graph_pixel[4:0]==5'b00001)
|
||||
vram_addr <= {1'b0, graph_line_2x[9:1], graph_pixel[8:5]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(graph_pixel[4:0]==5'b00011)
|
||||
latched_vram_data <= vram_data;
|
||||
end
|
||||
3'b110:
|
||||
begin
|
||||
// 128 x 192 x 4 gm: 110
|
||||
if(graph_pixel[3:0]==4'b0001)
|
||||
vram_addr <= {graph_line_2x[9:1], graph_pixel[8:4]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(graph_pixel[3:0]==4'b0011)
|
||||
latched_vram_data <= vram_data;
|
||||
end
|
||||
3'b111:
|
||||
begin
|
||||
// 256 x 192 x 2 gm: 111
|
||||
if(graph_pixel[3:0]==4'b0001)
|
||||
vram_addr <= {graph_line_2x[9:1], graph_pixel[8:4]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(graph_pixel[3:0]==4'b0011)
|
||||
latched_vram_data <= vram_data;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
// 128 x 64 x 4 gm: 010
|
||||
if(graph_pixel[3:0]==4'b0001)
|
||||
vram_addr <= {2'b0,graph_line_3x[9:3], graph_pixel[8:4]};
|
||||
//vram_addr <= {2'b0,graph_line_3x[8:3], graph_pixel[6:2]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(graph_pixel[3:0]==4'b0011)
|
||||
latched_vram_data <= vram_data;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
latched_vga_rgb <= vga_rgb;
|
||||
end
|
||||
|
||||
// palette
|
||||
/*
|
||||
位\色 绿 黄 蓝 红 浅黄 浅蓝 紫 橙
|
||||
D6 0 0 0 0 1 1 1 1
|
||||
D5 0 0 1 1 0 0 1 1
|
||||
D4 0 1 0 1 0 1 0 1
|
||||
|
||||
0x07 0xff 0x00 // GREEN
|
||||
0xff 0xff 0x00 // YELLOW
|
||||
0x3b 0x08 0xff // BLUE
|
||||
0xcc 0x00 0x3b // RED
|
||||
0xff 0xff 0xff // BUFF
|
||||
0x07 0xe3 0x99 // CYAN
|
||||
0xff 0x1c 0xff // MAGENTA
|
||||
0xff 0x81 0x00 // ORANGE
|
||||
|
||||
0x00 0x00 0x00 // BLACK
|
||||
0x07 0xff 0x00 // GREEN
|
||||
0x3b 0x08 0xff // BLUE
|
||||
0xff 0xff 0xff // BUFF
|
||||
|
||||
*/
|
||||
|
||||
wire [2:0] palette_bit_graph;
|
||||
|
||||
wire [23:0] palette_rgb_border = (~ag)?24'h000000: // 字符模式背景
|
||||
(css)?24'hffffff:24'h07ff00; // 图形模式背景
|
||||
|
||||
wire [23:0] palette_rgb_pixel = 24'h000000;
|
||||
wire [23:0] palette_rgb_background = 24'h07ff00;
|
||||
|
||||
// 64 x 64 x 4 gm: 000
|
||||
// 128 x 64 x 2 gm: 001
|
||||
// 128 x 64 x 4 gm: 010
|
||||
// 128 x 96 x 2 gm: 011
|
||||
// 128 x 96 x 4 gm: 100
|
||||
// 128 x 192 x 2 gm: 101
|
||||
// 128 x 192 x 4 gm: 110
|
||||
// 256 x 192 x 2 gm: 111
|
||||
|
||||
//assign palette_bit_graph = (ag)? {css, pixel_4p_2bit} : latched_palette_data[6:4];
|
||||
|
||||
assign palette_bit_graph = (~ag) ? latched_palette_data[6:4] :
|
||||
(gm==3'b000) ? {css, pixel_8p_2bit } :
|
||||
(gm==3'b001) ? {css, pixel_4p_1bit, pixel_4p_1bit } :
|
||||
(gm==3'b010) ? {css, pixel_4p_2bit } :
|
||||
(gm==3'b011) ? {css, pixel_4p_1bit, pixel_4p_1bit } :
|
||||
(gm==3'b100) ? {css, pixel_4p_2bit } :
|
||||
(gm==3'b101) ? {css, pixel_4p_1bit, pixel_4p_1bit } :
|
||||
(gm==3'b110) ? {css, pixel_4p_2bit } :
|
||||
{css, pixel_2p_1bit, pixel_2p_1bit } ;
|
||||
|
||||
wire [23:0] palette_rgb_graph = (palette_bit_graph==3'b000) ? 24'h07ff00 : // GREEN
|
||||
(palette_bit_graph==3'b001) ? 24'hffff00 : // YELLOW
|
||||
(palette_bit_graph==3'b010) ? 24'h3b08ff : // BLUE
|
||||
(palette_bit_graph==3'b011) ? 24'hcc003b : // RED
|
||||
(palette_bit_graph==3'b100) ? 24'hffffff : // BUFF
|
||||
(palette_bit_graph==3'b101) ? 24'h07e399 : // CYAN
|
||||
(palette_bit_graph==3'b110) ? 24'hff1cff : // MAGENTA
|
||||
24'hff8100 ; // ORANGE
|
||||
|
||||
/*
|
||||
24'h000000 // BLACK
|
||||
24'h07ff00 // GREEN
|
||||
24'h3b08ff // BLUE
|
||||
24'hffffff // BUFF
|
||||
*/
|
||||
|
||||
|
||||
// use the result of the character generator module to choose between the foreground and background color
|
||||
|
||||
assign vga_rgb = (show_border) ? palette_rgb_border :
|
||||
(ag) ? palette_rgb_graph :
|
||||
(~pixel_on) ? palette_rgb_pixel :
|
||||
(latched_palette_data[7]) ? palette_rgb_graph : palette_rgb_background;
|
||||
|
||||
assign vga_red = latched_vga_rgb[23:16];
|
||||
assign vga_green = latched_vga_rgb[15:8];
|
||||
assign vga_blue = latched_vga_rgb[7:0];
|
||||
|
||||
|
||||
// the character generator block includes the character RAM
|
||||
// and the character generator ROM
|
||||
CHAR_GEN CHAR_GEN
|
||||
(
|
||||
.reset(reset), // reset signal
|
||||
|
||||
.char_code(latched_vram_data),
|
||||
.subchar_line(subchar_line), // current line of pixels within current character
|
||||
.subchar_pixel(subchar_pixel), // current column of pixels withing current character
|
||||
|
||||
.pixel_clock(pixel_clock), // read clock
|
||||
.pixel_on(pixel_on) // read data
|
||||
);
|
||||
|
||||
PIXEL_GEN PIXEL_GEN
|
||||
(
|
||||
.reset(reset), // reset signal
|
||||
|
||||
.pixel_code(latched_vram_data),
|
||||
.graph_pixel(graph_pixel), // current column of pixels withing current character
|
||||
|
||||
.pixel_clock(pixel_clock), // read clock
|
||||
|
||||
.pixel_8p_2bit(pixel_8p_2bit), // 64x64x4
|
||||
.pixel_4p_2bit(pixel_4p_2bit), // 128x64x4 128x96x4 128x192x4
|
||||
.pixel_4p_1bit(pixel_4p_1bit), // 128x64x2 128x96x2 128x192x2
|
||||
.pixel_2p_1bit(pixel_2p_1bit) // 256x192x2
|
||||
);
|
||||
|
||||
endmodule //CHAR_DISPLAY
|
||||
129
Computer_MiST/Laser310_MiST/rtl/PIXEL_GEN.v
Normal file
129
Computer_MiST/Laser310_MiST/rtl/PIXEL_GEN.v
Normal file
@@ -0,0 +1,129 @@
|
||||
module PIXEL_GEN(
|
||||
// control
|
||||
reset,
|
||||
|
||||
pixel_code,
|
||||
graph_pixel,
|
||||
|
||||
pixel_clock,
|
||||
|
||||
pixel_8p_2bit, // 64x64x4
|
||||
pixel_4p_2bit, // 128x64x4 128x96x4 128x192x4
|
||||
pixel_4p_1bit, // 128x64x2 128x96x2 128x192x2
|
||||
pixel_2p_1bit // 256x192x2
|
||||
);
|
||||
|
||||
|
||||
input reset;
|
||||
|
||||
input [7:0] pixel_code;
|
||||
input [8:0] graph_pixel; // pixel number on the current line
|
||||
|
||||
input pixel_clock;
|
||||
|
||||
output reg [1:0] pixel_8p_2bit;
|
||||
output reg [1:0] pixel_4p_2bit;
|
||||
output reg pixel_4p_1bit;
|
||||
output reg pixel_2p_1bit;
|
||||
|
||||
reg [7:0] latched_8p_2bit_data;
|
||||
reg [7:0] latched_4p_2bit_data;
|
||||
reg [7:0] latched_4p_1bit_data;
|
||||
reg [7:0] latched_2p_1bit_data;
|
||||
|
||||
|
||||
// 移位寄存器有四种模式
|
||||
// 每2个点 移 1 位
|
||||
// 每4个点 移 2 位
|
||||
// 每4个点 移 1 位
|
||||
// 每8个点 移 2 位
|
||||
|
||||
|
||||
// serialize the GRAPH MODE data
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
pixel_8p_2bit <= 2'b00;
|
||||
latched_8p_2bit_data <= 8'h00;
|
||||
end
|
||||
else begin
|
||||
case(graph_pixel[4:0])
|
||||
5'b00101:
|
||||
latched_8p_2bit_data[7:0] <= pixel_code;
|
||||
default:
|
||||
if(graph_pixel[3:0]==3'b110)
|
||||
{pixel_8p_2bit,latched_8p_2bit_data[7:2]} <= latched_8p_2bit_data[7:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
// 延时：图形模式 128x64 4色
|
||||
// 1、(001)锁存 vram 地址，2、(010)读取 vram 3、(011)锁存 vram 数据 4、(100)空 5、(101)数据锁存至移位寄存器
|
||||
// 6、(110)移位得到点阵 7、(111)建立调色板，锁存色彩
|
||||
|
||||
// serialize the GRAPH MODE data
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
pixel_4p_2bit <= 2'b00;
|
||||
latched_4p_2bit_data <= 8'h00;
|
||||
end
|
||||
else begin
|
||||
case(graph_pixel[3:0])
|
||||
4'b0101:
|
||||
latched_4p_2bit_data[7:0] <= pixel_code;
|
||||
default:
|
||||
if(graph_pixel[1:0]==2'b10)
|
||||
{pixel_4p_2bit,latched_4p_2bit_data[7:2]} <= latched_4p_2bit_data[7:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
// serialize the GRAPH MODE data
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
pixel_4p_1bit <= 2'b00;
|
||||
latched_4p_1bit_data <= 8'h00;
|
||||
end
|
||||
else begin
|
||||
case(graph_pixel[4:0])
|
||||
5'b00101:
|
||||
latched_4p_1bit_data[7:0] <= pixel_code;
|
||||
default:
|
||||
if(graph_pixel[1:0]==2'b10)
|
||||
{pixel_4p_1bit,latched_4p_1bit_data[7:1]} <= latched_4p_1bit_data[7:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
// 延时：图形模式 256x192 2色
|
||||
// 1、(001)锁存 vram 地址，2、(010)读取 vram 3、(011)锁存 vram 数据 4、(100)空 5、(101)数据锁存至移位寄存器
|
||||
// 6、(110)移位得到点阵 7、(111)建立调色板，锁存色彩
|
||||
|
||||
// serialize the GRAPH MODE data
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
pixel_2p_1bit <= 1'b0;
|
||||
latched_2p_1bit_data <= 8'h00;
|
||||
end
|
||||
else begin
|
||||
case(graph_pixel[3:0])
|
||||
4'b0101:
|
||||
latched_2p_1bit_data[7:0] <= pixel_code;
|
||||
default:
|
||||
if(graph_pixel[0]==1'b0)
|
||||
{pixel_2p_1bit,latched_2p_1bit_data[7:1]} <= latched_2p_1bit_data[7:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endmodule //PIXEL_GEN
|
||||
246
Computer_MiST/Laser310_MiST/rtl/SVGA_DEFINES.v
Normal file
246
Computer_MiST/Laser310_MiST/rtl/SVGA_DEFINES.v
Normal file
@@ -0,0 +1,246 @@
|
||||
/*
|
||||
---------------------------------------------------------------------------------
|
||||
To select a resolution and refresh rate, remove the comments around the desired
|
||||
block in this file. The pixel clock output by the DCM module should approximately
|
||||
equal the rate specified above the timing block that is uncommented.
|
||||
---------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
// DEFINE THE VARIOUS PIPELINE DELAYS
|
||||
|
||||
`define CHARACTER_DECODE_DELAY 4
|
||||
|
||||
|
||||
// 640 X 480 @ 60Hz with a 25.175MHz pixel clock
|
||||
`define H_ACTIVE 640 // pixels
|
||||
`define H_FRONT_PORCH 16 // pixels
|
||||
`define H_SYNCH 96 // pixels
|
||||
`define H_BACK_PORCH 48 // pixels
|
||||
`define H_TOTAL 800 // pixels
|
||||
|
||||
`define V_ACTIVE 480 // lines
|
||||
`define V_FRONT_PORCH 11 // lines
|
||||
`define V_SYNCH 2 // lines
|
||||
`define V_BACK_PORCH 31 // lines
|
||||
`define V_TOTAL 524 // lines
|
||||
|
||||
`define CLK_MULTIPLY 2 // 50 * 2/4 = 25.000 MHz
|
||||
`define CLK_DIVIDE 4
|
||||
|
||||
|
||||
/*
|
||||
// 640 X 480 @ 72Hz with a 31.500MHz pixel clock
|
||||
`define H_ACTIVE 640 // pixels
|
||||
`define H_FRONT_PORCH 24 // pixels
|
||||
`define H_SYNCH 40 // pixels
|
||||
`define H_BACK_PORCH 128 // pixels
|
||||
`define H_TOTAL 832 // pixels
|
||||
|
||||
`define V_ACTIVE 480 // lines
|
||||
`define V_FRONT_PORCH 9 // lines
|
||||
`define V_SYNCH 3 // lines
|
||||
`define V_BACK_PORCH 28 // lines
|
||||
`define V_TOTAL 520 // lines
|
||||
|
||||
`define CLK_MULTIPLY 5 // 50 * 5/8 = 31.250 MHz
|
||||
`define CLK_DIVIDE 8
|
||||
*/
|
||||
|
||||
/*
|
||||
// 640 X 480 @ 75Hz with a 31.500MHz pixel clock
|
||||
`define H_ACTIVE 640 // pixels
|
||||
`define H_FRONT_PORCH 16 // pixels
|
||||
`define H_SYNCH 96 // pixels
|
||||
`define H_BACK_PORCH 48 // pixels
|
||||
`define H_TOTAL 800 // pixels
|
||||
|
||||
`define V_ACTIVE 480 // lines
|
||||
`define V_FRONT_PORCH 11 // lines
|
||||
`define V_SYNCH 2 // lines
|
||||
`define V_BACK_PORCH 32 // lines
|
||||
`define V_TOTAL 525 // lines
|
||||
|
||||
`define CLK_MULTIPLY 5 // 50 * 5/8 = 31.250 MHz
|
||||
`define CLK_DIVIDE 8
|
||||
*/
|
||||
|
||||
/*
|
||||
// 640 X 480 @ 85Hz with a 36.000MHz pixel clock
|
||||
`define H_ACTIVE 640 // pixels
|
||||
`define H_FRONT_PORCH 32 // pixels
|
||||
`define H_SYNCH 48 // pixels
|
||||
`define H_BACK_PORCH 112 // pixels
|
||||
`define H_TOTAL 832 // pixels
|
||||
|
||||
`define V_ACTIVE 480 // lines
|
||||
`define V_FRONT_PORCH 1 // lines
|
||||
`define V_SYNCH 3 // lines
|
||||
`define V_BACK_PORCH 25 // lines
|
||||
`define V_TOTAL 509 // lines
|
||||
|
||||
`define CLK_MULTIPLY 18 // 50 * 18/25 = 36.000 MHz
|
||||
`define CLK_DIVIDE 25
|
||||
*/
|
||||
|
||||
/*
|
||||
// 800 X 600 @ 56Hz with a 38.100MHz pixel clock
|
||||
`define H_ACTIVE 800 // pixels
|
||||
`define H_FRONT_PORCH 32 // pixels
|
||||
`define H_SYNCH 128 // pixels
|
||||
`define H_BACK_PORCH 128 // pixels
|
||||
`define H_TOTAL 1088 // pixels
|
||||
|
||||
`define V_ACTIVE 600 // lines
|
||||
`define V_FRONT_PORCH 1 // lines
|
||||
`define V_SYNCH 4 // lines
|
||||
`define V_BACK_PORCH 14 // lines
|
||||
`define V_TOTAL 619 // lines
|
||||
|
||||
`define CLK_MULTIPLY 16 // 50 * 16/21 = 38.095 MHz
|
||||
`define CLK_DIVIDE 21
|
||||
*/
|
||||
|
||||
/*
|
||||
// 800 X 600 @ 60Hz with a 40.000MHz pixel clock
|
||||
`define H_ACTIVE 800 // pixels
|
||||
`define H_FRONT_PORCH 40 // pixels
|
||||
`define H_SYNCH 128 // pixels
|
||||
`define H_BACK_PORCH 88 // pixels
|
||||
`define H_TOTAL 1056 // pixels
|
||||
|
||||
`define V_ACTIVE 600 // lines
|
||||
`define V_FRONT_PORCH 1 // lines
|
||||
`define V_SYNCH 4 // lines
|
||||
`define V_BACK_PORCH 23 // lines
|
||||
`define V_TOTAL 628 // lines
|
||||
|
||||
`define CLK_MULTIPLY 4 // 50 * 4/5 = 40.000 MHz
|
||||
`define CLK_DIVIDE 5
|
||||
*/
|
||||
|
||||
/*
|
||||
// 800 X 600 @ 72Hz with a 50.000MHz pixel clock
|
||||
`define H_ACTIVE 800 // pixels
|
||||
`define H_FRONT_PORCH 56 // pixels
|
||||
`define H_SYNCH 120 // pixels
|
||||
`define H_BACK_PORCH 64 // pixels
|
||||
`define H_TOTAL 1040 // pixels
|
||||
|
||||
`define V_ACTIVE 600 // lines
|
||||
`define V_FRONT_PORCH 37 // lines
|
||||
`define V_SYNCH 6 // lines
|
||||
`define V_BACK_PORCH 23 // lines
|
||||
`define V_TOTAL 666 // lines
|
||||
|
||||
`define CLK_MULTIPLY 2 // 50 * 2/2 = 50.000 MHz
|
||||
`define CLK_DIVIDE 2
|
||||
*/
|
||||
|
||||
/*
|
||||
// 800 X 600 @ 75Hz with a 49.500MHz pixel clock
|
||||
`define H_ACTIVE 800 // pixels
|
||||
`define H_FRONT_PORCH 16 // pixels
|
||||
`define H_SYNCH 80 // pixels
|
||||
`define H_BACK_PORCH 160 // pixels
|
||||
`define H_TOTAL 1056 // pixels
|
||||
|
||||
`define V_ACTIVE 600 // lines
|
||||
`define V_FRONT_PORCH 1 // lines
|
||||
`define V_SYNCH 2 // lines
|
||||
`define V_BACK_PORCH 21 // lines
|
||||
`define V_TOTAL 624 // lines
|
||||
|
||||
`define CLK_MULTIPLY 2 // 50 * 2/2 = 50.000 MHz
|
||||
`define CLK_DIVIDE 2
|
||||
*/
|
||||
|
||||
/*
|
||||
// 800 X 600 @ 85Hz with a 56.250MHz pixel clock
|
||||
`define H_ACTIVE 800 // pixels
|
||||
`define H_FRONT_PORCH 32 // pixels
|
||||
`define H_SYNCH 64 // pixels
|
||||
`define H_BACK_PORCH 152 // pixels
|
||||
`define H_TOTAL 1048 // pixels
|
||||
|
||||
`define V_ACTIVE 600 // lines
|
||||
`define V_FRONT_PORCH 1 // lines
|
||||
`define V_SYNCH 3 // lines
|
||||
`define V_BACK_PORCH 27 // lines
|
||||
`define V_TOTAL 631 // lines
|
||||
|
||||
`define CLK_MULTIPLY 9 // 50 * 9/8 = 56.250 MHz
|
||||
`define CLK_DIVIDE 8
|
||||
*/
|
||||
|
||||
/*
|
||||
// 1024 X 768 @ 60Hz with a 65.000MHz pixel clock
|
||||
`define H_ACTIVE 1024 // pixels
|
||||
`define H_FRONT_PORCH 24 // pixels
|
||||
`define H_SYNCH 136 // pixels
|
||||
`define H_BACK_PORCH 160 // pixels
|
||||
`define H_TOTAL 1344 // pixels
|
||||
|
||||
`define V_ACTIVE 768 // lines
|
||||
`define V_FRONT_PORCH 3 // lines
|
||||
`define V_SYNCH 6 // lines
|
||||
`define V_BACK_PORCH 29 // lines
|
||||
`define V_TOTAL 806 // lines
|
||||
|
||||
`define CLK_MULTIPLY 13 // 50 * 13/10 = 65.000 MHz
|
||||
`define CLK_DIVIDE 10
|
||||
/*
|
||||
|
||||
/*
|
||||
// 1024 X 768 @ 70Hz with a 75.000MHz pixel clock
|
||||
`define H_ACTIVE 1024 // pixels
|
||||
`define H_FRONT_PORCH 24 // pixels
|
||||
`define H_SYNCH 136 // pixels
|
||||
`define H_BACK_PORCH 144 // pixels
|
||||
`define H_TOTAL 1328 // pixels
|
||||
|
||||
`define V_ACTIVE 768 // lines
|
||||
`define V_FRONT_PORCH 3 // lines
|
||||
`define V_SYNCH 6 // lines
|
||||
`define V_BACK_PORCH 29 // lines
|
||||
`define V_TOTAL 806 // lines
|
||||
|
||||
`define CLK_MULTIPLY 3 // 50 * 3/2 = 75.000 MHz
|
||||
`define CLK_DIVIDE 2
|
||||
*/
|
||||
|
||||
/*
|
||||
// 1024 X 768 @ 75Hz with a 78.750MHz pixel clock
|
||||
`define H_ACTIVE 1024 // pixels
|
||||
`define H_FRONT_PORCH 16 // pixels
|
||||
`define H_SYNCH 96 // pixels
|
||||
`define H_BACK_PORCH 176 // pixels
|
||||
`define H_TOTAL 1312 // pixels
|
||||
|
||||
`define V_ACTIVE 768 // lines
|
||||
`define V_FRONT_PORCH 1 // lines
|
||||
`define V_SYNCH 3 // lines
|
||||
`define V_BACK_PORCH 28 // lines
|
||||
`define V_TOTAL 800 // lines
|
||||
|
||||
`define CLK_MULTIPLY 11 // 50 * 11/7 = 78.571 MHz
|
||||
`define CLK_DIVIDE 7
|
||||
*/
|
||||
|
||||
/*
|
||||
// 1024 X 768 @ 85Hz with a 94.500MHz pixel clock
|
||||
`define H_ACTIVE 1024 // pixels
|
||||
`define H_FRONT_PORCH 48 // pixels
|
||||
`define H_SYNCH 96 // pixels
|
||||
`define H_BACK_PORCH 208 // pixels
|
||||
`define H_TOTAL 1376 // pixels
|
||||
|
||||
`define V_ACTIVE 768 // lines
|
||||
`define V_FRONT_PORCH 1 // lines
|
||||
`define V_SYNCH 3 // lines
|
||||
`define V_BACK_PORCH 36 // lines
|
||||
`define V_TOTAL 808 // lines
|
||||
|
||||
`define CLK_MULTIPLY 17 // 50 * 17/9 = 94.444 MHz
|
||||
`define CLK_DIVIDE 9
|
||||
*/
|
||||
|
||||
353
Computer_MiST/Laser310_MiST/rtl/SVGA_TIMING_GENERATION.v
Normal file
353
Computer_MiST/Laser310_MiST/rtl/SVGA_TIMING_GENERATION.v
Normal file
@@ -0,0 +1,353 @@
|
||||
`include "SVGA_DEFINES.v"
|
||||
|
||||
|
||||
`define SVGA_DECODE_DELAY 7
|
||||
// 延时：字符模式
|
||||
// 1、(001)锁存 vram 地址，2、(010)读取 vram 3、(011)锁存 vram 数据 4、(100)字库地址 5、(101)锁存字库
|
||||
// 6、(110)移位得到点阵，同时锁存vram数据用于调色板 7、(111)建立调色板，锁存色彩
|
||||
|
||||
// Delay: Character mode
|
||||
// 1 (001) latch vram address, 2, (010) read vram 3, (011) latch vram data 4, (100) font address 5, (101) latch font
|
||||
// 6, (110) shift to get a lattice, while latching vram data for the palette 7, (111) to create a palette, latch color
|
||||
|
||||
// 延时：图形模式 128x64 4色
|
||||
// 1、(001)锁存 vram 地址，2、(010)读取 vram 3、(011)锁存 vram 数据 4、(100)空 5、(101)数据锁存至移位寄存器
|
||||
// 6、(110)移位得到点阵 7、(111)建立调色板，锁存色彩
|
||||
|
||||
// Delay: graphics mode 128x64 4 colors
|
||||
// 1, (001) latch vram address, 2, (010) read vram 3, (011) latch vram data 4, (100) empty 5, (101) data latched to the shift register
|
||||
// 6, (110) shift to get the dot matrix 7, (111) to create a palette, latch color
|
||||
|
||||
module SVGA_TIMING_GENERATION
|
||||
(
|
||||
pixel_clock,
|
||||
reset,
|
||||
h_synch,
|
||||
v_synch,
|
||||
blank,
|
||||
pixel_count,
|
||||
line_count,
|
||||
|
||||
show_border,
|
||||
|
||||
// text
|
||||
subchar_pixel,
|
||||
subchar_line,
|
||||
char_column,
|
||||
char_line,
|
||||
|
||||
// graph
|
||||
graph_pixel,
|
||||
graph_line_2x,
|
||||
graph_line_3x
|
||||
);
|
||||
|
||||
input pixel_clock; // pixel clock
|
||||
input reset; // reset
|
||||
(*keep*)output reg h_synch; // horizontal synch for VGA connector
|
||||
(*keep*)output reg v_synch; // vertical synch for VGA connector
|
||||
output reg blank; // composite blanking
|
||||
output reg [10:0] pixel_count; // counts the pixels in a line
|
||||
output reg [9:0] line_count; // counts the display lines
|
||||
|
||||
(*keep*)output reg show_border;
|
||||
|
||||
// 字符控制
|
||||
(*keep*)output reg [3:0] subchar_pixel; // pixel position within the character
|
||||
(*keep*)output reg [4:0] subchar_line; // identifies the line number within a character block
|
||||
(*keep*)output reg [6:0] char_column; // character number on the current line
|
||||
(*keep*)output reg [6:0] char_line; // line number on the screen
|
||||
|
||||
// 图形控制 128*64
|
||||
(*keep*)output reg [8:0] graph_pixel;
|
||||
(*keep*)output reg [9:0] graph_line_3x;
|
||||
|
||||
// 图形控制 256*192
|
||||
(*keep*)output reg [9:0] graph_line_2x;
|
||||
|
||||
(*keep*)reg h_blank;
|
||||
reg v_blank;
|
||||
|
||||
reg show_pixel;
|
||||
reg show_line;
|
||||
|
||||
// CREATE THE HORIZONTAL LINE PIXEL COUNTER
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
// on reset set pixel counter to 0
|
||||
pixel_count <= 11'd0;
|
||||
|
||||
else if (pixel_count == (`H_TOTAL - 1))
|
||||
// last pixel in the line, so reset pixel counter
|
||||
pixel_count <= 11'd0;
|
||||
|
||||
else
|
||||
pixel_count <= pixel_count + 1;
|
||||
end
|
||||
|
||||
// CREATE THE HORIZONTAL SYNCH PULSE
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
// on reset remove h_synch
|
||||
h_synch <= 1'b0;
|
||||
|
||||
else if (pixel_count == (`H_ACTIVE + `H_FRONT_PORCH - 1))
|
||||
// start of h_synch
|
||||
h_synch <= 1'b1;
|
||||
|
||||
else if (pixel_count == (`H_TOTAL - `H_BACK_PORCH - 1))
|
||||
// end of h_synch
|
||||
h_synch <= 1'b0;
|
||||
end
|
||||
|
||||
// CREATE THE VERTICAL FRAME LINE COUNTER
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
// on reset set line counter to 0
|
||||
line_count <= 10'd0;
|
||||
|
||||
else if ((line_count == (`V_TOTAL - 1)) & (pixel_count == (`H_TOTAL - 1)))
|
||||
// last pixel in last line of frame, so reset line counter
|
||||
line_count <= 10'd0;
|
||||
|
||||
else if ((pixel_count == (`H_TOTAL - 1)))
|
||||
// last pixel but not last line, so increment line counter
|
||||
line_count <= line_count + 1;
|
||||
end
|
||||
|
||||
// CREATE THE VERTICAL SYNCH PULSE
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
// on reset remove v_synch
|
||||
v_synch <= 1'b0;
|
||||
|
||||
else if ((line_count == (`V_ACTIVE + `V_FRONT_PORCH - 1) &
|
||||
(pixel_count == `H_TOTAL - 1)))
|
||||
// start of v_synch
|
||||
v_synch <= 1'b1;
|
||||
|
||||
else if ((line_count == (`V_TOTAL - `V_BACK_PORCH - 1)) &
|
||||
(pixel_count == (`H_TOTAL - 1)))
|
||||
// end of v_synch
|
||||
v_synch <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
// CREATE THE HORIZONTAL BLANKING SIGNAL
|
||||
// the "-2" is used instead of "-1" because of the extra register delay
|
||||
// for the composite blanking signal
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
// on reset remove the h_blank
|
||||
h_blank <= 1'b0;
|
||||
|
||||
else if (pixel_count == (`H_ACTIVE -2))
|
||||
// start of HBI
|
||||
h_blank <= 1'b1;
|
||||
|
||||
else if (pixel_count == (`H_TOTAL -2))
|
||||
// end of HBI
|
||||
h_blank <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
// CREATE THE VERTICAL BLANKING SIGNAL
|
||||
// the "-2" is used instead of "-1" in the horizontal factor because of the extra
|
||||
// register delay for the composite blanking signal
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
// on reset remove v_blank
|
||||
v_blank <= 1'b0;
|
||||
|
||||
else if ((line_count == (`V_ACTIVE - 1) &
|
||||
(pixel_count == `H_TOTAL - 2)))
|
||||
// start of VBI
|
||||
v_blank <= 1'b1;
|
||||
|
||||
else if ((line_count == (`V_TOTAL - 1)) &
|
||||
(pixel_count == (`H_TOTAL - 2)))
|
||||
// end of VBI
|
||||
v_blank <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
// CREATE THE COMPOSITE BANKING SIGNAL
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
// on reset remove blank
|
||||
blank <= 1'b0;
|
||||
|
||||
// blank during HBI or VBI
|
||||
else if (h_blank || v_blank)
|
||||
blank <= 1'b1;
|
||||
|
||||
else
|
||||
// active video do not blank
|
||||
blank <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
// 以上部分内容相对固定，是VGA的控制信号和计数器 //
|
||||
////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/*
|
||||
CREATE THE CHARACTER COUNTER.
|
||||
CHARACTERS ARE DEFINED WITHIN AN 8 x 8 PIXEL BLOCK.
|
||||
|
||||
A 640 x 480 video mode will display 80 characters on 60 lines.
|
||||
A 800 x 600 video mode will display 100 characters on 75 lines.
|
||||
A 1024 x 768 video mode will display 128 characters on 96 lines.
|
||||
|
||||
"subchar_line" identifies the row in the 8 x 8 block.
|
||||
"subchar_pixel" identifies the column in the 8 x 8 block.
|
||||
*/
|
||||
|
||||
// 8x12点阵 32x16个字符 256x192
|
||||
// 640x480 倍线 512x384 左右各空64个点，上下空 48 个点。
|
||||
// 需要生成四个数据：
|
||||
// 字符点阵 subchar_line subchar_pixel
|
||||
// 字符寻址 char_column char_line
|
||||
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
show_pixel <= 1'b0;
|
||||
else if (pixel_count == (-1) + 64 - `SVGA_DECODE_DELAY)
|
||||
show_pixel <= 1'b1;
|
||||
else if (pixel_count == (`H_ACTIVE - 1) - 64 - `SVGA_DECODE_DELAY)
|
||||
show_pixel <= 1'b0;
|
||||
end
|
||||
|
||||
always @ (posedge h_synch or posedge reset) begin
|
||||
if (reset)
|
||||
show_line <= 1'b0;
|
||||
else if (line_count == (-1) + 48)
|
||||
show_line <= 1'b1;
|
||||
else if (line_count == (`V_ACTIVE - 1) - 48)
|
||||
show_line <= 1'b0;
|
||||
end
|
||||
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
show_border <= 1'b1;
|
||||
else if (pixel_count == (-1) + 64)
|
||||
show_border <= ~show_line;
|
||||
else if (pixel_count == (`H_ACTIVE - 1) - 64)
|
||||
show_border <= 1'b1;
|
||||
end
|
||||
|
||||
|
||||
// text 32x16
|
||||
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
// reset to 5 so that the first character data can be latched
|
||||
subchar_pixel <= 4'b0000;
|
||||
char_column <= 7'd0;
|
||||
end
|
||||
else if (h_synch)
|
||||
begin
|
||||
// reset to 5 so that the first character data can be latched
|
||||
subchar_pixel <= 4'b0000;
|
||||
char_column <= 7'd0;
|
||||
end
|
||||
else if(show_pixel)
|
||||
begin
|
||||
subchar_pixel <= subchar_pixel + 1;
|
||||
if(subchar_pixel == 4'b1111) // 8*2-1
|
||||
char_column <= char_column + 1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @ (posedge h_synch or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
// on reset set line counter to 0
|
||||
subchar_line <= 5'b00000;
|
||||
char_line <= 7'd0;
|
||||
end
|
||||
else if(v_synch)
|
||||
begin
|
||||
// reset line counter
|
||||
subchar_line <= 5'b00000;
|
||||
char_line <= 7'd0;
|
||||
end
|
||||
else if(show_line)
|
||||
if(subchar_line == 5'd23) // 12*2-1
|
||||
begin
|
||||
subchar_line <= 5'b00000;
|
||||
char_line <= char_line + 1;
|
||||
end
|
||||
else
|
||||
// increment line counter
|
||||
subchar_line <= subchar_line + 1;
|
||||
end
|
||||
|
||||
|
||||
// 为所有图形模式提供水平计数
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
// reset to 5 so that the first character data can be latched
|
||||
graph_pixel <= 9'd0;
|
||||
end
|
||||
else if (h_synch)
|
||||
begin
|
||||
// reset to 5 so that the first character data can be latched
|
||||
graph_pixel <= 9'd0;
|
||||
end
|
||||
else if(show_pixel)
|
||||
begin
|
||||
graph_pixel <= graph_pixel + 1;
|
||||
end
|
||||
end
|
||||
|
||||
// 为图形模式提供垂直计数
|
||||
// 64x64 4色
|
||||
// 128x64 2色
|
||||
// 128x64 4色
|
||||
always @ (posedge h_synch or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
// on reset set line counter to 0
|
||||
graph_line_3x <= 10'd0;
|
||||
end
|
||||
else if(v_synch)
|
||||
begin
|
||||
// reset line counter
|
||||
graph_line_3x <= 10'd0;
|
||||
end
|
||||
else if(show_line)
|
||||
if(graph_line_3x[1:0] == 2'b10) // 3行为单位计数
|
||||
graph_line_3x <= graph_line_3x + 2;
|
||||
else
|
||||
// increment line counter
|
||||
graph_line_3x <= graph_line_3x + 1;
|
||||
end
|
||||
|
||||
// 为图形模式提供垂直计数
|
||||
// 128x96 2色
|
||||
// 128x96 4色
|
||||
// 128x192 2色
|
||||
// 128x192 4色
|
||||
// 256x192 2色
|
||||
always @ (posedge h_synch or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
// on reset set line counter to 0
|
||||
graph_line_2x <= 10'd0;
|
||||
end
|
||||
else if(v_synch)
|
||||
begin
|
||||
// reset line counter
|
||||
graph_line_2x <= 10'd0;
|
||||
end
|
||||
else if(show_line)
|
||||
// increment line counter
|
||||
graph_line_2x <= graph_line_2x + 1;
|
||||
end
|
||||
|
||||
endmodule //SVGA_TIMING_GENERATION
|
||||
1080
Computer_MiST/Laser310_MiST/rtl/T80/T80.vhd
Normal file
1080
Computer_MiST/Laser310_MiST/rtl/T80/T80.vhd
Normal file
File diff suppressed because it is too large
Load Diff
371
Computer_MiST/Laser310_MiST/rtl/T80/T80_ALU.vhd
Normal file
371
Computer_MiST/Laser310_MiST/rtl/T80/T80_ALU.vhd
Normal file
@@ -0,0 +1,371 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0247
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
|
||||
--
|
||||
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
|
||||
--
|
||||
-- 0240 : Added GB operations
|
||||
--
|
||||
-- 0242 : Cleanup
|
||||
--
|
||||
-- 0247 : Cleanup
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_ALU is
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_ALU;
|
||||
|
||||
architecture rtl of T80_ALU is
|
||||
|
||||
procedure AddSub(A : std_logic_vector;
|
||||
B : std_logic_vector;
|
||||
Sub : std_logic;
|
||||
Carry_In : std_logic;
|
||||
signal Res : out std_logic_vector;
|
||||
signal Carry : out std_logic) is
|
||||
|
||||
variable B_i : unsigned(A'length - 1 downto 0);
|
||||
variable Res_i : unsigned(A'length + 1 downto 0);
|
||||
begin
|
||||
if Sub = '1' then
|
||||
B_i := not unsigned(B);
|
||||
else
|
||||
B_i := unsigned(B);
|
||||
end if;
|
||||
|
||||
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
|
||||
Carry <= Res_i(A'length + 1);
|
||||
Res <= std_logic_vector(Res_i(A'length downto 1));
|
||||
end;
|
||||
|
||||
-- AddSub variables (temporary signals)
|
||||
signal UseCarry : std_logic;
|
||||
signal Carry7_v : std_logic;
|
||||
signal Overflow_v : std_logic;
|
||||
signal HalfCarry_v : std_logic;
|
||||
signal Carry_v : std_logic;
|
||||
signal Q_v : std_logic_vector(7 downto 0);
|
||||
|
||||
signal BitMask : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
with IR(5 downto 3) select BitMask <= "00000001" when "000",
|
||||
"00000010" when "001",
|
||||
"00000100" when "010",
|
||||
"00001000" when "011",
|
||||
"00010000" when "100",
|
||||
"00100000" when "101",
|
||||
"01000000" when "110",
|
||||
"10000000" when others;
|
||||
|
||||
UseCarry <= not ALU_Op(2) and ALU_Op(0);
|
||||
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
|
||||
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
|
||||
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
|
||||
|
||||
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
|
||||
process (Carry_v, Carry7_v, Q_v)
|
||||
begin
|
||||
if(Mode=2) then
|
||||
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
|
||||
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
|
||||
OverFlow_v <= Carry_v xor Carry7_v;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
|
||||
variable Q_t : std_logic_vector(7 downto 0);
|
||||
variable DAA_Q : unsigned(8 downto 0);
|
||||
begin
|
||||
Q_t := "--------";
|
||||
F_Out <= F_In;
|
||||
DAA_Q := "---------";
|
||||
case ALU_Op is
|
||||
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_C) <= '0';
|
||||
case ALU_OP(2 downto 0) is
|
||||
when "000" | "001" => -- ADD, ADC
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_C) <= Carry_v;
|
||||
F_Out(Flag_H) <= HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "010" | "011" | "111" => -- SUB, SBC, CP
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_N) <= '1';
|
||||
F_Out(Flag_C) <= not Carry_v;
|
||||
F_Out(Flag_H) <= not HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "100" => -- AND
|
||||
Q_t(7 downto 0) := BusA and BusB;
|
||||
F_Out(Flag_H) <= '1';
|
||||
when "101" => -- XOR
|
||||
Q_t(7 downto 0) := BusA xor BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
when others => -- OR "110"
|
||||
Q_t(7 downto 0) := BusA or BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
end case;
|
||||
if ALU_Op(2 downto 0) = "111" then -- CP
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
else
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
end if;
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
if Z16 = '1' then
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
|
||||
end if;
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
case ALU_Op(2 downto 0) is
|
||||
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
|
||||
when others =>
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
end case;
|
||||
if Arith16 = '1' then
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
end if;
|
||||
when "1100" =>
|
||||
-- DAA
|
||||
F_Out(Flag_H) <= F_In(Flag_H);
|
||||
F_Out(Flag_C) <= F_In(Flag_C);
|
||||
DAA_Q(7 downto 0) := unsigned(BusA);
|
||||
DAA_Q(8) := '0';
|
||||
if F_In(Flag_N) = '0' then
|
||||
-- After addition
|
||||
-- Alow > 9 or H = 1
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if (DAA_Q(3 downto 0) > 9) then
|
||||
F_Out(Flag_H) <= '1';
|
||||
else
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q := DAA_Q + 6;
|
||||
end if;
|
||||
-- new Ahigh > 9 or C = 1
|
||||
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q + 96; -- 0x60
|
||||
end if;
|
||||
else
|
||||
-- After subtraction
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if DAA_Q(3 downto 0) > 5 then
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
|
||||
end if;
|
||||
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q - 352; -- 0x160
|
||||
end if;
|
||||
end if;
|
||||
F_Out(Flag_X) <= DAA_Q(3);
|
||||
F_Out(Flag_Y) <= DAA_Q(5);
|
||||
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
|
||||
Q_t := std_logic_vector(DAA_Q(7 downto 0));
|
||||
if DAA_Q(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= DAA_Q(7);
|
||||
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
|
||||
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
|
||||
when "1101" | "1110" =>
|
||||
-- RLD, RRD
|
||||
Q_t(7 downto 4) := BusA(7 downto 4);
|
||||
if ALU_Op(0) = '1' then
|
||||
Q_t(3 downto 0) := BusB(7 downto 4);
|
||||
else
|
||||
Q_t(3 downto 0) := BusB(3 downto 0);
|
||||
end if;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
when "1001" =>
|
||||
-- BIT
|
||||
Q_t(7 downto 0) := BusB and BitMask;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
F_Out(Flag_P) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
F_Out(Flag_P) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_H) <= '1';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= '0';
|
||||
F_Out(Flag_Y) <= '0';
|
||||
if IR(2 downto 0) /= "110" then
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
end if;
|
||||
when "1010" =>
|
||||
-- SET
|
||||
Q_t(7 downto 0) := BusB or BitMask;
|
||||
when "1011" =>
|
||||
-- RES
|
||||
Q_t(7 downto 0) := BusB and not BitMask;
|
||||
when "1000" =>
|
||||
-- ROT
|
||||
case IR(5 downto 3) is
|
||||
when "000" => -- RLC
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "010" => -- RL
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "001" => -- RRC
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(0);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "011" => -- RR
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "100" => -- SLA
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '0';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "110" => -- SLL (Undocumented) / SWAP
|
||||
if Mode = 3 then
|
||||
Q_t(7 downto 4) := BusA(3 downto 0);
|
||||
Q_t(3 downto 0) := BusA(7 downto 4);
|
||||
F_Out(Flag_C) <= '0';
|
||||
else
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '1';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
end if;
|
||||
when "101" => -- SRA
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when others => -- SRL
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := '0';
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
end case;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
if ISet = "00" then
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
Q <= Q_t;
|
||||
end process;
|
||||
end;
|
||||
1944
Computer_MiST/Laser310_MiST/rtl/T80/T80_MCode.vhd
Normal file
1944
Computer_MiST/Laser310_MiST/rtl/T80/T80_MCode.vhd
Normal file
File diff suppressed because it is too large
Load Diff
217
Computer_MiST/Laser310_MiST/rtl/T80/T80_Pack.vhd
Normal file
217
Computer_MiST/Laser310_MiST/rtl/T80/T80_Pack.vhd
Normal file
@@ -0,0 +1,217 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0242
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
package T80_Pack is
|
||||
|
||||
component T80
|
||||
generic(
|
||||
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
IORQ : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DInst : in std_logic_vector(7 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0);
|
||||
MC : out std_logic_vector(2 downto 0);
|
||||
TS : out std_logic_vector(2 downto 0);
|
||||
IntCycle_n : out std_logic;
|
||||
IntE : out std_logic;
|
||||
Stop : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_Reg
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_MCode
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
IR : in std_logic_vector(7 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
MCycle : in std_logic_vector(2 downto 0);
|
||||
F : in std_logic_vector(7 downto 0);
|
||||
NMICycle : in std_logic;
|
||||
IntCycle : in std_logic;
|
||||
MCycles : out std_logic_vector(2 downto 0);
|
||||
TStates : out std_logic_vector(2 downto 0);
|
||||
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
|
||||
Inc_PC : out std_logic;
|
||||
Inc_WZ : out std_logic;
|
||||
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
|
||||
Read_To_Reg : out std_logic;
|
||||
Read_To_Acc : out std_logic;
|
||||
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
|
||||
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
|
||||
ALU_Op : out std_logic_vector(3 downto 0);
|
||||
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
|
||||
Save_ALU : out std_logic;
|
||||
PreserveC : out std_logic;
|
||||
Arith16 : out std_logic;
|
||||
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
|
||||
IORQ : out std_logic;
|
||||
Jump : out std_logic;
|
||||
JumpE : out std_logic;
|
||||
JumpXY : out std_logic;
|
||||
Call : out std_logic;
|
||||
RstP : out std_logic;
|
||||
LDZ : out std_logic;
|
||||
LDW : out std_logic;
|
||||
LDSPHL : out std_logic;
|
||||
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
|
||||
ExchangeDH : out std_logic;
|
||||
ExchangeRp : out std_logic;
|
||||
ExchangeAF : out std_logic;
|
||||
ExchangeRS : out std_logic;
|
||||
I_DJNZ : out std_logic;
|
||||
I_CPL : out std_logic;
|
||||
I_CCF : out std_logic;
|
||||
I_SCF : out std_logic;
|
||||
I_RETN : out std_logic;
|
||||
I_BT : out std_logic;
|
||||
I_BC : out std_logic;
|
||||
I_BTR : out std_logic;
|
||||
I_RLD : out std_logic;
|
||||
I_RRD : out std_logic;
|
||||
I_INRC : out std_logic;
|
||||
SetDI : out std_logic;
|
||||
SetEI : out std_logic;
|
||||
IMode : out std_logic_vector(1 downto 0);
|
||||
Halt : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_ALU
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
end;
|
||||
105
Computer_MiST/Laser310_MiST/rtl/T80/T80_Reg.vhd
Normal file
105
Computer_MiST/Laser310_MiST/rtl/T80/T80_Reg.vhd
Normal file
@@ -0,0 +1,105 @@
|
||||
--
|
||||
-- T80 Registers, technology independent
|
||||
--
|
||||
-- Version : 0244
|
||||
--
|
||||
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t51/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0242 : Initial release
|
||||
--
|
||||
-- 0244 : Changed to single register file
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_Reg is
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_Reg;
|
||||
|
||||
architecture rtl of T80_Reg is
|
||||
|
||||
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
|
||||
signal RegsH : Register_Image(0 to 7);
|
||||
signal RegsL : Register_Image(0 to 7);
|
||||
|
||||
begin
|
||||
|
||||
process (Clk)
|
||||
begin
|
||||
if Clk'event and Clk = '1' then
|
||||
if CEN = '1' then
|
||||
if WEH = '1' then
|
||||
RegsH(to_integer(unsigned(AddrA))) <= DIH;
|
||||
end if;
|
||||
if WEL = '1' then
|
||||
RegsL(to_integer(unsigned(AddrA))) <= DIL;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DOAH <= RegsH(to_integer(unsigned(AddrA)));
|
||||
DOAL <= RegsL(to_integer(unsigned(AddrA)));
|
||||
DOBH <= RegsH(to_integer(unsigned(AddrB)));
|
||||
DOBL <= RegsL(to_integer(unsigned(AddrB)));
|
||||
DOCH <= RegsH(to_integer(unsigned(AddrC)));
|
||||
DOCL <= RegsL(to_integer(unsigned(AddrC)));
|
||||
|
||||
end;
|
||||
179
Computer_MiST/Laser310_MiST/rtl/T80/T80sed.vhd
Normal file
179
Computer_MiST/Laser310_MiST/rtl/T80/T80sed.vhd
Normal file
@@ -0,0 +1,179 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
|
||||
--
|
||||
-- Z80 compatible microprocessor core, synchronous top level with clock enable
|
||||
-- Different timing than the original z80
|
||||
-- Inputs needs to be synchronous and outputs may glitch
|
||||
--
|
||||
-- Version : 0238
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0235 : First release
|
||||
--
|
||||
-- 0236 : Added T2Write generic
|
||||
--
|
||||
-- 0237 : Fixed T2Write with wait state
|
||||
--
|
||||
-- 0238 : Updated for T80 interface change
|
||||
--
|
||||
-- 0242 : Updated for T80 interface change
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.T80_Pack.all;
|
||||
|
||||
entity T80sed is
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CLKEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
MREQ_n : out std_logic;
|
||||
IORQ_n : out std_logic;
|
||||
RD_n : out std_logic;
|
||||
WR_n : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80sed;
|
||||
|
||||
architecture rtl of T80sed is
|
||||
|
||||
signal IntCycle_n : std_logic;
|
||||
signal NoRead : std_logic;
|
||||
signal Write : std_logic;
|
||||
signal IORQ : std_logic;
|
||||
signal DI_Reg : std_logic_vector(7 downto 0);
|
||||
signal MCycle : std_logic_vector(2 downto 0);
|
||||
signal TState : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
u0 : T80
|
||||
generic map(
|
||||
Mode => 0,
|
||||
IOWait => 1)
|
||||
port map(
|
||||
CEN => CLKEN,
|
||||
M1_n => M1_n,
|
||||
IORQ => IORQ,
|
||||
NoRead => NoRead,
|
||||
Write => Write,
|
||||
RFSH_n => RFSH_n,
|
||||
HALT_n => HALT_n,
|
||||
WAIT_n => Wait_n,
|
||||
INT_n => INT_n,
|
||||
NMI_n => NMI_n,
|
||||
RESET_n => RESET_n,
|
||||
BUSRQ_n => BUSRQ_n,
|
||||
BUSAK_n => BUSAK_n,
|
||||
CLK_n => CLK_n,
|
||||
A => A,
|
||||
DInst => DI,
|
||||
DI => DI_Reg,
|
||||
DO => DO,
|
||||
MC => MCycle,
|
||||
TS => TState,
|
||||
IntCycle_n => IntCycle_n);
|
||||
|
||||
process (RESET_n, CLK_n)
|
||||
begin
|
||||
if RESET_n = '0' then
|
||||
RD_n <= '1';
|
||||
WR_n <= '1';
|
||||
IORQ_n <= '1';
|
||||
MREQ_n <= '1';
|
||||
DI_Reg <= "00000000";
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
if CLKEN = '1' then
|
||||
RD_n <= '1';
|
||||
WR_n <= '1';
|
||||
IORQ_n <= '1';
|
||||
MREQ_n <= '1';
|
||||
if MCycle = "001" then
|
||||
if TState = "001" or (TState = "010" and Wait_n = '0') then
|
||||
RD_n <= not IntCycle_n;
|
||||
MREQ_n <= not IntCycle_n;
|
||||
IORQ_n <= IntCycle_n;
|
||||
end if;
|
||||
if TState = "011" then
|
||||
MREQ_n <= '0';
|
||||
end if;
|
||||
else
|
||||
if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
|
||||
RD_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
if ((TState = "001") or (TState = "010")) and Write = '1' then
|
||||
WR_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
end if;
|
||||
if TState = "010" and Wait_n = '1' then
|
||||
DI_Reg <= DI;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
483
Computer_MiST/Laser310_MiST/rtl/Text1.txt
Normal file
483
Computer_MiST/Laser310_MiST/rtl/Text1.txt
Normal file
@@ -0,0 +1,483 @@
|
||||
|
||||
|
||||
|
||||
|
||||
// keyboard
|
||||
|
||||
/*****************************************************************************
|
||||
* Convert PS/2 keyboard to ASCII keyboard
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
KD5 KD4 KD3 KD2 KD1 KD0 扫描用地址
|
||||
A0 R Q E W T 68FEH 0
|
||||
A1 F A D CTRL S G 68FDH 8
|
||||
A2 V Z C SHFT X B 68FBH 16
|
||||
A3 4 1 3 2 5 68F7H 24
|
||||
A4 M 空格 ， . N 68EFH 32
|
||||
A5 7 0 8 - 9 6 68DFH 40
|
||||
A6 U P I RETN O Y 68BFH 48
|
||||
A7 J ； K : L H 687FH 56
|
||||
*/
|
||||
|
||||
// 7: 0
|
||||
// 15: 8
|
||||
// 23:16
|
||||
// 31:24
|
||||
// 39:32
|
||||
// 47:40
|
||||
// 55:48
|
||||
// 63:56
|
||||
|
||||
|
||||
|
||||
// 键盘检测的方法，就是循环地问每一行线发送低电平信号，也就是用该地址线为“0”的地址去读取数据。
|
||||
// 例如，检测第一行时，使A0为0，其余为1；加上选通IC4的高五位地址01101，成为01101***11111110B（A8~A10不起作用，
|
||||
// 可为任意值，故68FEH，69FEH，6AFEH，6BFEH，6CFEH，6DFEH，6EFEH，6FFEH均可）。
|
||||
// 读 6800H 判断是否有按键按下。
|
||||
|
||||
// The method of keyboard detection is to cyclically ask each line to send a low level signal,
|
||||
// that is, to read the data with the address line "0".
|
||||
// For example, when detecting the first line, make A0 0 and the rest 1; plus the high five-bit address 01101 of the strobe IC4,
|
||||
// become 01101***11111110B (A8~A10 does not work,
|
||||
// It can be any value, so 68FEH, 69FEH, 6AFEH, 6BFEH, 6CFEH, 6DFEH, 6EFEH, 6FFEH can be).
|
||||
// Read 6800H to determine if there is a button press.
|
||||
|
||||
// 键盘选通，整个竖列有一个选通的位置被按下，对应值为0。
|
||||
// The keyboard is strobed, and a strobe position is pressed in the entire vertical column, and the corresponding value is 0.
|
||||
|
||||
// 键盘扩展
|
||||
// 加入方向键盘
|
||||
// Keyboard extension
|
||||
|
||||
// left: ctrl M 37 KEY_EX[5]
|
||||
// right: ctrl , 35 KEY_EX[6]
|
||||
// up: ctrl . 33 KEY_EX[4]
|
||||
// down: ctrl space 36 KEY_EX[7]
|
||||
// esc: ctrl - 42 KEY_EX[3]
|
||||
// backspace: ctrl M 37 KEY_EX[8]
|
||||
|
||||
// R-Shift
|
||||
|
||||
|
||||
wire [63:0] KEY_C = EMU_KEY_EN?EMU_KEY:KEY;
|
||||
wire [9:0] KEY_EX_C = EMU_KEY_EN?EMU_KEY_EX:KEY_EX;
|
||||
|
||||
//wire KEY_CTRL_ULRD = (KEY_EX[7:4]==4'b1111);
|
||||
wire KEY_CTRL_ULRD_BRK = (KEY_EX[8:3]==6'b111111);
|
||||
|
||||
wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY_C[61], KEY_C[53], KEY_C[45], KEY_C[37]&KEY_EX_C[5]&KEY_EX_C[8], KEY_C[29], KEY_C[21], KEY_C[13], KEY_C[ 5]})==8'hff;
|
||||
wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY_C[60], KEY_C[52], KEY_C[44], KEY_C[36]&KEY_EX_C[7], KEY_C[28], KEY_C[20], KEY_C[12], KEY_C[ 4]})==8'hff;
|
||||
wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY_C[59], KEY_C[51], KEY_C[43], KEY_C[35]&KEY_EX_C[6], KEY_C[27], KEY_C[19], KEY_C[11], KEY_C[ 3]})==8'hff;
|
||||
wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY_C[58], KEY_C[50], KEY_C[42]&KEY_EX_C[3], KEY_C[34], KEY_C[26], KEY_C[18]&KEY_EX_C[0], KEY_C[10]&KEY_CTRL_ULRD_BRK, KEY_C[ 2]})==8'hff;
|
||||
wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY_C[57], KEY_C[49], KEY_C[41], KEY_C[33]&KEY_EX_C[4], KEY_C[25], KEY_C[17], KEY_C[ 9], KEY_C[ 1]})==8'hff;
|
||||
wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY_C[56], KEY_C[48], KEY_C[40], KEY_C[32], KEY_C[24], KEY_C[16], KEY_C[ 8], KEY_C[ 0]})==8'hff;
|
||||
|
||||
/*
|
||||
wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY[61], KEY[53], KEY[45], KEY[37], KEY[29], KEY[21], KEY[13], KEY[ 5]})==8'hff;
|
||||
wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY[60], KEY[52], KEY[44], KEY[36], KEY[28], KEY[20], KEY[12], KEY[ 4]})==8'hff;
|
||||
wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY[59], KEY[51], KEY[43], KEY[35], KEY[27], KEY[19], KEY[11], KEY[ 3]})==8'hff;
|
||||
wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY[58], KEY[50], KEY[42], KEY[34], KEY[26], KEY[18], KEY[10], KEY[ 2]})==8'hff;
|
||||
wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY[57], KEY[49], KEY[41], KEY[33], KEY[25], KEY[17], KEY[ 9], KEY[ 1]})==8'hff;
|
||||
wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY[56], KEY[48], KEY[40], KEY[32], KEY[24], KEY[16], KEY[ 8], KEY[ 0]})==8'hff;
|
||||
*/
|
||||
|
||||
wire KEY_DATA_BIT7 = 1'b1; // 没有空置，具体用途没有理解
|
||||
//wire KEY_DATA_BIT6 = CASS_IN;
|
||||
wire KEY_DATA_BIT6 = ~CASS_IN;
|
||||
|
||||
assign KEY_DATA = { KEY_DATA_BIT7, KEY_DATA_BIT6, KEY_DATA_BIT5, KEY_DATA_BIT4, KEY_DATA_BIT3, KEY_DATA_BIT2, KEY_DATA_BIT1, KEY_DATA_BIT0 };
|
||||
|
||||
/*
|
||||
assign KEY_DATA = (CPU_A[0]==1'b0) ? KEY[ 7: 0] :
|
||||
(CPU_A[1]==1'b0) ? KEY[15: 8] :
|
||||
(CPU_A[2]==1'b0) ? KEY[23:16] :
|
||||
(CPU_A[3]==1'b0) ? KEY[31:24] :
|
||||
(CPU_A[4]==1'b0) ? KEY[39:32] :
|
||||
(CPU_A[5]==1'b0) ? KEY[47:40] :
|
||||
(CPU_A[6]==1'b0) ? KEY[55:48] :
|
||||
(CPU_A[7]==1'b0) ? KEY[63:56] :
|
||||
8'hff;
|
||||
|
||||
assign KEY_DATA =
|
||||
(CPU_A[7]==1'b0) ? KEY[63:56] :
|
||||
(CPU_A[6]==1'b0) ? KEY[55:48] :
|
||||
(CPU_A[5]==1'b0) ? KEY[47:40] :
|
||||
(CPU_A[4]==1'b0) ? KEY[39:32] :
|
||||
(CPU_A[3]==1'b0) ? KEY[31:24] :
|
||||
(CPU_A[2]==1'b0) ? KEY[23:16] :
|
||||
(CPU_A[1]==1'b0) ? KEY[15: 8] :
|
||||
(CPU_A[0]==1'b0) ? KEY[ 7: 0] :
|
||||
8'hff;
|
||||
*/
|
||||
|
||||
|
||||
assign A_KEY_PRESSED = (KEY[63:0] == 64'hFFFFFFFFFFFFFFFF) ? 1'b0:1'b1;
|
||||
|
||||
always @(posedge KB_CLK[3] or negedge SYS_RESET_N)
|
||||
begin
|
||||
if(~SYS_RESET_N)
|
||||
begin
|
||||
KEY <= 64'hFFFFFFFFFFFFFFFF;
|
||||
KEY_EX <= 10'h3FF;
|
||||
KEY_Fxx <= 12'h000;
|
||||
// CAPS_CLK <= 1'b0;
|
||||
RESET_KEY_COUNT <= 17'h1FFFF;
|
||||
|
||||
BOOTROM_BANK <= 0;
|
||||
BOOTROM_EN <= 1'b0;
|
||||
|
||||
AUTOSTARTROM_BANK <= 0;
|
||||
AUTOSTARTROM_EN <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
//KEY[?] <= CAPS;
|
||||
if(RESET_KEY_COUNT[16]==1'b0)
|
||||
RESET_KEY_COUNT <= RESET_KEY_COUNT+1;
|
||||
|
||||
case(SCAN)
|
||||
8'h07:
|
||||
begin
|
||||
KEY_Fxx[11] <= PRESS; // F12 RESET
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b0;
|
||||
BOOTROM_BANK <= 0;
|
||||
AUTOSTARTROM_EN <= 1'b0;
|
||||
AUTOSTARTROM_BANK <= 0;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h78: KEY_Fxx[10] <= PRESS; // F11
|
||||
8'h09: KEY_Fxx[ 9] <= PRESS; // F10 CASS STOP
|
||||
8'h01: KEY_Fxx[ 8] <= PRESS; // F9 CASS PLAY
|
||||
8'h0A:
|
||||
begin
|
||||
KEY_Fxx[ 7] <= PRESS; // F8 Ctrl or L-Shift BOOT 8
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 39;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 23;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h83:
|
||||
begin
|
||||
KEY_Fxx[ 6] <= PRESS; // F7 Ctrl or L-Shift BOOT 7
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 38;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 22;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h0B:
|
||||
begin
|
||||
KEY_Fxx[ 5] <= PRESS; // F6 Ctrl or L-Shift BOOT 6
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 37;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 21;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h03:
|
||||
begin
|
||||
KEY_Fxx[ 4] <= PRESS; // F5 Ctrl or L-Shift BOOT 5
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 36;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 20;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h0C:
|
||||
begin
|
||||
KEY_Fxx[ 3] <= PRESS; // F4 Ctrl or L-Shift BOOT 4
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 35;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 19;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h04:
|
||||
begin
|
||||
KEY_Fxx[ 2] <= PRESS; // F3 Ctrl or L-Shift BOOT 3
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 34;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 18;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h06:
|
||||
begin
|
||||
KEY_Fxx[ 1] <= PRESS; // F2 Ctrl or L-Shift BOOT 2
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 33;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 17;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h05:
|
||||
begin
|
||||
KEY_Fxx[ 0] <= PRESS; // F1 Ctrl or L-Shift BOOT 1
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 32;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 16;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
|
||||
8'h16: KEY[28] <= PRESS_N; // 1 !
|
||||
8'h1E: KEY[25] <= PRESS_N; // 2 @
|
||||
8'h26: KEY[27] <= PRESS_N; // 3 #
|
||||
8'h25: KEY[29] <= PRESS_N; // 4 $
|
||||
8'h2E: KEY[24] <= PRESS_N; // 5 %
|
||||
8'h36: KEY[40] <= PRESS_N; // 6 ^
|
||||
8'h3D: KEY[45] <= PRESS_N; // 7 &
|
||||
// 8'h0D: KEY[?] <= PRESS_N; // TAB
|
||||
8'h3E: KEY[43] <= PRESS_N; // 8 *
|
||||
8'h46: KEY[41] <= PRESS_N; // 9 (
|
||||
8'h45: KEY[44] <= PRESS_N; // 0 )
|
||||
8'h4E: KEY[42] <= PRESS_N; // - _
|
||||
// 8'h55: KEY[?] <= PRESS_N; // = +
|
||||
8'h66: KEY_EX[8] <= PRESS_N; // backspace
|
||||
// 8'h0E: KEY[?] <= PRESS_N; // ` ~
|
||||
// 8'h5D: KEY[?] <= PRESS_N; // \ |
|
||||
8'h49: KEY[33] <= PRESS_N; // . >
|
||||
8'h4b: KEY[57] <= PRESS_N; // L
|
||||
8'h44: KEY[49] <= PRESS_N; // O
|
||||
// 8'h11 KEY[?] <= PRESS_N; // line feed (really right ALT (Extended) see below
|
||||
8'h5A: KEY[50] <= PRESS_N; // CR
|
||||
// 8'h54: KEY[?] <= PRESS_N; // [ {
|
||||
// 8'h5B: KEY[?] <= PRESS_N; // ] }
|
||||
8'h52: KEY[58] <= PRESS_N; // ' "
|
||||
8'h1D: KEY[ 1] <= PRESS_N; // W
|
||||
8'h24: KEY[ 3] <= PRESS_N; // E
|
||||
8'h2D: KEY[ 5] <= PRESS_N; // R
|
||||
8'h2C: KEY[ 0] <= PRESS_N; // T
|
||||
8'h35: KEY[48] <= PRESS_N; // Y
|
||||
8'h3C: KEY[53] <= PRESS_N; // U
|
||||
8'h43: KEY[51] <= PRESS_N; // I
|
||||
8'h1B: KEY[ 9] <= PRESS_N; // S
|
||||
8'h23: KEY[11] <= PRESS_N; // D
|
||||
8'h2B: KEY[13] <= PRESS_N; // F
|
||||
8'h34: KEY[ 8] <= PRESS_N; // G
|
||||
8'h33: KEY[56] <= PRESS_N; // H
|
||||
8'h3B: KEY[61] <= PRESS_N; // J
|
||||
8'h42: KEY[59] <= PRESS_N; // K
|
||||
8'h22: KEY[17] <= PRESS_N; // X
|
||||
8'h21: KEY[19] <= PRESS_N; // C
|
||||
8'h2a: KEY[21] <= PRESS_N; // V
|
||||
8'h32: KEY[16] <= PRESS_N; // B
|
||||
8'h31: KEY[32] <= PRESS_N; // N
|
||||
8'h3a: KEY[37] <= PRESS_N; // M
|
||||
8'h41: KEY[35] <= PRESS_N; // , <
|
||||
8'h15: KEY[ 4] <= PRESS_N; // Q
|
||||
8'h1C: KEY[12] <= PRESS_N; // A
|
||||
8'h1A: KEY[20] <= PRESS_N; // Z
|
||||
8'h29: KEY[36] <= PRESS_N; // Space
|
||||
// 8'h4A: KEY[?] <= PRESS_N; // / ?
|
||||
8'h4C: KEY[60] <= PRESS_N; // ; :
|
||||
8'h4D: KEY[52] <= PRESS_N; // P
|
||||
8'h14: KEY[10] <= PRESS_N; // Ctrl either left or right
|
||||
8'h12: KEY[18] <= PRESS_N; // L-Shift
|
||||
8'h59: KEY_EX[0] <= PRESS_N; // R-Shift
|
||||
8'h11:
|
||||
begin
|
||||
if(~EXTENDED)
|
||||
KEY_EX[1] <= PRESS_N; // Repeat really left ALT
|
||||
else
|
||||
KEY_EX[2] <= PRESS_N; // LF really right ALT
|
||||
end
|
||||
8'h76: KEY_EX[3] <= PRESS_N; // Esc
|
||||
8'h75: KEY_EX[4] <= PRESS_N; // up
|
||||
8'h6B: KEY_EX[5] <= PRESS_N; // left
|
||||
8'h74: KEY_EX[6] <= PRESS_N; // right
|
||||
8'h72: KEY_EX[7] <= PRESS_N; // down
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
always @ (posedge CLK50MHZ) // 50MHz
|
||||
KB_CLK <= KB_CLK + 1'b1; // 50/32 = 1.5625 MHz
|
||||
|
||||
ps2_keyboard KEYBOARD(
|
||||
.RESET_N(RESET_N),
|
||||
.CLK(KB_CLK[4]),
|
||||
.PS2_CLK(PS2_KBCLK),
|
||||
.PS2_DATA(PS2_KBDAT),
|
||||
.RX_SCAN(SCAN),
|
||||
.RX_PRESSED(PRESS),
|
||||
.RX_EXTENDED(EXTENDED)
|
||||
);
|
||||
|
||||
assign PRESS_N = ~PRESS;
|
||||
|
||||
|
||||
`ifdef CASS_EMU
|
||||
|
||||
wire CASS_BUF_RD;
|
||||
wire [15:0] CASS_BUF_A;
|
||||
wire CASS_BUF_WR;
|
||||
wire [7:0] CASS_BUF_DAT;
|
||||
wire [7:0] CASS_BUF_Q;
|
||||
|
||||
// F9 CASS PLAY
|
||||
// F10 CASS STOP
|
||||
|
||||
EMU_CASS_KEY EMU_CASS_KEY(
|
||||
KEY_Fxx[8],
|
||||
KEY_Fxx[9],
|
||||
// cass emu
|
||||
CASS_BUF_RD,
|
||||
//
|
||||
CASS_BUF_A,
|
||||
CASS_BUF_WR,
|
||||
CASS_BUF_DAT,
|
||||
CASS_BUF_Q,
|
||||
// Control Signals
|
||||
EMU_CASS_EN,
|
||||
EMU_CASS_DAT,
|
||||
|
||||
// key emu
|
||||
EMU_KEY,
|
||||
EMU_KEY_EX,
|
||||
EMU_KEY_EN,
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
UART_RXD,
|
||||
UART_TXD,
|
||||
|
||||
// System
|
||||
TURBO_SPEED,
|
||||
// Clock: 10MHz
|
||||
CLK10MHZ,
|
||||
RESET_N
|
||||
);
|
||||
|
||||
|
||||
`ifdef CASS_EMU_16K
|
||||
|
||||
cass_ram_16k_altera cass_buf(
|
||||
.address(CASS_BUF_A[13:0]),
|
||||
.clock(CLK10MHZ),
|
||||
.data(CASS_BUF_DI),
|
||||
.wren(CASS_BUF_WR),
|
||||
.q(CASS_BUF_Q)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
`ifdef CASS_EMU_8K
|
||||
|
||||
cass_ram_8k_altera cass_buf(
|
||||
.address(CASS_BUF_A[12:0]),
|
||||
.clock(CLK10MHZ),
|
||||
.data(CASS_BUF_DI),
|
||||
.wren(CASS_BUF_WR),
|
||||
.q(CASS_BUF_Q)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
`ifdef CASS_EMU_4K
|
||||
|
||||
cass_ram_4k_altera cass_buf(
|
||||
.address(CASS_BUF_A[11:0]),
|
||||
.clock(CLK10MHZ),
|
||||
.data(CASS_BUF_DAT),
|
||||
.wren(CASS_BUF_WR),
|
||||
.q(CASS_BUF_Q)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
`ifdef CASS_EMU_2K
|
||||
|
||||
cass_ram_2k_altera cass_buf(
|
||||
.address(CASS_BUF_A[10:0]),
|
||||
.clock(CLK10MHZ),
|
||||
.data(CASS_BUF_DAT),
|
||||
.wren(CASS_BUF_WR),
|
||||
.q(CASS_BUF_Q)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
|
||||
assign CASS_OUT = EMU_CASS_EN ? EMU_CASS_DAT : {LATCHED_IO_DATA_WR[2], 1'b0};
|
||||
|
||||
(*keep*)wire trap = (CPU_RD|CPU_WR) && (CPU_A[15:12] == 4'h0);
|
||||
|
||||
70
Computer_MiST/Laser310_MiST/rtl/VIDEO_OUT.v
Normal file
70
Computer_MiST/Laser310_MiST/rtl/VIDEO_OUT.v
Normal file
@@ -0,0 +1,70 @@
|
||||
module VIDEO_OUT
|
||||
(
|
||||
pixel_clock,
|
||||
reset,
|
||||
vga_red_data,
|
||||
vga_green_data,
|
||||
vga_blue_data,
|
||||
h_synch,
|
||||
v_synch,
|
||||
blank,
|
||||
|
||||
VGA_OUT_HSYNC,
|
||||
VGA_OUT_VSYNC,
|
||||
VGA_OUT_RED,
|
||||
VGA_OUT_GREEN,
|
||||
VGA_OUT_BLUE
|
||||
);
|
||||
|
||||
input pixel_clock;
|
||||
input reset;
|
||||
input [7:0] vga_red_data;
|
||||
input [7:0] vga_green_data;
|
||||
input [7:0] vga_blue_data;
|
||||
input h_synch;
|
||||
input v_synch;
|
||||
input blank;
|
||||
|
||||
output VGA_OUT_HSYNC;
|
||||
output VGA_OUT_VSYNC;
|
||||
output [7:0] VGA_OUT_RED;
|
||||
output [7:0] VGA_OUT_GREEN;
|
||||
output [7:0] VGA_OUT_BLUE;
|
||||
|
||||
reg VGA_OUT_HSYNC;
|
||||
reg VGA_OUT_VSYNC;
|
||||
reg [7:0] VGA_OUT_RED;
|
||||
reg [7:0] VGA_OUT_GREEN;
|
||||
reg [7:0] VGA_OUT_BLUE;
|
||||
|
||||
// make the external video connections
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
// shut down the video output during reset
|
||||
VGA_OUT_HSYNC <= 1'b1;
|
||||
VGA_OUT_VSYNC <= 1'b1;
|
||||
VGA_OUT_RED <= 8'b0;
|
||||
VGA_OUT_GREEN <= 8'b0;
|
||||
VGA_OUT_BLUE <= 8'b0;
|
||||
end
|
||||
|
||||
else if (blank) begin
|
||||
// output black during the blank signal
|
||||
VGA_OUT_HSYNC <= h_synch;
|
||||
VGA_OUT_VSYNC <= v_synch;
|
||||
VGA_OUT_RED <= 8'b0;
|
||||
VGA_OUT_GREEN <= 8'b0;
|
||||
VGA_OUT_BLUE <= 8'b0;
|
||||
end
|
||||
|
||||
else begin
|
||||
// output color data otherwise
|
||||
VGA_OUT_HSYNC <= h_synch;
|
||||
VGA_OUT_VSYNC <= v_synch;
|
||||
VGA_OUT_RED <= vga_red_data;
|
||||
VGA_OUT_GREEN <= vga_green_data;
|
||||
VGA_OUT_BLUE <= vga_blue_data;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // VIDEO_OUT
|
||||
35
Computer_MiST/Laser310_MiST/rtl/build_id.tcl
Normal file
35
Computer_MiST/Laser310_MiST/rtl/build_id.tcl
Normal file
@@ -0,0 +1,35 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
|
||||
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "rtl/build_id.v"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
# Output the Verilog source
|
||||
puts $outputFile "`define BUILD_DATE \"$buildDate\""
|
||||
puts $outputFile "`define BUILD_TIME \"$buildTime\""
|
||||
close $outputFile
|
||||
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
|
||||
post_message "Date: $buildDate"
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
48
Computer_MiST/Laser310_MiST/rtl/dac.vhd
Normal file
48
Computer_MiST/Laser310_MiST/rtl/dac.vhd
Normal file
@@ -0,0 +1,48 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Delta-Sigma DAC
|
||||
--
|
||||
-- Refer to Xilinx Application Note XAPP154.
|
||||
--
|
||||
-- This DAC requires an external RC low-pass filter:
|
||||
--
|
||||
-- dac_o 0---XXXXX---+---0 analog audio
|
||||
-- 3k3 |
|
||||
-- === 4n7
|
||||
-- |
|
||||
-- GND
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity dac is
|
||||
generic (
|
||||
C_bits : integer := 12
|
||||
);
|
||||
port (
|
||||
clk_i : in std_logic;
|
||||
res_n_i : in std_logic;
|
||||
dac_i : in std_logic_vector(C_bits-1 downto 0);
|
||||
dac_o : out std_logic
|
||||
);
|
||||
end dac;
|
||||
|
||||
architecture rtl of dac is
|
||||
signal sig_in: unsigned(C_bits downto 0);
|
||||
begin
|
||||
seq: process(clk_i, res_n_i)
|
||||
begin
|
||||
if res_n_i = '0' then
|
||||
sig_in <= to_unsigned(2**C_bits, sig_in'length);
|
||||
dac_o <= '0';
|
||||
elsif rising_edge(clk_i) then
|
||||
-- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
|
||||
--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
|
||||
sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
|
||||
dac_o <= sig_in(C_bits);
|
||||
end if;
|
||||
end process seq;
|
||||
end rtl;
|
||||
58
Computer_MiST/Laser310_MiST/rtl/dpram.vhd
Normal file
58
Computer_MiST/Laser310_MiST/rtl/dpram.vhd
Normal file
@@ -0,0 +1,58 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity dpram is
|
||||
|
||||
generic (
|
||||
addr_width_g : integer := 8;
|
||||
data_width_g : integer := 8
|
||||
);
|
||||
port (
|
||||
clk_a_i : in std_logic;
|
||||
en_a_i : in std_logic;
|
||||
we_i : in std_logic;
|
||||
addr_a_i : in std_logic_vector(addr_width_g-1 downto 0);
|
||||
data_a_i : in std_logic_vector(data_width_g-1 downto 0);
|
||||
data_a_o : out std_logic_vector(data_width_g-1 downto 0);
|
||||
clk_b_i : in std_logic;
|
||||
addr_b_i : in std_logic_vector(addr_width_g-1 downto 0);
|
||||
data_b_o : out std_logic_vector(data_width_g-1 downto 0)
|
||||
);
|
||||
|
||||
end dpram;
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
architecture rtl of dpram is
|
||||
|
||||
type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0);
|
||||
signal ram_q : ram_t;
|
||||
|
||||
begin
|
||||
|
||||
mem_a: process (clk_a_i)
|
||||
begin
|
||||
if rising_edge(clk_a_i) then
|
||||
if we_i = '1' and en_a_i = '1' then
|
||||
ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i;
|
||||
data_a_o <= data_a_i;
|
||||
else
|
||||
data_a_o <= ram_q(to_integer(unsigned(addr_a_i)));
|
||||
end if;
|
||||
end if;
|
||||
end process mem_a;
|
||||
|
||||
mem_b: process (clk_b_i)
|
||||
begin
|
||||
if rising_edge(clk_b_i) then
|
||||
data_b_o <= ram_q(to_integer(unsigned(addr_b_i)));
|
||||
end if;
|
||||
end process mem_b;
|
||||
|
||||
end rtl;
|
||||
199
Computer_MiST/Laser310_MiST/rtl/mc6847_vga.v
Normal file
199
Computer_MiST/Laser310_MiST/rtl/mc6847_vga.v
Normal file
@@ -0,0 +1,199 @@
|
||||
// LASER310 VZ200
|
||||
// mc6847
|
||||
|
||||
module MC6847_VGA(
|
||||
PIX_CLK,
|
||||
RESET_N,
|
||||
|
||||
RD,
|
||||
DD,
|
||||
DA,
|
||||
|
||||
AG,
|
||||
AS,
|
||||
EXT,
|
||||
INV,
|
||||
GM,
|
||||
CSS,
|
||||
|
||||
// vga
|
||||
blank,
|
||||
VGA_OUT_HSYNC,
|
||||
VGA_OUT_VSYNC,
|
||||
VGA_OUT_RED,
|
||||
VGA_OUT_GREEN,
|
||||
VGA_OUT_BLUE
|
||||
);
|
||||
|
||||
input PIX_CLK;
|
||||
input RESET_N;
|
||||
|
||||
output wire RD;
|
||||
output wire [12:0] DA; // 8KB
|
||||
input [7:0] DD;
|
||||
input AG;
|
||||
input AS;
|
||||
input EXT;
|
||||
input INV;
|
||||
input CSS;
|
||||
input [2:0] GM;
|
||||
output wire blank;
|
||||
output wire VGA_OUT_HSYNC;
|
||||
output wire VGA_OUT_VSYNC;
|
||||
output wire [7:0] VGA_OUT_RED;
|
||||
output wire [7:0] VGA_OUT_GREEN;
|
||||
output wire [7:0] VGA_OUT_BLUE;
|
||||
|
||||
|
||||
reg LATCHED_AG;
|
||||
reg LATCHED_AS;
|
||||
reg LATCHED_EXT;
|
||||
reg LATCHED_INV;
|
||||
reg [2:0] LATCHED_GM;
|
||||
reg LATCHED_CSS;
|
||||
|
||||
wire pixel_clock; // generated from SYSTEM CLOCK
|
||||
wire reset; // reset asserted when DCMs are NOT LOCKED
|
||||
|
||||
wire [7:0] vga_red; // red video data
|
||||
wire [7:0] vga_green; // green video data
|
||||
wire [7:0] vga_blue; // blue video data
|
||||
|
||||
// internal video timing signals
|
||||
wire h_synch; // horizontal synch for VGA connector
|
||||
wire v_synch; // vertical synch for VGA connector
|
||||
//wire blank; // composite blanking
|
||||
wire [10:0] pixel_count; // bit mapped pixel position within the line
|
||||
wire [9:0] line_count; // bit mapped line number in a frame lines within the frame
|
||||
|
||||
wire show_border;
|
||||
|
||||
// text
|
||||
wire [3:0] subchar_pixel; // pixel position within the character
|
||||
wire [4:0] subchar_line; // identifies the line number within a character block
|
||||
wire [6:0] char_column; // character number on the current line
|
||||
wire [6:0] char_line; // line number on the screen
|
||||
|
||||
// graph
|
||||
wire [8:0] graph_pixel; // pixel number on the current line
|
||||
wire [9:0] graph_line_2x; // line number on the screen
|
||||
wire [9:0] graph_line_3x; // line number on the screen
|
||||
|
||||
/*
|
||||
wire [11:0] ROM_ADDRESS;
|
||||
wire [7:0] ROM_DATA;
|
||||
*/
|
||||
|
||||
assign reset = ~RESET_N;
|
||||
assign pixel_clock = PIX_CLK;
|
||||
|
||||
//assign vga_red = 8'hff;
|
||||
//assign vga_green = 8'h7f;
|
||||
//assign vga_blue = 8'h7f;
|
||||
|
||||
// Character generator
|
||||
/*
|
||||
char_rom_4k_altera char_rom(
|
||||
.address(ROM_ADDRESS),
|
||||
.clock(pixel_clock),
|
||||
.q(ROM_DATA)
|
||||
);
|
||||
*/
|
||||
|
||||
// 为了防止闪屏，再垂直回扫信号产生时，锁存模式信号。
|
||||
|
||||
always @ (posedge v_synch or negedge RESET_N)
|
||||
begin
|
||||
if(!RESET_N)
|
||||
begin
|
||||
LATCHED_AG <= 1'b0;
|
||||
LATCHED_AS <= 1'b0;
|
||||
LATCHED_EXT <= 1'b0;
|
||||
LATCHED_INV <= 1'b0;
|
||||
LATCHED_GM <= 3'b0;
|
||||
LATCHED_CSS <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
LATCHED_AG <= AG;
|
||||
LATCHED_AS <= AS;
|
||||
LATCHED_EXT <= EXT;
|
||||
LATCHED_INV <= INV;
|
||||
LATCHED_GM <= GM;
|
||||
LATCHED_CSS <= CSS;
|
||||
end
|
||||
end
|
||||
|
||||
// instantiate the character generator
|
||||
PIXEL_DISPLAY PIXEL_DISPLAY(
|
||||
.pixel_clock(pixel_clock),
|
||||
.reset(reset),
|
||||
.show_border(show_border),
|
||||
// mode
|
||||
.ag(LATCHED_AG),
|
||||
.gm(LATCHED_GM),
|
||||
.css(LATCHED_CSS),
|
||||
// text
|
||||
.char_column(char_column),
|
||||
.char_line(char_line),
|
||||
.subchar_line(subchar_line),
|
||||
.subchar_pixel(subchar_pixel),
|
||||
// graph
|
||||
.graph_pixel(graph_pixel),
|
||||
.graph_line_2x(graph_line_2x),
|
||||
.graph_line_3x(graph_line_3x),
|
||||
// vram
|
||||
.vram_rd_enable(RD),
|
||||
.vram_addr(DA),
|
||||
.vram_data(DD),
|
||||
// vga
|
||||
.vga_red(vga_red),
|
||||
.vga_green(vga_green),
|
||||
.vga_blue(vga_blue)
|
||||
);
|
||||
|
||||
// instantiate the video timing generator
|
||||
SVGA_TIMING_GENERATION SVGA_TIMING_GENERATION
|
||||
(
|
||||
pixel_clock,
|
||||
reset,
|
||||
h_synch,
|
||||
v_synch,
|
||||
blank,
|
||||
pixel_count,
|
||||
line_count,
|
||||
|
||||
show_border,
|
||||
|
||||
// text
|
||||
subchar_pixel,
|
||||
subchar_line,
|
||||
char_column,
|
||||
char_line,
|
||||
|
||||
// graph
|
||||
graph_pixel,
|
||||
graph_line_2x,
|
||||
graph_line_3x
|
||||
);
|
||||
|
||||
// instantiate the video output mux
|
||||
VIDEO_OUT VIDEO_OUT
|
||||
(
|
||||
pixel_clock,
|
||||
reset,
|
||||
vga_red,
|
||||
vga_green,
|
||||
vga_blue,
|
||||
h_synch,
|
||||
v_synch,
|
||||
blank,
|
||||
|
||||
VGA_OUT_HSYNC,
|
||||
VGA_OUT_VSYNC,
|
||||
VGA_OUT_RED,
|
||||
VGA_OUT_GREEN,
|
||||
VGA_OUT_BLUE
|
||||
);
|
||||
|
||||
endmodule
|
||||
4
Computer_MiST/Laser310_MiST/rtl/pll.qip
Normal file
4
Computer_MiST/Laser310_MiST/rtl/pll.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
|
||||
451
Computer_MiST/Laser310_MiST/rtl/pll.vhd
Normal file
451
Computer_MiST/Laser310_MiST/rtl/pll.vhd
Normal file
@@ -0,0 +1,451 @@
|
||||
-- megafunction wizard: %ALTPLL%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: pll.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altpll
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2014 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY pll IS
|
||||
PORT
|
||||
(
|
||||
areset : IN STD_LOGIC := '0';
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
c2 : OUT STD_LOGIC ;
|
||||
c3 : OUT STD_LOGIC
|
||||
);
|
||||
END pll;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF pll IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC ;
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC ;
|
||||
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altpll
|
||||
GENERIC (
|
||||
bandwidth_type : STRING;
|
||||
clk0_divide_by : NATURAL;
|
||||
clk0_duty_cycle : NATURAL;
|
||||
clk0_multiply_by : NATURAL;
|
||||
clk0_phase_shift : STRING;
|
||||
clk1_divide_by : NATURAL;
|
||||
clk1_duty_cycle : NATURAL;
|
||||
clk1_multiply_by : NATURAL;
|
||||
clk1_phase_shift : STRING;
|
||||
clk2_divide_by : NATURAL;
|
||||
clk2_duty_cycle : NATURAL;
|
||||
clk2_multiply_by : NATURAL;
|
||||
clk2_phase_shift : STRING;
|
||||
clk3_divide_by : NATURAL;
|
||||
clk3_duty_cycle : NATURAL;
|
||||
clk3_multiply_by : NATURAL;
|
||||
clk3_phase_shift : STRING;
|
||||
compensate_clock : STRING;
|
||||
inclk0_input_frequency : NATURAL;
|
||||
intended_device_family : STRING;
|
||||
lpm_hint : STRING;
|
||||
lpm_type : STRING;
|
||||
operation_mode : STRING;
|
||||
pll_type : STRING;
|
||||
port_activeclock : STRING;
|
||||
port_areset : STRING;
|
||||
port_clkbad0 : STRING;
|
||||
port_clkbad1 : STRING;
|
||||
port_clkloss : STRING;
|
||||
port_clkswitch : STRING;
|
||||
port_configupdate : STRING;
|
||||
port_fbin : STRING;
|
||||
port_inclk0 : STRING;
|
||||
port_inclk1 : STRING;
|
||||
port_locked : STRING;
|
||||
port_pfdena : STRING;
|
||||
port_phasecounterselect : STRING;
|
||||
port_phasedone : STRING;
|
||||
port_phasestep : STRING;
|
||||
port_phaseupdown : STRING;
|
||||
port_pllena : STRING;
|
||||
port_scanaclr : STRING;
|
||||
port_scanclk : STRING;
|
||||
port_scanclkena : STRING;
|
||||
port_scandata : STRING;
|
||||
port_scandataout : STRING;
|
||||
port_scandone : STRING;
|
||||
port_scanread : STRING;
|
||||
port_scanwrite : STRING;
|
||||
port_clk0 : STRING;
|
||||
port_clk1 : STRING;
|
||||
port_clk2 : STRING;
|
||||
port_clk3 : STRING;
|
||||
port_clk4 : STRING;
|
||||
port_clk5 : STRING;
|
||||
port_clkena0 : STRING;
|
||||
port_clkena1 : STRING;
|
||||
port_clkena2 : STRING;
|
||||
port_clkena3 : STRING;
|
||||
port_clkena4 : STRING;
|
||||
port_clkena5 : STRING;
|
||||
port_extclk0 : STRING;
|
||||
port_extclk1 : STRING;
|
||||
port_extclk2 : STRING;
|
||||
port_extclk3 : STRING;
|
||||
width_clock : NATURAL
|
||||
);
|
||||
PORT (
|
||||
areset : IN STD_LOGIC ;
|
||||
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire7_bv(0 DOWNTO 0) <= "0";
|
||||
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
|
||||
sub_wire4 <= sub_wire0(2);
|
||||
sub_wire3 <= sub_wire0(0);
|
||||
sub_wire2 <= sub_wire0(3);
|
||||
sub_wire1 <= sub_wire0(1);
|
||||
c1 <= sub_wire1;
|
||||
c3 <= sub_wire2;
|
||||
c0 <= sub_wire3;
|
||||
c2 <= sub_wire4;
|
||||
sub_wire5 <= inclk0;
|
||||
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
|
||||
|
||||
altpll_component : altpll
|
||||
GENERIC MAP (
|
||||
bandwidth_type => "AUTO",
|
||||
clk0_divide_by => 27,
|
||||
clk0_duty_cycle => 50,
|
||||
clk0_multiply_by => 50,
|
||||
clk0_phase_shift => "0",
|
||||
clk1_divide_by => 27,
|
||||
clk1_duty_cycle => 50,
|
||||
clk1_multiply_by => 25,
|
||||
clk1_phase_shift => "0",
|
||||
clk2_divide_by => 27,
|
||||
clk2_duty_cycle => 50,
|
||||
clk2_multiply_by => 10,
|
||||
clk2_phase_shift => "0",
|
||||
clk3_divide_by => 108,
|
||||
clk3_duty_cycle => 50,
|
||||
clk3_multiply_by => 25,
|
||||
clk3_phase_shift => "0",
|
||||
compensate_clock => "CLK0",
|
||||
inclk0_input_frequency => 37037,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_hint => "CBX_MODULE_PREFIX=pll",
|
||||
lpm_type => "altpll",
|
||||
operation_mode => "NORMAL",
|
||||
pll_type => "AUTO",
|
||||
port_activeclock => "PORT_UNUSED",
|
||||
port_areset => "PORT_USED",
|
||||
port_clkbad0 => "PORT_UNUSED",
|
||||
port_clkbad1 => "PORT_UNUSED",
|
||||
port_clkloss => "PORT_UNUSED",
|
||||
port_clkswitch => "PORT_UNUSED",
|
||||
port_configupdate => "PORT_UNUSED",
|
||||
port_fbin => "PORT_UNUSED",
|
||||
port_inclk0 => "PORT_USED",
|
||||
port_inclk1 => "PORT_UNUSED",
|
||||
port_locked => "PORT_UNUSED",
|
||||
port_pfdena => "PORT_UNUSED",
|
||||
port_phasecounterselect => "PORT_UNUSED",
|
||||
port_phasedone => "PORT_UNUSED",
|
||||
port_phasestep => "PORT_UNUSED",
|
||||
port_phaseupdown => "PORT_UNUSED",
|
||||
port_pllena => "PORT_UNUSED",
|
||||
port_scanaclr => "PORT_UNUSED",
|
||||
port_scanclk => "PORT_UNUSED",
|
||||
port_scanclkena => "PORT_UNUSED",
|
||||
port_scandata => "PORT_UNUSED",
|
||||
port_scandataout => "PORT_UNUSED",
|
||||
port_scandone => "PORT_UNUSED",
|
||||
port_scanread => "PORT_UNUSED",
|
||||
port_scanwrite => "PORT_UNUSED",
|
||||
port_clk0 => "PORT_USED",
|
||||
port_clk1 => "PORT_USED",
|
||||
port_clk2 => "PORT_USED",
|
||||
port_clk3 => "PORT_USED",
|
||||
port_clk4 => "PORT_UNUSED",
|
||||
port_clk5 => "PORT_UNUSED",
|
||||
port_clkena0 => "PORT_UNUSED",
|
||||
port_clkena1 => "PORT_UNUSED",
|
||||
port_clkena2 => "PORT_UNUSED",
|
||||
port_clkena3 => "PORT_UNUSED",
|
||||
port_clkena4 => "PORT_UNUSED",
|
||||
port_clkena5 => "PORT_UNUSED",
|
||||
port_extclk0 => "PORT_UNUSED",
|
||||
port_extclk1 => "PORT_UNUSED",
|
||||
port_extclk2 => "PORT_UNUSED",
|
||||
port_extclk3 => "PORT_UNUSED",
|
||||
width_clock => 5
|
||||
)
|
||||
PORT MAP (
|
||||
areset => areset,
|
||||
inclk => sub_wire6,
|
||||
clk => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "27"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "108"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "10.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.250000"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "50"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "10"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "25"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "10.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.25000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||||
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
|
||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
|
||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27"
|
||||
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "10"
|
||||
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "108"
|
||||
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "25"
|
||||
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
227
Computer_MiST/Laser310_MiST/rtl/ps2_keyboard_glb.v
Normal file
227
Computer_MiST/Laser310_MiST/rtl/ps2_keyboard_glb.v
Normal file
@@ -0,0 +1,227 @@
|
||||
/*****************************************************************************
|
||||
* gbfpgaapple APPLE ][e core.
|
||||
*
|
||||
*
|
||||
* Ver 1.0
|
||||
* July 2006
|
||||
* Latest version from gbfpgaapple.tripod.com
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* CPU section copyrighted by Daniel Wallner
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* Apple ][e compatible system on a chip
|
||||
*
|
||||
* Version : 1.0
|
||||
*
|
||||
* Copyright (c) 2006 Gary Becker (gary_l_becker@yahoo.com)
|
||||
*
|
||||
* All rights reserved
|
||||
*
|
||||
* Redistribution and use in source and synthezised forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in synthesized form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of the author nor the names of other contributors may
|
||||
* be used to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Please report bugs to the author, but before you do so, please
|
||||
* make sure that this is not a derivative work and that
|
||||
* you have the latest version of this file.
|
||||
*
|
||||
* The latest version of this file can be found at:
|
||||
* http://gbfpgaapple.tripod.com
|
||||
*******************************************************************************/
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module ps2_keyboard (
|
||||
CLK,
|
||||
RESET_N,
|
||||
PS2_CLK,
|
||||
PS2_DATA,
|
||||
RX_PRESSED,
|
||||
RX_EXTENDED,
|
||||
RX_SCAN
|
||||
);
|
||||
|
||||
input CLK;
|
||||
input RESET_N;
|
||||
input PS2_CLK;
|
||||
input PS2_DATA;
|
||||
output RX_PRESSED;
|
||||
reg RX_PRESSED;
|
||||
output RX_EXTENDED;
|
||||
reg RX_EXTENDED;
|
||||
output [7:0] RX_SCAN;
|
||||
reg [7:0] RX_SCAN;
|
||||
|
||||
reg KB_CLK;
|
||||
reg KB_DATA;
|
||||
reg KB_CLK_B;
|
||||
reg KB_DATA_B;
|
||||
reg PRESSED_N;
|
||||
reg EXTENDED;
|
||||
reg [2:0] BIT;
|
||||
reg [7:0] STATE;
|
||||
reg [7:0] SCAN;
|
||||
wire PARITY;
|
||||
reg [10:0] TIMER;
|
||||
reg KILLER;
|
||||
wire RESET_X;
|
||||
|
||||
// Double buffer
|
||||
always @ (posedge CLK)
|
||||
begin
|
||||
KB_CLK_B <= PS2_CLK;
|
||||
KB_DATA_B <= PS2_DATA;
|
||||
KB_CLK <= KB_CLK_B;
|
||||
KB_DATA <= KB_DATA_B;
|
||||
end
|
||||
assign PARITY = ~(((SCAN[0]^SCAN[1])
|
||||
^(SCAN[2]^SCAN[3]))
|
||||
^((SCAN[4]^SCAN[5])
|
||||
^(SCAN[6]^SCAN[7])));
|
||||
|
||||
assign RESET_X = RESET_N & KILLER;
|
||||
always @ (negedge CLK or negedge RESET_N)
|
||||
if(!RESET_N)
|
||||
begin
|
||||
KILLER <= 1'b1;
|
||||
TIMER <= 11'h000;
|
||||
end
|
||||
else
|
||||
case(TIMER)
|
||||
11'h000:
|
||||
begin
|
||||
KILLER <= 1'b1;
|
||||
if(STATE != 8'h00)
|
||||
TIMER <= 11'h001;
|
||||
end
|
||||
11'h7FD:
|
||||
begin
|
||||
KILLER <= 1'b0;
|
||||
TIMER <= 11'h7FE;
|
||||
end
|
||||
default:
|
||||
if(STATE == 8'h00)
|
||||
TIMER <= 11'h000;
|
||||
else
|
||||
TIMER <= TIMER + 1'b1;
|
||||
endcase
|
||||
|
||||
always @ (posedge CLK or negedge RESET_X)
|
||||
begin
|
||||
if(!RESET_X)
|
||||
begin
|
||||
STATE <= 8'h00;
|
||||
SCAN <= 8'h00;
|
||||
BIT <= 3'b000;
|
||||
RX_SCAN <= 8'h00;
|
||||
RX_PRESSED <= 1'b0;
|
||||
PRESSED_N <= 1'b0;
|
||||
EXTENDED <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
|
||||
case (STATE)
|
||||
8'h00: // Hunt for start bit
|
||||
begin
|
||||
SCAN <= 8'h00;
|
||||
BIT <= 3'b000;
|
||||
RX_SCAN <= 8'h00;
|
||||
RX_PRESSED <= 1'b0;
|
||||
if(~KB_DATA & ~KB_CLK)
|
||||
STATE <= 8'h01;
|
||||
end
|
||||
8'h01: // Started
|
||||
begin
|
||||
if(KB_CLK)
|
||||
STATE <= 8'h02;
|
||||
end
|
||||
8'h02: // Hunt for Bit
|
||||
begin
|
||||
if(~KB_CLK)
|
||||
STATE <= 8'h03;
|
||||
end
|
||||
8'h03:
|
||||
begin
|
||||
if(KB_CLK)
|
||||
begin
|
||||
SCAN[BIT] <= KB_DATA;
|
||||
BIT <= BIT + 1'b1;
|
||||
if(BIT == 3'b111)
|
||||
STATE <= 8'h04;
|
||||
else
|
||||
STATE <= 8'h02;
|
||||
end
|
||||
end
|
||||
8'h04: // Hunt for Bit
|
||||
begin
|
||||
if(~KB_CLK)
|
||||
STATE <= 8'h05;
|
||||
end
|
||||
8'h05: // Test parity
|
||||
begin
|
||||
if(KB_CLK)
|
||||
begin
|
||||
if(KB_DATA == PARITY)
|
||||
STATE <= 8'h06;
|
||||
else
|
||||
begin
|
||||
STATE <= 8'h00;
|
||||
end
|
||||
end
|
||||
end
|
||||
8'h06:
|
||||
begin
|
||||
if(SCAN == 8'hE0)
|
||||
begin
|
||||
EXTENDED <= 1'b1;
|
||||
STATE <= 8'h00;
|
||||
end
|
||||
else
|
||||
if(SCAN == 8'hF0)
|
||||
begin
|
||||
PRESSED_N <= 1'b1;
|
||||
STATE <= 8'h00;
|
||||
end
|
||||
else
|
||||
begin
|
||||
RX_SCAN <= SCAN;
|
||||
RX_PRESSED <= ~PRESSED_N;
|
||||
RX_EXTENDED <= EXTENDED;
|
||||
PRESSED_N <= 1'b0;
|
||||
EXTENDED <= 1'b0;
|
||||
STATE <= 8'h07;
|
||||
end
|
||||
end
|
||||
8'h07:
|
||||
STATE <= 8'h00;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
59
Computer_MiST/Laser310_MiST/rtl/reset_de.v
Normal file
59
Computer_MiST/Laser310_MiST/rtl/reset_de.v
Normal file
@@ -0,0 +1,59 @@
|
||||
module RESET_DE(
|
||||
CLK, // 50MHz
|
||||
SYS_RESET_N,
|
||||
RESET_N, // 50MHz/32/65536
|
||||
RESET_AHEAD_N // 提前恢复，可以接 FLASH_RESET_N
|
||||
);
|
||||
|
||||
|
||||
input CLK;
|
||||
input SYS_RESET_N;
|
||||
output RESET_N;
|
||||
output RESET_AHEAD_N;
|
||||
|
||||
|
||||
wire RESET_N;
|
||||
wire RESET_AHEAD_N;
|
||||
|
||||
reg [5:0] CLK_CNT;
|
||||
reg [16:0] RESET_COUNT;
|
||||
|
||||
wire RESET_COUNT_CLK;
|
||||
wire RESET_DE_N;
|
||||
wire RESET_AHEAD_DE_N;
|
||||
|
||||
assign RESET_COUNT_CLK = CLK_CNT[5];
|
||||
|
||||
assign RESET_DE_N = RESET_COUNT[16]!=1'b0;
|
||||
assign RESET_N = SYS_RESET_N && RESET_DE_N;
|
||||
|
||||
assign RESET_AHEAD_DE_N = RESET_COUNT[16:15]!=2'b00;
|
||||
assign RESET_AHEAD_N = SYS_RESET_N && RESET_AHEAD_DE_N;
|
||||
|
||||
`ifdef SIMULATE
|
||||
initial
|
||||
begin
|
||||
CLK_CNT = 6'b0;
|
||||
end
|
||||
`endif
|
||||
|
||||
// 50MHz/32 = 1.5625MHz
|
||||
always @ (posedge CLK)
|
||||
CLK_CNT <= CLK_CNT+1;
|
||||
|
||||
// 50MHz/32/65536 = 23.84HZ
|
||||
always @ (posedge RESET_COUNT_CLK or negedge SYS_RESET_N)
|
||||
begin
|
||||
if(~SYS_RESET_N)
|
||||
begin
|
||||
RESET_COUNT <= 17'h00000;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if(RESET_COUNT!=17'h10000)
|
||||
RESET_COUNT <= RESET_COUNT+1;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
122
Computer_MiST/Laser310_MiST/rtl/roms/boot_rom_6000.mif
Normal file
122
Computer_MiST/Laser310_MiST/rtl/roms/boot_rom_6000.mif
Normal file
@@ -0,0 +1,122 @@
|
||||
DEPTH = 115;
|
||||
WIDTH = 8;
|
||||
ADDRESS_RADIX = HEX;
|
||||
DATA_RADIX = HEX;
|
||||
CONTENT
|
||||
BEGIN
|
||||
0000:AA;
|
||||
0001:55;
|
||||
0002:E7;
|
||||
0003:18;
|
||||
0004:AF;
|
||||
0005:2A;
|
||||
0006:00;
|
||||
0007:C0;
|
||||
0008:11;
|
||||
0009:00;
|
||||
000A:80;
|
||||
000B:ED;
|
||||
000C:52;
|
||||
000D:30;
|
||||
000E:63;
|
||||
000F:3A;
|
||||
0010:02;
|
||||
0011:C0;
|
||||
0012:FE;
|
||||
0013:56;
|
||||
0014:20;
|
||||
0015:18;
|
||||
0016:3A;
|
||||
0017:03;
|
||||
0018:C0;
|
||||
0019:FE;
|
||||
001A:5A;
|
||||
001B:20;
|
||||
001C:55;
|
||||
001D:3A;
|
||||
001E:04;
|
||||
001F:C0;
|
||||
0020:FE;
|
||||
0021:46;
|
||||
0022:20;
|
||||
0023:4E;
|
||||
0024:3A;
|
||||
0025:05;
|
||||
0026:C0;
|
||||
0027:FE;
|
||||
0028:20;
|
||||
0029:20;
|
||||
002A:47;
|
||||
002B:C3;
|
||||
002C:B7;
|
||||
002D:17;
|
||||
002E:FE;
|
||||
002F:20;
|
||||
0030:20;
|
||||
0031:40;
|
||||
0032:3A;
|
||||
0033:03;
|
||||
0034:C0;
|
||||
0035:FE;
|
||||
0036:20;
|
||||
0037:20;
|
||||
0038:39;
|
||||
0039:3A;
|
||||
003A:04;
|
||||
003B:C0;
|
||||
003C:FE;
|
||||
003D:00;
|
||||
003E:20;
|
||||
003F:32;
|
||||
0040:3A;
|
||||
0041:05;
|
||||
0042:C0;
|
||||
0043:FE;
|
||||
0044:00;
|
||||
0045:20;
|
||||
0046:2B;
|
||||
0047:3A;
|
||||
0048:17;
|
||||
0049:C0;
|
||||
004A:FE;
|
||||
004B:F0;
|
||||
004C:28;
|
||||
004D:07;
|
||||
004E:3A;
|
||||
004F:17;
|
||||
0050:C0;
|
||||
0051:FE;
|
||||
0052:F1;
|
||||
0053:20;
|
||||
0054:1D;
|
||||
0055:AF;
|
||||
0056:2A;
|
||||
0057:00;
|
||||
0058:C0;
|
||||
0059:11;
|
||||
005A:18;
|
||||
005B:00;
|
||||
005C:ED;
|
||||
005D:52;
|
||||
005E:44;
|
||||
005F:4D;
|
||||
0060:21;
|
||||
0061:1A;
|
||||
0062:C0;
|
||||
0063:ED;
|
||||
0064:5B;
|
||||
0065:18;
|
||||
0066:C0;
|
||||
0067:ED;
|
||||
0068:B0;
|
||||
0069:AF;
|
||||
006A:3E;
|
||||
006B:00;
|
||||
006C:D3;
|
||||
006D:70;
|
||||
006E:2A;
|
||||
006F:18;
|
||||
0070:C0;
|
||||
0071:E9;
|
||||
0072:76;
|
||||
END;
|
||||
1313
Computer_MiST/Laser310_MiST/rtl/roms/cass_ram.mif
Normal file
1313
Computer_MiST/Laser310_MiST/rtl/roms/cass_ram.mif
Normal file
File diff suppressed because it is too large
Load Diff
3079
Computer_MiST/Laser310_MiST/rtl/roms/charrom.mif
Normal file
3079
Computer_MiST/Laser310_MiST/rtl/roms/charrom.mif
Normal file
File diff suppressed because it is too large
Load Diff
4103
Computer_MiST/Laser310_MiST/rtl/roms/charrom_4k.mif
Normal file
4103
Computer_MiST/Laser310_MiST/rtl/roms/charrom_4k.mif
Normal file
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user