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47 lines
1.7 KiB
VHDL
47 lines
1.7 KiB
VHDL
{\rtf1\ansi\deff0\nouicompat{\fonttbl{\f0\fnil\fcharset0 Calibri;}}
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{\*\generator Riched20 10.0.17134}\viewkind4\uc1
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\pard\sa200\sl276\slmult1\f0\fs22\lang7 library ieee;\par
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\tab use ieee.std_logic_1164.all;\par
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\tab use ieee.numeric_std.all;\par
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\par
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-------------------------------------------------------------------------------\par
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-- 74xx138\par
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-- 3-to-8 line decoder\par
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-------------------------------------------------------------------------------\par
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entity LOGIC_74XX138 is\par
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\tab port (\par
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\tab\tab I_G1 : in std_logic;\par
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\tab\tab I_G2a : in std_logic;\par
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\tab\tab I_G2b : in std_logic;\par
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\tab\tab I_Sel : in std_logic_vector(2 downto 0);\par
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\tab\tab O_Q : out std_logic_vector(7 downto 0)\par
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\tab );\par
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end logic_74xx138;\par
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\par
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architecture RTL of LOGIC_74XX138 is\par
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\tab signal I_G : std_logic_vector(2 downto 0) := (others => '0');\par
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\par
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begin\par
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\tab I_G <= I_G1 & I_G2a & I_G2b;\par
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\par
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\tab xx138 : process(I_G, I_Sel)\par
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\tab begin\par
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\tab\tab if(I_G = "100" ) then\par
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\tab\tab\tab case I_Sel is\par
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\tab\tab\tab\tab when "000" => O_Q <= "11111110";\par
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\tab\tab\tab\tab when "001" => O_Q <= "11111101";\par
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\tab\tab\tab\tab when "010" => O_Q <= "11111011";\par
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\tab\tab\tab\tab when "011" => O_Q <= "11110111";\par
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\tab\tab\tab\tab when "100" => O_Q <= "11101111";\par
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\tab\tab\tab\tab when "101" => O_Q <= "11011111";\par
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\tab\tab\tab\tab when "110" => O_Q <= "10111111";\par
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\tab\tab\tab\tab when "111" => O_Q <= "01111111";\par
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\tab\tab\tab\tab when others => null;\par
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\tab\tab\tab end case;\par
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\tab\tab else\par
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\tab\tab\tab\tab O_Q <= (others => '1');\par
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\tab\tab end if;\par
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\tab end process;\par
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end RTL;\par
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}
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