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44 lines
869 B
VHDL
44 lines
869 B
VHDL
-- 74161 counter - extended to 8 bits
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-- code found on the internet
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-- adjustments made for 8 bit counter structure
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library IEEE;
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use IEEE.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity v74161 is
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port ( CLK, CLRN, LDN, ENP, ENT: in STD_LOGIC :='0';
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D: in UNSIGNED (7 downto 0) := "00000000";
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Q: out UNSIGNED (7 downto 0):= "00000000";
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RCO: out STD_LOGIC :='0');
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end v74161;
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architecture V74x161_arch of v74161 is
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signal IQ: UNSIGNED (7 downto 0) := "00000000";
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signal IRCO: STD_LOGIC := '0';
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begin
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process (CLK, CLRN, IQ, ENT)
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begin
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if CLRN='0' then IQ <= "00000000";
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elsif rising_edge(CLK) then
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if LDN='0' then IQ <= D;
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elsif (ENT and ENP)='1' then IQ <= IQ + 1;
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end if;
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end if;
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--if (IQ=15) and (ENT='1') then IRCO <= '1';
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if (IQ=255) and (ENT='1') then IRCO <= '1';
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else IRCO <= '0';
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end if;
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end process;
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Q <= IQ;
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RCO <= IRCO;
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end V74x161_arch;
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