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80 lines
1.5 KiB
Verilog
80 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 00:04:28 04/24/2014
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// Design Name:
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// Module Name: Random
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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/*module Random(input Clk,req,output reg [7:0] Num);
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reg [7:0] Position;
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initial Position = 8'b00000000;
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always@(posedge Clk)
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begin
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Position[0] <= Position[7] ^ Position[5];
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end
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always@(posedge req)
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begin
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Num <= Position;
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end
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endmodule*/
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module LFSR (
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input clock,
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input reset,
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output [12:0] rnd
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);
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wire feedback = random[12] ^ random[3] ^ random[2] ^ random[0];
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reg [12:0] random, random_next, random_done;
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reg [3:0] count, count_next; //to keep track of the shifts
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always @ (posedge clock or posedge reset)
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begin
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if (reset)
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begin
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random <= 13'hF; //An LFSR cannot have an all 0 state, thus reset to FF
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count <= 0;
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end
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else
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begin
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random <= random_next;
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count <= count_next;
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end
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end
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always @ (*)
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begin
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random_next = random; //default state stays the same
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count_next = count;
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random_next = {random[11:0], feedback}; //shift left the xor'd every posedge clock
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count_next = count + 1;
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if (count == 13)
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begin
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count = 0;
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random_done = random; //assign the random number to output after 13 shifts
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end
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end
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assign rnd = random_done;
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endmodule |