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38 lines
965 B
Verilog
38 lines
965 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 20:36:33 04/27/2014
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// Design Name:
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// Module Name: Sound
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Sound(
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input clk,input [15:0] PipesPosition1,input [15:0] PipesPosition2,
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output reg speaker
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);
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reg [25:0] clkdivider;
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//parameter clkdivider = 25000000/440/2;
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always @ (PipesPosition1 or PipesPosition2)
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if (PipesPosition1 < 10 || PipesPosition2 < 10) clkdivider <= 25000000/440/2;
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else clkdivider <= 2;
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reg [14:0] counter;
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always @(posedge clk) if(counter==0) counter <= clkdivider-1; else counter <= counter-1;
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always @(posedge clk) if(counter==0) speaker <= ~speaker;
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endmodule
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