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31 lines
770 B
Verilog
31 lines
770 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 03:54:03 04/24/2014
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// Design Name:
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// Module Name: StatusChecker
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module StatusChecker(input Reset,CounterX,input R_Pipes_off,input R_Pipes2_off,input R_Bird_off,output reg Status);
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initial Status = 1;
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always @ (posedge CounterX)
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begin
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if (!Reset) Status <= 1;
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if ((R_Pipes_off && R_Bird_off) || (R_Pipes2_off && R_Bird_off)) Status <= 0;
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end
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endmodule
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