mirror of
https://github.com/Gehstock/Mist_FPGA.git
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102 lines
4.2 KiB
Verilog
102 lines
4.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 04:47:12 04/23/2014
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// Design Name:
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// Module Name: TopModule
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module TopModule(Clk,Button,Reset, vga_h_sync, vga_v_sync, vga_R, vga_G, vga_B,Speaker);
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input Clk,Button,Reset;
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output vga_h_sync, vga_v_sync, vga_R, vga_G, vga_B ,Speaker;
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wire inDisplayArea;
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wire [9:0] CounterX;
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wire [8:0] CounterY;
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wire [24:0] Clks;
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wire Status;
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wire [15:0] Pattern1;
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wire [15:0] Pattern2;
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wire [15:0] PipesPosition1;
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wire [15:0] PipesPosition2;
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wire R_Pipes_on,G_Pipes_on,B_Pipes_on,R_Pipes_off,G_Pipes_off,B_Pipes_off;
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wire R_Pipes2_on,G_Pipes2_on,B_Pipes2_on,R_Pipes2_off,G_Pipes2_off,B_Pipes2_off;
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wire [15:0] R_Bird_on,G_Bird_on,B_Bird_on,R_Bird_off,G_Bird_off,B_Bird_off;
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wire Button;
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wire R_Background, G_Background, B_Background;
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wire R_OnBackground_on, G_OnBackground_on, B_OnBackground_on;
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wire R_OnBackground_off, G_OnBackground_off, B_OnBackground_off;
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wire R_Board_on,G_Board_on,B_Board_on,R_Board_off,G_Board_off,B_Board_off;
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wire R_Score_on,G_Score_on,B_Score_on,R_Score_off,G_Score_off,B_Score_off;
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wire R_Item_on,G_Item_on,B_Item_on,R_Item_off,G_Item_off,B_Item_off;
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VGAOut syncgen(.Clk(Clk), .vga_h_sync(vga_h_sync), .vga_v_sync(vga_v_sync), .inDisplayArea(inDisplayArea), .CounterX(CounterX), .CounterY(CounterY));
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//Debouncer deb (Clk,Button,Button);
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SlowClock s1 (Clk,Reset,Clks);
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////////////////////////////////////////////////////////////////////////////////////////////////////////////
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StatusChecker s7 (Reset,CounterX,R_Pipes_off,R_Pipes2_off,R_Bird_off,Status);
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DrawBackground s2 (Clks,Status,CounterX,CounterY,R_Background,G_Background,B_Background);
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DrawOnBackground s22 (Clks,CounterX,CounterY,R_OnBackground_on,G_OnBackground_on,B_OnBackground_on,R_OnBackground_off,G_OnBackground_off,B_OnBackground_off);
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DrawBird s3 (Clks,Reset,CounterX,CounterY,Button,Status,R_Bird_on,G_Bird_on,B_Bird_on,R_Bird_off,G_Bird_off,B_Bird_off);
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DrawPipes s4 (Clks,Reset,CounterX,CounterY,Button,Status,Pattern1,R_Pipes_on,G_Pipes_on,B_Pipes_on,R_Pipes_off,G_Pipes_off,B_Pipes_off,PipesPosition1);
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DrawPipes2 s44 (Clks,Reset,CounterX,CounterY,Button,Status,Pattern2,R_Pipes2_on,G_Pipes2_on,B_Pipes2_on,R_Pipes2_off,G_Pipes2_off,B_Pipes2_off,PipesPosition2);
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Pattern p (Clks,Reset,PipesPosition1,PipesPosition2,Button,Pattern1,Pattern2);
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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DrawScore s5 (Clks,Reset,PipesPosition1,PipesPosition2,CounterX,CounterY,Button,Status,R_Score_on,G_Score_on,B_Score_on,R_Score_off,G_Score_off,B_Score_off);
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Sound so (Clk,PipesPosition1,PipesPosition2,Speaker);
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DrawItem s6 (Clks,CounterX,CounterY,Button,R_Item_on,G_Item_on,B_Item_on,R_Item_off,G_Item_off,B_Item_off);
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DrawBoard dd (Clks,Reset,CounterX,CounterY,Button,Status,R_Board_on,G_Board_on,B_Board_on,R_Board_off,G_Board_off,B_Board_off);
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wire RLayer0 = (R_Background | R_OnBackground_on) & ~R_OnBackground_off;
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wire GLayer0 = (G_Background | G_OnBackground_on) & ~G_OnBackground_off;
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wire BLayer0 = (B_Background | B_OnBackground_on) & ~B_OnBackground_off;
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wire RLayer1 = (RLayer0 & ~R_Pipes_off) & ~R_Pipes2_off;
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wire GLayer1 = ((GLayer0 | G_Pipes_on | G_Pipes2_on) & ~G_Pipes_off) & ~G_Pipes2_off;
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wire BLayer1 = (BLayer0 & ~B_Pipes_off) & ~B_Pipes2_off;
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wire RLayer2 = (RLayer1 | R_Board_on) &~R_Board_off;
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wire GLayer2 = (GLayer1 | G_Board_on) &~G_Board_off;
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wire BLayer2 = (BLayer1 | B_Board_on) &~B_Board_off;
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wire RLayer3 = (RLayer2 | R_Bird_on) & ~R_Bird_off;
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wire GLayer3 = (GLayer2 | G_Bird_on) & ~G_Bird_off;
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wire BLayer3 = (BLayer2 | B_Bird_on) & ~B_Bird_off;
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wire RLayer4 = (RLayer3 | R_Score_on) & ~R_Score_off;
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wire GLayer4 = (GLayer3 | G_Score_on) & ~G_Score_off;
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wire BLayer4 = (BLayer3 | B_Score_on) & ~B_Score_off;
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reg vga_R, vga_G, vga_B;
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always @(posedge Clk)
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begin
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begin
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vga_R <= RLayer4 & inDisplayArea;
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vga_G <= GLayer4 & inDisplayArea;
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vga_B <= BLayer4 & inDisplayArea;
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end
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end
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endmodule |