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99 lines
5.1 KiB
Markdown
99 lines
5.1 KiB
Markdown
# JT49 FPGA Clone of YM2149 hardware by Jose Tejada (@topapate)
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You can show your appreciation through
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* [Patreon](https://patreon.com/topapate), by supporting releases
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* [Paypal](https://paypal.me/topapate), with a donation
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YM2149 compatible Verilog core, with emphasis on FPGA implementation as part of JT12 in order to recreate the YM2203 part.
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## Usage
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There are two top level files you can use:
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- **jt49_bus**: presents the expected AY-3-8910 interface
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- **jt49**: presents a simplified interface, ideal to embed. This is the one used by jt12
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clk_en cannot be set to 1 for correct operation. The design assumes that there will be at least one empty clock cycle between every two clk_en high clock cycles.
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## Port Description jt49
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Name | Direction | Width | Purpose
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---------|-----------|-------|-------------------------------------
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rst_n | input | | active-low asynchronous reset signal
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clk | input | | clock
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clk_en | input | | clock enable. It cannot be a permanent 1
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addr | input | 4 | selects the register to access to
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cs_n | input | | chip-select, active low
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wr_n | input | | active-low write signal
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din | input | 8 | data to write to registers
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sel | input | | input clock is further divided by 2 when low
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dout | output | 8 | data read from registers. Updated when cs_n is low
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sound | output | 10 | Unsigned combined output of the three channels
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A | output | 8 | Unsigned output of channel A
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B | output | 8 | Unsigned output of channel B
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C | output | 8 | Unsigned output of channel C
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The module is not designed to be used at full clk speed. The clock enable input signal should divide the clock at least by two. This is needed because the volume LUT is shared for all three channels and the pipeline does not include wait states for the LUT as wait states happen naturally when clk_en is used.
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The ports of **jt49_bus** replace the CPU interface with that of the original AY-3-8910.
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Name | Direction | Width | Purpose
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---------|-----------|-------|-------------------------------------
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rst_n | input | | active-low asynchronous reset signal
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clk | input | | clock
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clk_en | input | | clock enable. It cannot be a permanent 1
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bdir | input | | bdir pin of AY-3-8910
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bc1 | input | | bc1 pin of AY-3-8910
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din | input | 8 | data to write to registers
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sel | input | | input clock is further divided by 2 when low
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dout | output | 8 | data read from registers. Updated when cs_n is low
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sound | output | 10 | Unsigned combined output of the three channels
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A | output | 8 | Unsigned output of channel A
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B | output | 8 | Unsigned output of channel B
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C | output | 8 | Unsigned output of channel C
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IOA_in | input | 8 | I/O port A, input side
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IOA_in | output | 8 | I/O port A, output side
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IOB_in | input | 8 | I/O port B, input side
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IOB_in | output | 8 | I/O port B, output side
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## Comparison with AY-3-8910 Verilog Model
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A simulation test bench of jt49 vs the AY-3-8910 model (available in the doc folder via a git submodule) is available in folder ver/comp. The simulation uses a simple text file to enter arbitrary commands (test_cmd). The command file is converted to hexadecimal by parser.awk and used in simulation. The following parameters were tested:
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Item | Compliance | Remarks
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---------------------|------------------|-------------------------------
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channel period | Yes | Tested: 0, 1 and FFFF values
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noise period | Yes | Tested: 0, 7 and 1F values
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envelope shape | Yes | Tested all 16 shapes
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envelope period | Yes | Tested 0 and FFF values
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## Resistor Load Modelling
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The resistor load had an effect of gain compression on the chip. There is a parameter called **COMP** which can be used to model this effect. You can assign a value from 0 to 3.
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Value | Dynamic Range | Equivalent resistor
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------|---------------|--------------------
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0 | 43.6 dB | <1000 Ohm
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1 | 29.1 dB | ~8000 Ohm
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2 | 21.8 dB | ~40 kOhm (?)
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3 | 13.4 dB | ~99 kOhm
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## Non Linear Effects
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- Saturation effects are not modelled
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- Channel mixing effects by short circuiting the outputs are not modelled
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## Related Projects
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Other sound chips from the same author
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Chip | Repository
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-----------------------|------------
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YM2203, YM2612, YM2610 | [JT12](https://github.com/jotego/jt12)
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YM2151 | [JT51](https://github.com/jotego/jt51)
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YM3526 | [JTOPL](https://github.com/jotego/jtopl)
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YM2149 | [JT49](https://github.com/jotego/jt49)
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sn76489an | [JT89](https://github.com/jotego/jt89)
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OKI 6295 | [JT6295](https://github.com/jotego/jt6295)
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OKI MSM5205 | [JT5205](https://github.com/jotego/jt5205)
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NEC uPN7759 | [JT7759](https://github.com/jotego/jt7759) |