mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-04-25 20:11:30 +00:00
122 lines
1.7 KiB
Systemverilog
122 lines
1.7 KiB
Systemverilog
module LaserCassEmu(
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input wire [15:0] CPU_A,
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input wire CPU_RD,
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input wire CPU_WR
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);
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// cassette
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(*keep*)wire [1:0] CASS_OUT;
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(*keep*)wire CASS_IN;
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(*keep*)wire CASS_IN_L;
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(*keep*)wire CASS_IN_R;
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reg [7:0] LATCHED_IO_DATA_WR;
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// 用于外部磁带仿真计数
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//(*keep*)reg EMU_CASS_CLK;
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(*keep*)wire EMU_CASS_EN;
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(*keep*)wire [1:0] EMU_CASS_DAT;
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`ifdef CASS_EMU
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wire CASS_BUF_RD;
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wire [15:0] CASS_BUF_A;
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wire CASS_BUF_WR;
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wire [7:0] CASS_BUF_DAT;
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wire [7:0] CASS_BUF_Q;
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// F9 CASS PLAY
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// F10 CASS STOP
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EMU_CASS_KEY EMU_CASS_KEY(
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KEY_Fxx[8],
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KEY_Fxx[9],
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// cass emu
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CASS_BUF_RD,
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//
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CASS_BUF_A,
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CASS_BUF_WR,
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CASS_BUF_DAT,
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CASS_BUF_Q,
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// Control Signals
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EMU_CASS_EN,
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EMU_CASS_DAT,
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// key emu
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EMU_KEY,
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EMU_KEY_EX,
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EMU_KEY_EN,
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/*
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* UART: 115200 bps, 8N1
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*/
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UART_RXD,
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UART_TXD,
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// System
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TURBO_SPEED,
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// Clock: 10MHz
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CLK10MHZ,
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RESET_N
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);
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`ifdef CASS_EMU_16K
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cass_ram_16k_altera cass_buf(
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.address(CASS_BUF_A[13:0]),
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.clock(CLK10MHZ),
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.data(CASS_BUF_DI),
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.wren(CASS_BUF_WR),
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.q(CASS_BUF_Q)
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);
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`endif
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`ifdef CASS_EMU_8K
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cass_ram_8k_altera cass_buf(
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.address(CASS_BUF_A[12:0]),
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.clock(CLK10MHZ),
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.data(CASS_BUF_DI),
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.wren(CASS_BUF_WR),
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.q(CASS_BUF_Q)
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);
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`endif
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`ifdef CASS_EMU_4K
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cass_ram_4k_altera cass_buf(
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.address(CASS_BUF_A[11:0]),
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.clock(CLK10MHZ),
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.data(CASS_BUF_DAT),
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.wren(CASS_BUF_WR),
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.q(CASS_BUF_Q)
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);
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`endif
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`ifdef CASS_EMU_2K
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cass_ram_2k_altera cass_buf(
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.address(CASS_BUF_A[10:0]),
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.clock(CLK10MHZ),
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.data(CASS_BUF_DAT),
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.wren(CASS_BUF_WR),
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.q(CASS_BUF_Q)
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);
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`endif
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`endif
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assign CASS_OUT = EMU_CASS_EN ? EMU_CASS_DAT : {LATCHED_IO_DATA_WR[2], 1'b0};
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(*keep*)wire trap = (CPU_RD|CPU_WR) && (CPU_A[15:12] == 4'h0);
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endmodule
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