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https://github.com/Gehstock/Mist_FPGA.git
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22 lines
1.7 KiB
Plaintext
22 lines
1.7 KiB
Plaintext
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) cpu86pack.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) cpu86instr.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) biufsm_fsm.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) a_table.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) d_table.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) n_table.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) r_table.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) m_table.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) formatter_struct.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) regshiftmux_regshift.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) biu_struct.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dataregfile_rtl.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) segregfile_rtl.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) divider_rtl_ser.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) multiplier_rtl.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) alu_rtl.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ipregister_rtl.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) datapath_struct.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) proc_rtl.vhd ]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) cpu86_struct.vhd ]
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