mirror of
https://github.com/Gehstock/Mist_FPGA.git
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434 lines
9.2 KiB
Systemverilog
434 lines
9.2 KiB
Systemverilog
//============================================================================
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//
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// SD card ROM loader and ROM selector for MISTer.
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// Copyright (C) 2019, 2020 Kitrinx (aka Rysha)
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//
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// Permission is hereby granted, free of charge, to any person obtaining a
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// copy of this software and associated documentation files (the "Software"),
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// to deal in the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS IN THE SOFTWARE.
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//
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//============================================================================
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// Rom layout for Finalizer:
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// 0x0000 - 0x3FFF = eprom_1
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// 0x4000 - 0x7FFF = eprom_2
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// 0x8000 - 0xBFFF = eprom_3
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// 0xC000 - 0xFFFF = eprom_4
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// 0x10000 - 0x13FFF = eprom_5
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// 0x14000 - 0x17FFF = eprom_6
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// 0x18000 - 0x1BFFF = eprom_7
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// 0x1C000 - 0x1FFFF = eprom_8
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// 0x20000 - 0x23FFF = eprom_9
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// 0x24000 - 0x247FF = snd01
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// 0x24800 - 0x248FF = prom_1
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// 0x24900 - 0x249FF = prom_2
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// 0x24A00 - 0x24A1F = prom_3
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// 0x24A20 - 0x24A3F = prom_4
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module selector
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(
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input logic [24:0] ioctl_addr,
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output logic ep1_cs, ep2_cs, ep3_cs, ep4_cs, ep5_cs, ep6_cs, ep7_cs, ep8_cs, ep9_cs, snd01_cs,
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prom1_cs, prom2_cs, prom3_cs, prom4_cs
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);
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always_comb begin
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{ep1_cs, ep2_cs, ep3_cs, ep4_cs, ep5_cs, ep6_cs, ep7_cs, ep8_cs, ep9_cs, snd01_cs,
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prom1_cs, prom2_cs, prom3_cs, prom4_cs} = 0;
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if(ioctl_addr < 'h4000)
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ep1_cs = 1; // 0x4000 14
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else if(ioctl_addr < 'h8000)
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ep2_cs = 1; // 0x4000 14
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else if(ioctl_addr < 'hC000)
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ep3_cs = 1; // 0x4000 14
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else if(ioctl_addr < 'h10000)
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ep4_cs = 1; // 0x4000 14
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else if(ioctl_addr < 'h14000)
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ep5_cs = 1; // 0x4000 14
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else if(ioctl_addr < 'h18000)
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ep6_cs = 1; // 0x4000 14
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else if(ioctl_addr < 'h1C000)
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ep7_cs = 1; // 0x4000 14
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else if(ioctl_addr < 'h20000)
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ep8_cs = 1; // 0x4000 14
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else if(ioctl_addr < 'h24000)
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ep9_cs = 1; // 0x4000 14
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else if(ioctl_addr < 'h24800)
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snd01_cs = 1; // 0x800 11
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else if(ioctl_addr < 'h24900)
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prom1_cs = 1; // 0x100 8
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else if(ioctl_addr < 'h24A00)
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prom2_cs = 1; // 0x100 8
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else if(ioctl_addr < 'h24A20)
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prom3_cs = 1; // 0x20 5
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else
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prom4_cs = 1; // 0x20 5
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end
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endmodule
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////////////
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// EPROMS //
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////////////
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module eprom_1
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(
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input logic CLK,
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input logic CLK_DL,
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input logic [13:0] ADDR,
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input logic [24:0] ADDR_DL,
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input logic [7:0] DATA_IN,
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input logic CS_DL,
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input logic WR,
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output logic [7:0] DATA
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);
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dpram_dc #(.widthad_a(14)) eprom_1
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(
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.clock_a(CLK),
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.address_a(ADDR[13:0]),
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.q_a(DATA[7:0]),
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.clock_b(CLK_DL),
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.address_b(ADDR_DL[13:0]),
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.data_b(DATA_IN),
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.wren_b(WR & CS_DL)
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);
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endmodule
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module eprom_2
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(
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input logic CLK,
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input logic CLK_DL,
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input logic [13:0] ADDR,
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input logic [24:0] ADDR_DL,
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input logic [7:0] DATA_IN,
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input logic CS_DL,
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input logic WR,
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output logic [7:0] DATA
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);
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dpram_dc #(.widthad_a(14)) eprom_2
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(
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.clock_a(CLK),
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.address_a(ADDR[13:0]),
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.q_a(DATA[7:0]),
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.clock_b(CLK_DL),
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.address_b(ADDR_DL[13:0]),
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.data_b(DATA_IN),
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.wren_b(WR & CS_DL)
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);
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endmodule
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module eprom_3
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(
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input logic CLK,
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input logic CLK_DL,
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input logic [13:0] ADDR,
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input logic [24:0] ADDR_DL,
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input logic [7:0] DATA_IN,
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input logic CS_DL,
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input logic WR,
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output logic [7:0] DATA
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);
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dpram_dc #(.widthad_a(14)) eprom_3
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(
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.clock_a(CLK),
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.address_a(ADDR[13:0]),
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.q_a(DATA[7:0]),
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.clock_b(CLK_DL),
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.address_b(ADDR_DL[13:0]),
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.data_b(DATA_IN),
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.wren_b(WR & CS_DL)
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);
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endmodule
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module eprom_4
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(
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input logic CLK_A,
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input logic CLK_B,
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input logic [13:0] ADDR_A,
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input logic [24:0] ADDR_B,
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input logic [7:0] DATA_IN,
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input logic CS_DL,
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input logic WR,
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output logic [7:0] DATAOUT_A,
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output logic [7:0] DATAOUT_B
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);
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dpram_dc #(.widthad_a(14)) eprom_4
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(
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.clock_a(CLK_A),
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.address_a(ADDR_A[13:0]),
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.q_a(DATAOUT_A[7:0]),
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.clock_b(CLK_B),
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.address_b(ADDR_B[13:0]),
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.data_b(DATA_IN),
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.q_b(DATAOUT_B[7:0]),
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.wren_b(WR & CS_DL)
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);
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endmodule
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module eprom_5
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(
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input logic CLK_A,
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input logic CLK_B,
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input logic [13:0] ADDR_A,
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input logic [24:0] ADDR_B,
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input logic [7:0] DATA_IN,
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input logic CS_DL,
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input logic WR,
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output logic [7:0] DATAOUT_A,
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output logic [7:0] DATAOUT_B
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);
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dpram_dc #(.widthad_a(14)) eprom_5
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(
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.clock_a(CLK_A),
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.address_a(ADDR_A[13:0]),
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.q_a(DATAOUT_A[7:0]),
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.clock_b(CLK_B),
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.address_b(ADDR_B[13:0]),
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.data_b(DATA_IN),
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.q_b(DATAOUT_B[7:0]),
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.wren_b(WR & CS_DL)
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);
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endmodule
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module eprom_6
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(
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input logic CLK,
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input logic CLK_DL,
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input logic [13:0] ADDR,
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input logic [24:0] ADDR_DL,
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input logic [7:0] DATA_IN,
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input logic CS_DL,
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input logic WR,
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output logic [7:0] DATA
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);
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dpram_dc #(.widthad_a(14)) eprom_6
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(
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.clock_a(CLK),
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.address_a(ADDR[13:0]),
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.q_a(DATA[7:0]),
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.clock_b(CLK_DL),
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.address_b(ADDR_DL[13:0]),
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.data_b(DATA_IN),
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.wren_b(WR & CS_DL)
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);
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endmodule
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module eprom_7
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(
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input logic CLK,
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input logic CLK_DL,
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input logic [13:0] ADDR,
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input logic [24:0] ADDR_DL,
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input logic [7:0] DATA_IN,
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input logic CS_DL,
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input logic WR,
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output logic [7:0] DATA
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);
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dpram_dc #(.widthad_a(14)) eprom_7
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(
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.clock_a(CLK),
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.address_a(ADDR[13:0]),
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.q_a(DATA[7:0]),
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.clock_b(CLK_DL),
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.address_b(ADDR_DL[13:0]),
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.data_b(DATA_IN),
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.wren_b(WR & CS_DL)
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);
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endmodule
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module eprom_8
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(
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input logic CLK,
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input logic CLK_DL,
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input logic [13:0] ADDR,
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input logic [24:0] ADDR_DL,
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input logic [7:0] DATA_IN,
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input logic CS_DL,
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input logic WR,
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output logic [7:0] DATA
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);
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dpram_dc #(.widthad_a(14)) eprom_8
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(
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.clock_a(CLK),
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.address_a(ADDR[13:0]),
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.q_a(DATA[7:0]),
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.clock_b(CLK_DL),
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.address_b(ADDR_DL[13:0]),
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.data_b(DATA_IN),
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.wren_b(WR & CS_DL)
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);
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endmodule
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module eprom_9
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(
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input logic CLK,
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input logic CLK_DL,
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input logic [13:0] ADDR,
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input logic [24:0] ADDR_DL,
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input logic [7:0] DATA_IN,
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input logic CS_DL,
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input logic WR,
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output logic [7:0] DATA
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);
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dpram_dc #(.widthad_a(14)) eprom_9
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(
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.clock_a(CLK),
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.address_a(ADDR[13:0]),
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.q_a(DATA[7:0]),
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.clock_b(CLK_DL),
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.address_b(ADDR_DL[13:0]),
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.data_b(DATA_IN),
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.wren_b(WR & CS_DL)
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);
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endmodule
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///////////////////
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// EMBEDDED ROMS //
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///////////////////
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module kSND01_ROM
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(
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input logic CLK,
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input logic CLK_DL,
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input logic [10:0] ADDR,
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input logic [24:0] ADDR_DL,
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input logic [7:0] DATA_IN,
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input logic CS_DL,
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input logic WR,
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output logic [7:0] DATA
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);
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dpram_dc #(.widthad_a(11)) kSND01_ROM
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(
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.clock_a(CLK),
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.address_a(ADDR[10:0]),
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.q_a(DATA[7:0]),
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.clock_b(CLK_DL),
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.address_b(ADDR_DL[10:0]),
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.data_b(DATA_IN),
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.wren_b(WR & CS_DL)
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);
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endmodule
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///////////
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// PROMS //
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///////////
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module prom_1
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(
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input logic CLK,
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input logic CLK_DL,
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input logic [7:0] ADDR,
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input logic [24:0] ADDR_DL,
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input logic [3:0] DATA_IN,
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input logic CS_DL,
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input logic WR,
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output logic [3:0] DATA
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);
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dpram_dc #(.widthad_a(8)) prom_1
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(
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.clock_a(CLK),
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.address_a(ADDR),
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.q_a(DATA[3:0]),
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.clock_b(CLK_DL),
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.address_b(ADDR_DL[7:0]),
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.data_b(DATA_IN),
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.wren_b(WR & CS_DL)
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);
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endmodule
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module prom_2
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(
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input logic CLK,
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input logic CLK_DL,
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input logic [7:0] ADDR,
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input logic [24:0] ADDR_DL,
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input logic [3:0] DATA_IN,
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input logic CS_DL,
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input logic WR,
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output logic [3:0] DATA
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);
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dpram_dc #(.widthad_a(8)) prom_2
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(
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.clock_a(CLK),
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.address_a(ADDR),
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.q_a(DATA[3:0]),
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.clock_b(CLK_DL),
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.address_b(ADDR_DL[7:0]),
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.data_b(DATA_IN),
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.wren_b(WR & CS_DL)
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);
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endmodule
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module prom_3
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(
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input logic CLK,
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input logic CLK_DL,
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input logic [4:0] ADDR,
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input logic [24:0] ADDR_DL,
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input logic [7:0] DATA_IN,
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input logic CS_DL,
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input logic WR,
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output logic [7:0] DATA
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);
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dpram_dc #(.widthad_a(5)) prom_3
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(
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.clock_a(CLK),
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.address_a(ADDR),
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.q_a(DATA[7:0]),
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.clock_b(CLK_DL),
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.address_b(ADDR_DL[7:0]),
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.data_b(DATA_IN),
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.wren_b(WR & CS_DL)
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);
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endmodule
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module prom_4
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(
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input logic CLK,
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input logic CLK_DL,
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input logic [4:0] ADDR,
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input logic [24:0] ADDR_DL,
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input logic [7:0] DATA_IN,
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input logic CS_DL,
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input logic WR,
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output logic [7:0] DATA
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);
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dpram_dc #(.widthad_a(5)) prom_4
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(
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.clock_a(CLK),
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.address_a(ADDR),
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.q_a(DATA[7:0]),
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.clock_b(CLK_DL),
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.address_b(ADDR_DL[7:0]),
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.data_b(DATA_IN),
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.wren_b(WR & CS_DL)
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);
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endmodule
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