mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-04-25 12:01:37 +00:00
8 lines
658 B
Plaintext
8 lines
658 B
Plaintext
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) opl3.sv ]
|
|
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) opl3fm.sv ]
|
|
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) opl3seq.sv ]
|
|
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) compressor.sv]
|
|
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) NextZ80Reg.v ]
|
|
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) NextZ80CPU.v ]
|
|
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) NextZ80ALU.v ]
|