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23 lines
379 B
Verilog
23 lines
379 B
Verilog
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module rom (
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input clk,
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input [15:0] addr,
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output reg [7:0] dout,
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input cs,
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input rom_init,
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input rom_init_clk,
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input [15:0] rom_init_address,
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input [7:0] rom_init_data
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);
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reg [7:0] memory[65535:0];
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always @(posedge clk)
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if (~cs) dout <= memory[addr];
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always @(posedge rom_init_clk)
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if (rom_init)
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memory[rom_init_address] <= rom_init_data;
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endmodule
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