mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-04-12 22:56:55 +00:00
Supervision
This commit is contained in:
Marcel
@@ -102,8 +102,8 @@ ultra_tank ultra_tank (
|
||||
.Reset_n(~(status[0] | buttons[1])),
|
||||
.HS(hs),
|
||||
.VS(vs),
|
||||
.HB(vb),
|
||||
.VB(hb),
|
||||
.HB(hb),
|
||||
.VB(vb),
|
||||
.Vid(Vid),
|
||||
.CC3_n_O(),
|
||||
.CC0_O(video_b),
|
||||
|
||||
@@ -28,8 +28,7 @@ localparam CONF_STR = {
|
||||
};
|
||||
|
||||
assign LED = ~ioctl_downl;
|
||||
//assign AUDIO_R = AUDIO_L;
|
||||
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
wire pll_locked,clock_28p636, clk3p579;
|
||||
pll pll(
|
||||
.locked ( pll_locked ),
|
||||
@@ -56,13 +55,14 @@ channel_f channel_f(
|
||||
.ioctl_wr ( ~ioctl_wr ),//todo
|
||||
.ioctl_addr ( ioctl_addr ),
|
||||
.ioctl_dout ( ioctl_dout ),
|
||||
.ioctl_wait ( ),//todo
|
||||
.ioctl_wait ( ioctl_wait ),//todo
|
||||
.audio ( audio )
|
||||
);
|
||||
|
||||
wire ioctl_downl;
|
||||
wire [7:0] ioctl_index;
|
||||
wire ioctl_wr;
|
||||
wire ioctl_wait;
|
||||
wire [24:0] ioctl_addr;
|
||||
wire [7:0] ioctl_dout;
|
||||
|
||||
@@ -101,11 +101,10 @@ mist_video #(.COLOR_DEPTH(6),.SD_HCNT_WIDTH(10)) mist_video(
|
||||
.no_csync ( no_csync )
|
||||
);
|
||||
|
||||
wire [31:0] status;
|
||||
wire [63:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire [1:0] switches;
|
||||
wire [31:0] joystick_0;
|
||||
wire [31:0] joystick_1;
|
||||
wire [31:0] joystick_0, joystick_1;
|
||||
wire scandoublerD;
|
||||
wire [7:0] r, g, b;
|
||||
wire hs, vs, blankn;
|
||||
@@ -138,23 +137,14 @@ user_io(
|
||||
.status ( status )
|
||||
);
|
||||
|
||||
//dac #(
|
||||
// .C_bits(16))
|
||||
//dac(
|
||||
// .clk_i ( clock_28p636 ),
|
||||
// .res_n_i ( 1'b1 ),
|
||||
// .dac_i ( audio ),
|
||||
// .dac_o ( AUDIO_L )
|
||||
// );
|
||||
|
||||
mist_audio #(16,0,0) mist_audio(
|
||||
.clk ( clock_28p636 ),
|
||||
.reset_n ( 1'b1 ),
|
||||
.audio_inL ( audio ),
|
||||
// .audio_inR ( audio ),
|
||||
.AUDIO_L ( AUDIO_L ),
|
||||
.AUDIO_R ( AUDIO_R )
|
||||
);
|
||||
dac #(
|
||||
.C_bits(16))
|
||||
dac(
|
||||
.clk_i ( clock_28p636 ),
|
||||
.res_n_i ( 1'b1 ),
|
||||
.dac_i ( audio ),
|
||||
.dac_o ( AUDIO_L )
|
||||
);
|
||||
|
||||
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
|
||||
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
|
||||
|
||||
19
Console_MiST/Supervision_MiST/ReadMe.txt
Normal file
19
Console_MiST/Supervision_MiST/ReadMe.txt
Normal file
@@ -0,0 +1,19 @@
|
||||
Watara Supervision for MiSTer by Pierre Cornier
|
||||
|
||||
|
||||
|
||||
wip
|
||||
|
||||
VGA Only
|
||||
|
||||
|
||||
Working for Now
|
||||
|
||||
Brain Power
|
||||
Galactic Crusader
|
||||
Galaxy Fighter
|
||||
Happy Pairs
|
||||
John Advenzure
|
||||
Kabi Island
|
||||
Penguin Hideout
|
||||
Super Kong
|
||||
BIN
Console_MiST/Supervision_MiST/Snapshot/Supervision_MiST.rbf
Normal file
BIN
Console_MiST/Supervision_MiST/Snapshot/Supervision_MiST.rbf
Normal file
Binary file not shown.
30
Console_MiST/Supervision_MiST/Supervision_MiST.qpf
Normal file
30
Console_MiST/Supervision_MiST/Supervision_MiST.qpf
Normal file
@@ -0,0 +1,30 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
|
||||
# Date created = 14:59:16 November 16, 2017
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.1"
|
||||
DATE = "14:59:16 November 16, 2017"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "Supervision_MiST"
|
||||
240
Console_MiST/Supervision_MiST/Supervision_MiST.qsf
Normal file
240
Console_MiST/Supervision_MiST/Supervision_MiST.qsf
Normal file
@@ -0,0 +1,240 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2014 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
|
||||
# Date created = 21:20:48 December 16, 2020
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# Supervision_MiST_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Supervision_MiST.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Supervision_Top.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/audio.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dma.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ram88.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
|
||||
set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/mist/mist.qip"
|
||||
set_global_assignment -name VERILOG_FILE rtl/65c02/cpu_65c02.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/65c02/cpu.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/65c02/ALU.v
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_location_assignment PIN_7 -to LED
|
||||
set_location_assignment PIN_54 -to CLOCK_27
|
||||
set_location_assignment PIN_144 -to VGA_R[5]
|
||||
set_location_assignment PIN_143 -to VGA_R[4]
|
||||
set_location_assignment PIN_142 -to VGA_R[3]
|
||||
set_location_assignment PIN_141 -to VGA_R[2]
|
||||
set_location_assignment PIN_137 -to VGA_R[1]
|
||||
set_location_assignment PIN_135 -to VGA_R[0]
|
||||
set_location_assignment PIN_133 -to VGA_B[5]
|
||||
set_location_assignment PIN_132 -to VGA_B[4]
|
||||
set_location_assignment PIN_125 -to VGA_B[3]
|
||||
set_location_assignment PIN_121 -to VGA_B[2]
|
||||
set_location_assignment PIN_120 -to VGA_B[1]
|
||||
set_location_assignment PIN_115 -to VGA_B[0]
|
||||
set_location_assignment PIN_114 -to VGA_G[5]
|
||||
set_location_assignment PIN_113 -to VGA_G[4]
|
||||
set_location_assignment PIN_112 -to VGA_G[3]
|
||||
set_location_assignment PIN_111 -to VGA_G[2]
|
||||
set_location_assignment PIN_110 -to VGA_G[1]
|
||||
set_location_assignment PIN_106 -to VGA_G[0]
|
||||
set_location_assignment PIN_136 -to VGA_VS
|
||||
set_location_assignment PIN_119 -to VGA_HS
|
||||
set_location_assignment PIN_65 -to AUDIO_L
|
||||
set_location_assignment PIN_80 -to AUDIO_R
|
||||
set_location_assignment PIN_105 -to SPI_DO
|
||||
set_location_assignment PIN_88 -to SPI_DI
|
||||
set_location_assignment PIN_126 -to SPI_SCK
|
||||
set_location_assignment PIN_127 -to SPI_SS2
|
||||
set_location_assignment PIN_91 -to SPI_SS3
|
||||
set_location_assignment PIN_13 -to CONF_DATA0
|
||||
set_location_assignment PIN_49 -to SDRAM_A[0]
|
||||
set_location_assignment PIN_44 -to SDRAM_A[1]
|
||||
set_location_assignment PIN_42 -to SDRAM_A[2]
|
||||
set_location_assignment PIN_39 -to SDRAM_A[3]
|
||||
set_location_assignment PIN_4 -to SDRAM_A[4]
|
||||
set_location_assignment PIN_6 -to SDRAM_A[5]
|
||||
set_location_assignment PIN_8 -to SDRAM_A[6]
|
||||
set_location_assignment PIN_10 -to SDRAM_A[7]
|
||||
set_location_assignment PIN_11 -to SDRAM_A[8]
|
||||
set_location_assignment PIN_28 -to SDRAM_A[9]
|
||||
set_location_assignment PIN_50 -to SDRAM_A[10]
|
||||
set_location_assignment PIN_30 -to SDRAM_A[11]
|
||||
set_location_assignment PIN_32 -to SDRAM_A[12]
|
||||
set_location_assignment PIN_83 -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_79 -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_77 -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_76 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_72 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_71 -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_69 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_68 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_86 -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_87 -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_98 -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_99 -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_100 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_101 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_103 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_104 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_58 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_51 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_85 -to SDRAM_DQMH
|
||||
set_location_assignment PIN_67 -to SDRAM_DQML
|
||||
set_location_assignment PIN_60 -to SDRAM_nRAS
|
||||
set_location_assignment PIN_64 -to SDRAM_nCAS
|
||||
set_location_assignment PIN_66 -to SDRAM_nWE
|
||||
set_location_assignment PIN_59 -to SDRAM_nCS
|
||||
set_location_assignment PIN_33 -to SDRAM_CKE
|
||||
set_location_assignment PIN_43 -to SDRAM_CLK
|
||||
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
|
||||
|
||||
# Classic Timing Assignments
|
||||
# ==========================
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||
set_global_assignment -name SAVE_DISK_SPACE OFF
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY Supervision_MiST
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
|
||||
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
|
||||
set_global_assignment -name ENABLE_NCE_PIN OFF
|
||||
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
|
||||
# Power Estimation Assignments
|
||||
# ============================
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
# Advanced I/O Timing Assignments
|
||||
# ===============================
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
|
||||
# ------------------------------
|
||||
# start ENTITY(Supervision_MiST)
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
# end ENTITY(Supervision_MiST)
|
||||
# ----------------------------
|
||||
set_global_assignment -name VERILOG_FILE rtl/pll1.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/pll2.v
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
41
Console_MiST/Supervision_MiST/clean.bat
Normal file
41
Console_MiST/Supervision_MiST/clean.bat
Normal file
@@ -0,0 +1,41 @@
|
||||
@echo off
|
||||
del /s *.bak
|
||||
del /s *.orig
|
||||
del /s *.rej
|
||||
del /s *~
|
||||
rmdir /s /q db
|
||||
rmdir /s /q incremental_db
|
||||
rmdir /s /q output_files
|
||||
rmdir /s /q simulation
|
||||
rmdir /s /q greybox_tmp
|
||||
rmdir /s /q hc_output
|
||||
rmdir /s /q .qsys_edit
|
||||
rmdir /s /q hps_isw_handoff
|
||||
rmdir /s /q sys\.qsys_edit
|
||||
rmdir /s /q sys\vip
|
||||
cd sys
|
||||
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
|
||||
cd ..
|
||||
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
|
||||
del build_id.v
|
||||
del c5_pin_model_dump.txt
|
||||
del PLLJ_PLLSPE_INFO.txt
|
||||
del /s *.qws
|
||||
del /s *.ppf
|
||||
del /s *.ddb
|
||||
del /s *.csv
|
||||
del /s *.cmp
|
||||
del /s *.sip
|
||||
del /s *.spd
|
||||
del /s *.bsf
|
||||
del /s *.f
|
||||
del /s *.sopcinfo
|
||||
del /s *.xml
|
||||
del *.cdf
|
||||
del /s new_rtl_netlist
|
||||
del /s old_rtl_netlist
|
||||
del sys\vip.qip
|
||||
del sys\sysmem.qip
|
||||
del sys\sdram.sv
|
||||
del sys\ddram.sv
|
||||
pause
|
||||
108
Console_MiST/Supervision_MiST/rtl/65c02/ALU.v
Normal file
108
Console_MiST/Supervision_MiST/rtl/65c02/ALU.v
Normal file
@@ -0,0 +1,108 @@
|
||||
/*
|
||||
* ALU.
|
||||
*
|
||||
* AI and BI are 8 bit inputs. Result in OUT.
|
||||
* CI is Carry In.
|
||||
* CO is Carry Out.
|
||||
*
|
||||
* op[3:0] is defined as follows:
|
||||
*
|
||||
* 0011 AI + BI
|
||||
* 0111 AI - BI
|
||||
* 1011 AI + AI
|
||||
* 1100 AI | BI
|
||||
* 1101 AI & BI
|
||||
* 1110 AI ^ BI
|
||||
* 1111 AI
|
||||
*
|
||||
*/
|
||||
|
||||
module ALU( clk, op, right, AI, BI, CI, CO, BCD, OUT, V, Z, N, HC, RDY );
|
||||
input clk;
|
||||
input right;
|
||||
input [3:0] op; // operation
|
||||
input [7:0] AI;
|
||||
input [7:0] BI;
|
||||
input CI;
|
||||
input BCD; // BCD style carry
|
||||
output [7:0] OUT;
|
||||
output CO;
|
||||
output V;
|
||||
output Z;
|
||||
output N;
|
||||
output HC;
|
||||
input RDY;
|
||||
|
||||
reg [7:0] OUT;
|
||||
reg CO;
|
||||
wire V;
|
||||
wire Z;
|
||||
reg N;
|
||||
reg HC;
|
||||
|
||||
reg AI7;
|
||||
reg BI7;
|
||||
reg [8:0] temp_logic;
|
||||
reg [7:0] temp_BI;
|
||||
reg [4:0] temp_l;
|
||||
reg [4:0] temp_h;
|
||||
wire [8:0] temp = { temp_h, temp_l[3:0] };
|
||||
wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI;
|
||||
|
||||
// calculate the logic operations. The 'case' can be done in 1 LUT per
|
||||
// bit. The 'right' shift is a simple mux that can be implemented by
|
||||
// F5MUX.
|
||||
always @* begin
|
||||
case( op[1:0] )
|
||||
2'b00: temp_logic = AI | BI;
|
||||
2'b01: temp_logic = AI & BI;
|
||||
2'b10: temp_logic = AI ^ BI;
|
||||
2'b11: temp_logic = AI;
|
||||
endcase
|
||||
|
||||
if( right )
|
||||
temp_logic = { AI[0], CI, AI[7:1] };
|
||||
end
|
||||
|
||||
// Add logic result to BI input. This only makes sense when logic = AI.
|
||||
// This stage can be done in 1 LUT per bit, using carry chain logic.
|
||||
always @* begin
|
||||
case( op[3:2] )
|
||||
2'b00: temp_BI = BI; // A+B
|
||||
2'b01: temp_BI = ~BI; // A-B
|
||||
2'b10: temp_BI = temp_logic; // A+A
|
||||
2'b11: temp_BI = 0; // A+0
|
||||
endcase
|
||||
end
|
||||
|
||||
// HC9 is the half carry bit when doing BCD add
|
||||
wire HC9 = BCD & (temp_l[3:1] >= 3'd5);
|
||||
|
||||
// CO9 is the carry-out bit when doing BCD add
|
||||
wire CO9 = BCD & (temp_h[3:1] >= 3'd5);
|
||||
|
||||
// combined half carry bit
|
||||
wire temp_HC = temp_l[4] | HC9;
|
||||
|
||||
// perform the addition as 2 separate nibble, so we get
|
||||
// access to the half carry flag
|
||||
always @* begin
|
||||
temp_l = temp_logic[3:0] + temp_BI[3:0] + adder_CI;
|
||||
temp_h = temp_logic[8:4] + temp_BI[7:4] + temp_HC;
|
||||
end
|
||||
|
||||
// calculate the flags
|
||||
always @(posedge clk)
|
||||
if( RDY ) begin
|
||||
AI7 <= AI[7];
|
||||
BI7 <= temp_BI[7];
|
||||
OUT <= temp[7:0];
|
||||
CO <= temp[8] | CO9;
|
||||
N <= temp[7];
|
||||
HC <= temp_HC;
|
||||
end
|
||||
|
||||
assign V = AI7 ^ BI7 ^ CO ^ N;
|
||||
assign Z = ~|OUT;
|
||||
|
||||
endmodule
|
||||
67
Console_MiST/Supervision_MiST/rtl/65c02/README
Normal file
67
Console_MiST/Supervision_MiST/rtl/65c02/README
Normal file
@@ -0,0 +1,67 @@
|
||||
========================================================
|
||||
A Verilog HDL version of the old MOS 6502 and 65C02 CPUs
|
||||
========================================================
|
||||
|
||||
Original 6502 core by Arlet Ottens
|
||||
|
||||
65C02 extensions by David Banks and Ed Spittles
|
||||
|
||||
==========
|
||||
6502 Core
|
||||
==========
|
||||
|
||||
Arlet's original 6502 core (cpu.v) is unchanged.
|
||||
|
||||
Note: the 6502/65C02 cores assumes a synchronous memory. This means
|
||||
that valid data (DI) is expected on the cycle *after* valid
|
||||
address. This allows direct connection to (Xilinx) block RAMs. When
|
||||
using asynchronous memory, I suggest registering the address/control
|
||||
lines for glitchless output signals.
|
||||
|
||||
Have fun.
|
||||
|
||||
==========
|
||||
65C02 Core
|
||||
==========
|
||||
|
||||
A second core (cpu_65c02.v) has been added, based on Arlet's 6502
|
||||
core, with additional 65C02 instructions and addressing modes:
|
||||
- PHX, PHY, PLX, PLY
|
||||
- BRA
|
||||
- INC A, DEC A
|
||||
- (zp) addressing mode
|
||||
- STZ
|
||||
- BIT zpx, absx, imm
|
||||
- TSB/TRB
|
||||
- JMP (,X)
|
||||
- NOPs (optional)
|
||||
- 65C02 BCD N/Z flags (optional, disabled)
|
||||
|
||||
The Rockwell/WDC specific instructions (RMB/SMB/BBR/BBS/WAI/STP) are
|
||||
not currently implemented
|
||||
|
||||
The 65C02 core passes the Dormann 6502 test suite, and also passes the
|
||||
Dormann 65C02 test suite if the optional support for NOPs and 65C02
|
||||
BCD flags is enabled.
|
||||
|
||||
It has been tested as a BBC Micro "Matchbox" 65C02 Co Processor, in a
|
||||
XC6SLX9-2 FPGA, running at 80MHz using 64KB of internel block RAM. It
|
||||
just meets timing at 80MHz in this environment. It successfully runs
|
||||
BBC Basic IV and Tube Elite.
|
||||
|
||||
============
|
||||
Known Issues
|
||||
============
|
||||
|
||||
The Matchbox Co Processor needed one wait state (via RDY) to be added
|
||||
to each ROM access (only needed early in the boot process, as
|
||||
eventually everything runs from RAM). The DIHOLD logic did not work
|
||||
correctly with a single wait state, and so has been commented out.
|
||||
|
||||
I now believe the correct fix is actually just:
|
||||
|
||||
always @(posedge clk )
|
||||
if( RDY )
|
||||
DIHOLD <= DI;
|
||||
|
||||
assign DIMUX = ~RDY ? DIHOLD : DI;
|
||||
1225
Console_MiST/Supervision_MiST/rtl/65c02/cpu.v
Normal file
1225
Console_MiST/Supervision_MiST/rtl/65c02/cpu.v
Normal file
File diff suppressed because it is too large
Load Diff
1395
Console_MiST/Supervision_MiST/rtl/65c02/cpu_65c02.v
Normal file
1395
Console_MiST/Supervision_MiST/rtl/65c02/cpu_65c02.v
Normal file
File diff suppressed because it is too large
Load Diff
232
Console_MiST/Supervision_MiST/rtl/Supervision_MiST.sv
Normal file
232
Console_MiST/Supervision_MiST/rtl/Supervision_MiST.sv
Normal file
@@ -0,0 +1,232 @@
|
||||
module Supervision_MiST(
|
||||
output LED,
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_HS,
|
||||
output VGA_VS,
|
||||
output AUDIO_L,
|
||||
output AUDIO_R,
|
||||
input SPI_SCK,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
input SPI_SS2,
|
||||
input SPI_SS3,
|
||||
input CONF_DATA0,
|
||||
input CLOCK_27,
|
||||
|
||||
output [12:0] SDRAM_A,
|
||||
inout [15:0] SDRAM_DQ,
|
||||
output SDRAM_DQML,
|
||||
output SDRAM_DQMH,
|
||||
output SDRAM_nWE,
|
||||
output SDRAM_nCAS,
|
||||
output SDRAM_nRAS,
|
||||
output SDRAM_nCS,
|
||||
output [1:0] SDRAM_BA,
|
||||
output SDRAM_CLK,
|
||||
output SDRAM_CKE
|
||||
);
|
||||
|
||||
`include "rtl\build_id.v"
|
||||
|
||||
localparam CONF_STR = {
|
||||
"SVISION;bin;",
|
||||
// "O34,Scanlines,Off,25%,50%,75%;",
|
||||
// "O5,Blending,Off,On;",
|
||||
"O6,Joyswap,Off,On;",
|
||||
"O8,Screen Color,Green,White;",
|
||||
"T0,Reset;",
|
||||
"V,v1.00.",`BUILD_DATE
|
||||
};
|
||||
|
||||
assign LED = ~ioctl_downl;
|
||||
assign SDRAM_CLK = ~clk_sys;
|
||||
assign SDRAM_CKE = 1;
|
||||
|
||||
wire clk_sys, clk_vid, clk_cpu, pll_locked;
|
||||
pll1 pll1(
|
||||
.inclk0(CLOCK_27),
|
||||
.c0(clk_sys),//50
|
||||
.c1(clk_cpu),// 4
|
||||
.locked(pll_locked)
|
||||
);
|
||||
|
||||
pll2 pll2(
|
||||
.inclk0(CLOCK_27),
|
||||
.c0(clk_vid)// 25.175
|
||||
);
|
||||
|
||||
wire [63:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire [1:0] switches;
|
||||
wire ypbpr;
|
||||
wire scandoublerD;
|
||||
wire [3:0] audio_ch1, audio_ch2;
|
||||
wire hs, vs, hb, vb;
|
||||
wire blankn = ~(hb | vb);
|
||||
wire [7:0] r, g, b;
|
||||
wire key_strobe;
|
||||
wire key_pressed;
|
||||
wire [7:0] key_code;
|
||||
wire [31:0] joystick_0, joystick_1;
|
||||
wire [15:0] rom_addr;
|
||||
wire [15:0] rom_do;
|
||||
wire ioctl_downl;
|
||||
wire [7:0] ioctl_index;
|
||||
wire ioctl_wr;
|
||||
wire [24:0] ioctl_addr;
|
||||
wire [7:0] ioctl_dout;
|
||||
|
||||
data_io data_io(
|
||||
.clk_sys ( clk_sys ),
|
||||
.SPI_SCK ( SPI_SCK ),
|
||||
.SPI_SS2 ( SPI_SS2 ),
|
||||
.SPI_DI ( SPI_DI ),
|
||||
.ioctl_download( ioctl_downl ),
|
||||
.ioctl_index ( ioctl_index ),
|
||||
.ioctl_wr ( ioctl_wr ),
|
||||
.ioctl_addr ( ioctl_addr ),
|
||||
.ioctl_dout ( ioctl_dout )
|
||||
);
|
||||
|
||||
reg port1_req;
|
||||
sdram sdram(
|
||||
.*,
|
||||
.init_n ( pll_locked ),
|
||||
.clk ( clk_sys ),
|
||||
|
||||
// port1 used for main CPU
|
||||
.port1_req ( port1_req ),
|
||||
.port1_ack ( ),
|
||||
.port1_a ( ioctl_addr[23:1] ),
|
||||
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
|
||||
.port1_we ( ioctl_downl ),
|
||||
.port1_d ( {ioctl_dout, ioctl_dout} ),
|
||||
.port1_q ( ),
|
||||
|
||||
.cpu1_addr ( ioctl_downl ? 16'hffff : {1'b0, rom_addr[15:1]}),
|
||||
.cpu1_q ( rom_do )
|
||||
);
|
||||
|
||||
always @(posedge clk_sys) begin
|
||||
reg ioctl_wr_last = 0;
|
||||
|
||||
ioctl_wr_last <= ioctl_wr;
|
||||
if (ioctl_downl) begin
|
||||
if (~ioctl_wr_last && ioctl_wr) begin
|
||||
port1_req <= ~port1_req;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg reset = 1;
|
||||
reg rom_loaded = 0;
|
||||
always @(posedge clk_sys) begin
|
||||
reg ioctl_downlD;
|
||||
ioctl_downlD <= ioctl_downl;
|
||||
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
|
||||
reset <= status[0] | buttons[1] | ~rom_loaded;
|
||||
end
|
||||
|
||||
Supervision_Top Supervision_Top(
|
||||
.clk_sys(clk_sys),
|
||||
.clk_vid(clk_vid),
|
||||
.clk_cpu(clk_cpu),
|
||||
.reset(reset),
|
||||
.hsync(hs),
|
||||
.vsync(vs),
|
||||
.hblank(hb),
|
||||
.vblank(vb),
|
||||
.white(status[8]),
|
||||
.red(r),
|
||||
.green(g),
|
||||
.blue(b),
|
||||
.joystick({m_fireA, m_fireB, m_fireC, m_fireD, m_up, m_down, m_left, m_right}),
|
||||
.audio_ch1(audio_ch1),
|
||||
.audio_ch2(audio_ch2),
|
||||
.cpu_rom_addr(rom_addr),
|
||||
.cpu_rom_data(rom_addr[0] ? rom_do[15:8] : rom_do[7:0])
|
||||
);
|
||||
|
||||
mist_video #(.COLOR_DEPTH(6),.SD_HCNT_WIDTH(9)) mist_video(
|
||||
.clk_sys(clk_vid),
|
||||
.SPI_SCK(SPI_SCK),
|
||||
.SPI_SS3(SPI_SS3),
|
||||
.SPI_DI(SPI_DI),
|
||||
.R(blankn ? r[7:2] : 0),
|
||||
.G(blankn ? g[7:2] : 0),
|
||||
.B(blankn ? b[7:2] : 0),
|
||||
.HSync(~hs),
|
||||
.VSync(~vs),
|
||||
.VGA_R(VGA_R),
|
||||
.VGA_G(VGA_G),
|
||||
.VGA_B(VGA_B),
|
||||
.VGA_VS(VGA_VS),
|
||||
.VGA_HS(VGA_HS),
|
||||
.ce_divider(1'b0),
|
||||
.blend(status[5]),
|
||||
.scandoubler_disable(1'b1),//scandoublerD),
|
||||
.scanlines(status[4:3]),
|
||||
.ypbpr(ypbpr)
|
||||
);
|
||||
|
||||
user_io #(
|
||||
.STRLEN(($size(CONF_STR)>>3)))
|
||||
user_io(
|
||||
.clk_sys (clk_sys ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_CLK (SPI_SCK ),
|
||||
.SPI_SS_IO (CONF_DATA0 ),
|
||||
.SPI_MISO (SPI_DO ),
|
||||
.SPI_MOSI (SPI_DI ),
|
||||
.buttons (buttons ),
|
||||
.switches (switches ),
|
||||
.scandoubler_disable (scandoublerD ),
|
||||
.ypbpr (ypbpr ),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_code (key_code ),
|
||||
.joystick_0 (joystick_0 ),
|
||||
.joystick_1 (joystick_1 ),
|
||||
.status (status )
|
||||
);
|
||||
|
||||
dac #(
|
||||
.C_bits(4))
|
||||
dac_l(
|
||||
.clk_i(clk_sys),
|
||||
.res_n_i(1),
|
||||
.dac_i(audio_ch2),
|
||||
.dac_o(AUDIO_L)
|
||||
);
|
||||
|
||||
dac #(
|
||||
.C_bits(4))
|
||||
dac_r(
|
||||
.clk_i(clk_sys),
|
||||
.res_n_i(1),
|
||||
.dac_i(audio_ch1),
|
||||
.dac_o(AUDIO_R)
|
||||
);
|
||||
|
||||
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
|
||||
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
|
||||
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
|
||||
|
||||
arcade_inputs inputs (
|
||||
.clk ( clk_sys ),
|
||||
.key_strobe ( key_strobe ),
|
||||
.key_pressed ( key_pressed ),
|
||||
.key_code ( key_code ),
|
||||
.joystick_0 ( joystick_0 ),
|
||||
//.rotate ( rotate ),
|
||||
//.orientation ( orientation ),
|
||||
.joyswap ( status[6] ),
|
||||
.oneplayer ( 1'b1 ),
|
||||
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
|
||||
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
|
||||
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
|
||||
);
|
||||
|
||||
endmodule
|
||||
332
Console_MiST/Supervision_MiST/rtl/Supervision_Top.sv
Normal file
332
Console_MiST/Supervision_MiST/rtl/Supervision_Top.sv
Normal file
@@ -0,0 +1,332 @@
|
||||
module Supervision_Top(
|
||||
input clk_sys,//50
|
||||
input clk_vid,// 25.175
|
||||
input clk_cpu,//4
|
||||
input reset,
|
||||
output hsync,
|
||||
output vsync,
|
||||
output hblank,
|
||||
output vblank,
|
||||
input white,
|
||||
output [7:0] red,
|
||||
output [7:0] green,
|
||||
output [7:0] blue,
|
||||
output [3:0] audio_ch1,
|
||||
output [3:0] audio_ch2,
|
||||
input [7:0] joystick,
|
||||
output [15:0]cpu_rom_addr,
|
||||
input [7:0] cpu_rom_data
|
||||
);
|
||||
|
||||
reg [15:0] nmi_clk;
|
||||
//wire clk_cpu;
|
||||
wire nmi = nmi_clk == 0;
|
||||
always @(posedge clk_cpu)
|
||||
nmi_clk <= nmi_clk + 16'b1;
|
||||
|
||||
reg [7:0] sys_ctl;
|
||||
reg [7:0] irq_timer; // 2023
|
||||
reg [7:0] irq_status; // 2027 ??????DT 1=expired/finished
|
||||
reg irq_tim;
|
||||
reg irq_dma;
|
||||
|
||||
wire [15:0] cpu_addr;
|
||||
wire [7:0] cpu_dout;
|
||||
wire [7:0] wram_dout;
|
||||
wire [7:0] vram_dout;
|
||||
wire [7:0] rom_dout;
|
||||
wire [7:0] sys_dout;
|
||||
|
||||
reg [7:0] dma_src_lo;
|
||||
reg [7:0] dma_src_hi;
|
||||
reg [7:0] dma_dst_lo;
|
||||
reg [7:0] dma_dst_hi;
|
||||
reg [7:0] dma_length;
|
||||
reg [7:0] dma_ctrl;
|
||||
wire [7:0] dma_dout;
|
||||
wire [13:0] dma_addr;
|
||||
wire dma_busy;
|
||||
wire dma_sel;
|
||||
wire dma_write;
|
||||
|
||||
reg [7:0] lcd_xscroll;
|
||||
reg [7:0] lcd_yscroll;
|
||||
reg [7:0] lcd_xsize;
|
||||
reg [7:0] lcd_ysize;
|
||||
wire [7:0] lcd_din;
|
||||
wire lcd_pulse;
|
||||
wire cpu_rdy = ~dma_busy;
|
||||
wire dma_rdy = ~lcd_pulse;
|
||||
wire cpu_we;
|
||||
wire [15:0] lcd_addr;
|
||||
|
||||
reg [7:0] ch1_freq_hi, ch1_freq_low, ch1_length, ch1_vduty;
|
||||
reg [7:0] ch2_freq_hi, ch2_freq_low, ch2_length, ch2_vduty;
|
||||
reg [7:0] audio_dma_addr_low, audio_dma_addr_high;
|
||||
reg [7:0] audio_dma_ctrl, audio_dma_length, audio_dma_trigger;
|
||||
reg [7:0] noise_ctrl, noise_freq_vol, noise_length;
|
||||
//wire [3:0] audio_ch1, audio_ch2;
|
||||
|
||||
////////////////////// IRQ //////////////////////////
|
||||
reg [13:0] timer_div;
|
||||
|
||||
// irq_tim
|
||||
always @(posedge clk_sys)
|
||||
if (sys_ctl[1]) begin // irq enable flag
|
||||
if (irq_timer == 0 && ~irq_status[0]) irq_tim <= 1;
|
||||
else if (sys_cs && cpu_we && AB[2:0] == 3'h3 && cpu_dout == 0) irq_tim <= 1;
|
||||
else irq_tim <= 0;
|
||||
end
|
||||
|
||||
// irq status
|
||||
always @(posedge clk_sys)
|
||||
if (sys_cs && ~cpu_we && AB[2:0] == 3'h4) // write to irq timer ack
|
||||
irq_status[0] <= 1'b0;
|
||||
else if (irq_tim) // change status on irq
|
||||
irq_status[0] <= 1'b1;
|
||||
|
||||
// timer prescaler
|
||||
always @(posedge clk_cpu)
|
||||
if (timer_div > 0)
|
||||
timer_div <= timer_div - 14'b1;
|
||||
else if (sys_ctl[4])
|
||||
timer_div <= 14'h3fff;
|
||||
else
|
||||
timer_div <= 14'hff;
|
||||
|
||||
// irq_timer
|
||||
always @(posedge clk_cpu)
|
||||
if (sys_cs && cpu_we && AB[2:0] == 3'h3)
|
||||
irq_timer <= cpu_dout;
|
||||
else if (timer_div == 0 && irq_timer > 0)
|
||||
irq_timer <= irq_timer - 8'b1;
|
||||
|
||||
|
||||
/////////////////////////// MEMORY MAP /////////////////////
|
||||
|
||||
// 0000 - 1FFF - WRAM
|
||||
// 2000 - 202F - CTRL
|
||||
// 2030 - 3FFF - CTRL - mirrors ??
|
||||
// 4000 - 5FFF - VRAM ??
|
||||
// 6000 - 7FFF - VRAM - mirrors ??
|
||||
// 8000 - BFFF - banks
|
||||
// C000 - FFFF - last 16k of cartridge
|
||||
|
||||
|
||||
wire wram_cs = AB ==? 16'b000x_xxxx_xxxx_xxxx;
|
||||
wire lcd_cs = AB ==? 16'b0010_0000_0000_0xxx; // match 2000-2007 LCD control registers
|
||||
wire dma_cs = AB ==? 16'b0010_0000_0000_1xxx; // match 2008-200F DMA control registers
|
||||
wire snd_cs = AB ==? 16'b0010_0000_0001_xxxx; // match 2010-201F sound registers
|
||||
wire sys_cs = AB ==? 16'b0010_0000_0010_0xxx; // match 2020-2027 sys registers
|
||||
wire noi_cs = AB ==? 16'b0010_0000_0010_1xxx; // match 2028-202F sound registers (noise)
|
||||
wire vram_cs = AB ==? 16'b01xx_xxxx_xxxx_xxxx;
|
||||
wire rom_cs = AB ==? 16'b1xxx_xxxx_xxxx_xxxx;
|
||||
wire rom_hi = AB ==? 16'b11xx_xxxx_xxxx_xxxx;
|
||||
|
||||
wire [15:0] AB = dma_busy ? { 2'b0, dma_addr } : cpu_addr;
|
||||
|
||||
reg [7:0] DI;
|
||||
|
||||
wire [7:0] DO = dma_busy ? dma_dout : cpu_dout;
|
||||
wire wram_we = wram_cs ? dma_busy ? ~dma_write : ~cpu_we : 1'b1;
|
||||
wire vram_we = vram_cs ? dma_busy ? ~dma_write : ~cpu_we : 1'b1;
|
||||
|
||||
wire [15:0] rom_addr = rom_hi ? AB : { sys_ctl[6:5], AB[13:0] };
|
||||
|
||||
always @(posedge clk_cpu)
|
||||
DI <= sys_cs ? sys_dout :
|
||||
wram_cs ? wram_dout :
|
||||
vram_cs ? vram_dout :
|
||||
rom_cs ? rom_dout : 8'hff;
|
||||
|
||||
// write to lcd registers
|
||||
always @(posedge clk_sys)
|
||||
if (lcd_cs && cpu_we) begin
|
||||
case (AB[1:0])
|
||||
2'h0: lcd_xsize <= cpu_dout;
|
||||
2'h1: lcd_ysize <= cpu_dout;
|
||||
2'h2: lcd_xscroll <= cpu_dout;
|
||||
2'h3: lcd_yscroll <= cpu_dout;
|
||||
endcase
|
||||
end
|
||||
|
||||
// write to audio registers
|
||||
always @(posedge clk_sys)
|
||||
if (snd_cs && cpu_we) begin
|
||||
case (AB[3:0])
|
||||
4'h0: ch1_freq_low <= cpu_dout;
|
||||
4'h1: ch1_freq_hi <= cpu_dout;
|
||||
4'h2: ch1_vduty <= cpu_dout;
|
||||
4'h3: ch1_length <= cpu_dout;
|
||||
4'h4: ch2_freq_low <= cpu_dout;
|
||||
4'h5: ch2_freq_hi <= cpu_dout;
|
||||
4'h6: ch2_vduty <= cpu_dout;
|
||||
4'h7: ch2_length <= cpu_dout;
|
||||
4'h8: audio_dma_addr_low <= cpu_dout;
|
||||
4'h9: audio_dma_addr_high <= cpu_dout;
|
||||
4'ha: audio_dma_length <= cpu_dout;
|
||||
4'hb: audio_dma_ctrl <= cpu_dout;
|
||||
4'hc: audio_dma_trigger <= cpu_dout;
|
||||
endcase
|
||||
end
|
||||
|
||||
// write to noise registers
|
||||
always @(posedge clk_sys)
|
||||
if (noi_cs && cpu_we) begin
|
||||
case (AB[2:0])
|
||||
3'h0: noise_freq_vol <= cpu_dout;
|
||||
3'h1: noise_length <= cpu_dout;
|
||||
3'h2: noise_ctrl <= cpu_dout;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
// write to dma registers
|
||||
always @(posedge clk_sys)
|
||||
if (dma_cs && cpu_we)
|
||||
case (AB[2:0])
|
||||
3'h0: dma_src_lo <= cpu_dout;
|
||||
3'h1: dma_src_hi <= cpu_dout;
|
||||
3'h2: dma_dst_lo <= cpu_dout;
|
||||
3'h3: dma_dst_hi <= cpu_dout;
|
||||
3'h4: dma_length <= cpu_dout;
|
||||
3'h5: dma_ctrl <= cpu_dout;
|
||||
default:
|
||||
dma_ctrl <= 8'd0;
|
||||
endcase
|
||||
|
||||
// write to sys registers
|
||||
always @(posedge clk_sys)
|
||||
if (sys_cs && cpu_we)
|
||||
case (AB[2:0])
|
||||
// 3'h3: irq_timer = cpu_dout;
|
||||
3'h6: sys_ctl <= cpu_dout;
|
||||
endcase
|
||||
|
||||
// read sys registers
|
||||
always @(posedge clk_sys)
|
||||
if (sys_cs && ~cpu_we)
|
||||
case (AB[2:0])
|
||||
3'h0: sys_dout <= {
|
||||
~joystick[7],
|
||||
~joystick[6],
|
||||
~joystick[5],
|
||||
~joystick[4],
|
||||
~joystick[3],
|
||||
~joystick[2],
|
||||
~joystick[1],
|
||||
~joystick[0]
|
||||
};
|
||||
3'h3: sys_dout <= irq_timer;
|
||||
3'h6: sys_dout <= sys_ctl;
|
||||
endcase
|
||||
|
||||
|
||||
////////////////////////////////////////////////
|
||||
|
||||
|
||||
//rom cart(
|
||||
// .clk(clk_sys),
|
||||
// .addr(rom_addr),
|
||||
// .dout(rom_dout),
|
||||
// .cs(~rom_cs),
|
||||
// .rom_init(ioctl_download),
|
||||
// .rom_init_clk(clk_sys),
|
||||
// .rom_init_address(ioctl_addr),
|
||||
// .rom_init_data(ioctl_dout)
|
||||
//);
|
||||
|
||||
assign cpu_rom_addr = rom_addr;
|
||||
assign rom_dout = cpu_rom_data;
|
||||
|
||||
|
||||
ram88 wram(
|
||||
.clk(clk_sys),
|
||||
.addr(AB[12:0]),
|
||||
.din(DO), // <= cpu or dma
|
||||
.dout(wram_dout),
|
||||
.we(wram_we),
|
||||
.cs(~wram_cs)
|
||||
);
|
||||
|
||||
// dual port ram
|
||||
ram88 vram(
|
||||
.clk(clk_sys),
|
||||
.addr(AB[12:0]),
|
||||
.din(DO), // <= cpu or dma
|
||||
.dout(vram_dout),
|
||||
.addrb(lcd_addr),
|
||||
.doutb(lcd_din),
|
||||
.we(vram_we),
|
||||
.cs(~vram_cs)
|
||||
);
|
||||
|
||||
dma dma(
|
||||
.clk(clk_sys),
|
||||
.rdy(dma_rdy),
|
||||
.irq_dma(irq_dma),
|
||||
.ctrl(dma_ctrl),
|
||||
.src_addr({ dma_src_hi, dma_src_lo }),
|
||||
.dst_addr({ dma_dst_hi, dma_dst_lo }),
|
||||
.addr(dma_addr), // => to AB
|
||||
.din(DI),
|
||||
.dout(dma_dout),
|
||||
.length(dma_length),
|
||||
.busy(dma_busy),
|
||||
.sel(dma_sel),
|
||||
.write(dma_write)
|
||||
);
|
||||
|
||||
audio audio(
|
||||
.clk(clk_sys),
|
||||
.CH1_freq({ ch1_freq_hi[2:0], ch1_freq_low }),
|
||||
.CH1_vduty(ch1_vduty),
|
||||
.CH1_length(ch1_length),
|
||||
.CH2_freq({ ch2_freq_hi[2:0], ch2_freq_low }),
|
||||
.CH2_vduty(ch2_vduty),
|
||||
.CH2_length(ch2_length),
|
||||
.DMA_addr({ audio_dma_addr_high, audio_dma_addr_low }),
|
||||
.DMA_length(audio_dma_length),
|
||||
.DMA_ctrl(audio_dma_ctrl),
|
||||
.DMA_trigger(audio_dma_trigger),
|
||||
.noise_freq_vol(noise_freq_vol),
|
||||
.noise_length(noise_length),
|
||||
.noise_ctrl(noise_ctrl),
|
||||
.CH1(audio_ch1),
|
||||
.CH2(audio_ch2)
|
||||
);
|
||||
|
||||
video video(
|
||||
.clk(clk_vid),
|
||||
.ce(sys_ctl[3]),
|
||||
.white(white),
|
||||
.lcd_xsize(lcd_xsize),
|
||||
.lcd_ysize(lcd_ysize),
|
||||
.lcd_xscroll(lcd_xscroll),
|
||||
.lcd_yscroll(lcd_yscroll),
|
||||
.lcd_pulse(lcd_pulse),
|
||||
.addr(lcd_addr),
|
||||
.data(lcd_din),
|
||||
.hsync(hsync),
|
||||
.vsync(vsync),
|
||||
.hblank(hblank),
|
||||
.vblank(vblank),
|
||||
.red(red),
|
||||
.green(green),
|
||||
.blue(blue)
|
||||
);
|
||||
|
||||
cpu_65c02 cpu(
|
||||
.clk(clk_cpu),
|
||||
.reset(reset),
|
||||
.AB(cpu_addr),
|
||||
.DI(DI),
|
||||
.DO(cpu_dout),
|
||||
.WE(cpu_we),
|
||||
.IRQ(irq_tim | irq_dma),
|
||||
.NMI(nmi),
|
||||
.RDY(cpu_rdy)
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
102
Console_MiST/Supervision_MiST/rtl/audio.sv
Normal file
102
Console_MiST/Supervision_MiST/rtl/audio.sv
Normal file
@@ -0,0 +1,102 @@
|
||||
|
||||
module audio (
|
||||
input clk, // clk_sys
|
||||
|
||||
input [9:0] CH1_freq,
|
||||
input [7:0] CH1_vduty,
|
||||
input [7:0] CH1_length,
|
||||
|
||||
input [9:0] CH2_freq,
|
||||
input [7:0] CH2_vduty,
|
||||
input [7:0] CH2_length,
|
||||
|
||||
input [7:0] DMA_addr,
|
||||
input [7:0] DMA_length,
|
||||
input [7:0] DMA_ctrl,
|
||||
input [7:0] DMA_trigger,
|
||||
|
||||
input [7:0] noise_freq_vol,
|
||||
input [7:0] noise_length,
|
||||
input [7:0] noise_ctrl,
|
||||
|
||||
output [3:0] CH1,
|
||||
output [3:0] CH2
|
||||
);
|
||||
|
||||
|
||||
|
||||
reg [23:0] clk_cnt;
|
||||
reg pulse;
|
||||
reg clk_audio;
|
||||
reg [15:0] prescaler;
|
||||
reg prescaler_overflow;
|
||||
|
||||
// 50000/125=400/2=200 2^24/200=83886
|
||||
always @(posedge clk)
|
||||
{ pulse, clk_cnt } <= clk_cnt + 24'd83886;
|
||||
|
||||
always @(posedge pulse)
|
||||
clk_audio <= ~clk_audio;
|
||||
|
||||
always @(posedge clk)
|
||||
{ prescaler_overflow, prescaler } <= prescaler + 16'd1;
|
||||
|
||||
reg [16:0] CH1_sum, CH2_sum;
|
||||
reg [16:0] CH1_dc, CH2_dc; // duty cycle
|
||||
reg CH1_sw, CH2_sw; // square wave
|
||||
reg [7:0] CH1_dlength, CH2_dlength, CH1_timer, CH2_timer;
|
||||
|
||||
wire [3:0] CH1_out = CH1_sw ? CH1_vduty[3:0] : 4'd0;
|
||||
wire [3:0] CH2_out = CH2_sw ? CH2_vduty[3:0] : 4'd0;
|
||||
wire CH1_en = CH1_timer || CH1_vduty[6] ? 1'b1 : 1'b0;
|
||||
wire CH2_en = CH2_timer || CH2_vduty[6] ? 1'b1 : 1'b0;
|
||||
assign CH1 = CH1_en ? CH1_out : 4'd0;
|
||||
assign CH2 = CH2_en ? CH2_out : 4'd0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (prescaler_overflow && CH1_timer > 8'd0) CH1_timer <= CH1_timer - 8'd1;
|
||||
if (prescaler_overflow && CH2_timer > 8'd0) CH2_timer <= CH2_length - 8'd1;
|
||||
if (CH1_dlength != CH1_length) begin
|
||||
CH1_dlength <= CH1_length;
|
||||
CH1_timer <= CH1_length;
|
||||
end
|
||||
if (CH2_dlength != CH2_length) begin
|
||||
CH2_dlength <= CH2_length;
|
||||
CH2_timer <= CH2_length;
|
||||
end
|
||||
end
|
||||
|
||||
always @*
|
||||
case (CH1_vduty[5:4])
|
||||
2'b00: CH1_dc = 17'd15240; // 12.5%
|
||||
2'b01: CH1_dc = 17'd31750; // 25%
|
||||
2'b10: CH1_dc = 17'd63500; // 50%
|
||||
2'b11: CH1_dc = 17'd95250; // 75%
|
||||
endcase
|
||||
|
||||
always @*
|
||||
case (CH2_vduty[5:4])
|
||||
2'b00: CH2_dc = 17'd15240; // 12.5%
|
||||
2'b01: CH2_dc = 17'd31750; // 25%
|
||||
2'b10: CH2_dc = 17'd63500; // 50%
|
||||
2'b11: CH2_dc = 17'd95250; // 75%
|
||||
endcase
|
||||
|
||||
always @(posedge clk_audio) begin
|
||||
CH1_sum <= CH1_sum + { 7'd0, CH1_freq };
|
||||
if (CH1_sum >= CH1_dc) begin
|
||||
CH1_sum <= 17'd0;
|
||||
CH1_sw = ~CH1_sw;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_audio) begin
|
||||
CH2_sum <= CH2_sum + { 7'd0, CH2_freq };
|
||||
if (CH2_sum >= CH2_dc) begin
|
||||
CH2_sum <= 17'd0;
|
||||
CH2_sw = ~CH2_sw;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
35
Console_MiST/Supervision_MiST/rtl/build_id.tcl
Normal file
35
Console_MiST/Supervision_MiST/rtl/build_id.tcl
Normal file
@@ -0,0 +1,35 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
|
||||
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "rtl/build_id.v"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
# Output the Verilog source
|
||||
puts $outputFile "`define BUILD_DATE \"$buildDate\""
|
||||
puts $outputFile "`define BUILD_TIME \"$buildTime\""
|
||||
close $outputFile
|
||||
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
|
||||
post_message "Date: $buildDate"
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
77
Console_MiST/Supervision_MiST/rtl/dma.sv
Normal file
77
Console_MiST/Supervision_MiST/rtl/dma.sv
Normal file
@@ -0,0 +1,77 @@
|
||||
|
||||
module dma(
|
||||
input clk, // 4 x CPU speed ?
|
||||
input rdy,
|
||||
output irq_dma,
|
||||
input [7:0] ctrl,
|
||||
input [15:0] src_addr,
|
||||
input [15:0] dst_addr,
|
||||
output reg [15:0] addr,
|
||||
input [7:0] din,
|
||||
output reg [7:0] dout,
|
||||
input [7:0] length,
|
||||
output busy,
|
||||
output sel, // 1: src -> dst, 2: src <- dst
|
||||
output write
|
||||
);
|
||||
|
||||
reg [11:0] queue;
|
||||
reg [12:0] addr_a, addr_b;
|
||||
reg started;
|
||||
assign irq_dma = 1'b1;
|
||||
|
||||
assign sel = dst_addr[14];
|
||||
assign busy = state != DONE;
|
||||
assign write = state == WRITE;
|
||||
reg [1:0] state;
|
||||
|
||||
parameter
|
||||
DONE = 2'b00,
|
||||
START = 2'b01,
|
||||
READ = 2'b10,
|
||||
WRITE = 2'b11;
|
||||
|
||||
always @(posedge clk)
|
||||
started <= ctrl[7] ? 1'b1 : 1'b0;
|
||||
|
||||
always @(posedge clk)
|
||||
if (rdy)
|
||||
case (state)
|
||||
DONE: if (~started & ctrl[7]) state <= START;
|
||||
START: state <= READ;
|
||||
READ: state <= WRITE;
|
||||
WRITE: state <= queue == 0 ? DONE : READ;
|
||||
endcase
|
||||
|
||||
always @(posedge clk)
|
||||
if (rdy)
|
||||
case (state)
|
||||
START: queue <= { length, 4'd0 };
|
||||
WRITE: queue <= queue - 12'b1;
|
||||
endcase
|
||||
|
||||
always @(posedge clk)
|
||||
if (rdy)
|
||||
case (state)
|
||||
READ: addr <= addr_a;
|
||||
WRITE: addr <= addr_b;
|
||||
endcase
|
||||
|
||||
always @(posedge clk)
|
||||
if (rdy && state == WRITE) dout <= din;
|
||||
|
||||
always @(posedge clk)
|
||||
if (rdy)
|
||||
case (state)
|
||||
START: begin
|
||||
addr_a <= sel ? src_addr[12:0] : dst_addr[12:0];
|
||||
addr_b <= sel ? dst_addr[12:0] : src_addr[12:0];
|
||||
end
|
||||
WRITE: begin
|
||||
addr_a <= addr_a + 13'b1;
|
||||
addr_b <= addr_b + 13'b1;
|
||||
end
|
||||
endcase
|
||||
|
||||
|
||||
endmodule
|
||||
348
Console_MiST/Supervision_MiST/rtl/pll1.v
Normal file
348
Console_MiST/Supervision_MiST/rtl/pll1.v
Normal file
@@ -0,0 +1,348 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll1.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.4 Build 182 03/12/2014 SJ Full Version
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2014 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll1 (
|
||||
areset,
|
||||
inclk0,
|
||||
c0,
|
||||
c1,
|
||||
locked);
|
||||
|
||||
input areset;
|
||||
input inclk0;
|
||||
output c0;
|
||||
output c1;
|
||||
output locked;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 areset;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire [4:0] sub_wire0;
|
||||
wire sub_wire2;
|
||||
wire [0:0] sub_wire6 = 1'h0;
|
||||
wire [0:0] sub_wire3 = sub_wire0[0:0];
|
||||
wire [1:1] sub_wire1 = sub_wire0[1:1];
|
||||
wire c1 = sub_wire1;
|
||||
wire locked = sub_wire2;
|
||||
wire c0 = sub_wire3;
|
||||
wire sub_wire4 = inclk0;
|
||||
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
|
||||
|
||||
altpll altpll_component (
|
||||
.areset (areset),
|
||||
.inclk (sub_wire5),
|
||||
.clk (sub_wire0),
|
||||
.locked (sub_wire2),
|
||||
.activeclock (),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 9,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 20,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.clk1_divide_by = 27,
|
||||
altpll_component.clk1_duty_cycle = 50,
|
||||
altpll_component.clk1_multiply_by = 4,
|
||||
altpll_component.clk1_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll1",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_USED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_USED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_USED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.self_reset_on_loss_lock = "OFF",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "60.000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "4.000000"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "20"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "60.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "4.00000000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "20"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
|
||||
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
|
||||
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll1_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
320
Console_MiST/Supervision_MiST/rtl/pll2.v
Normal file
320
Console_MiST/Supervision_MiST/rtl/pll2.v
Normal file
@@ -0,0 +1,320 @@
|
||||
// megafunction wizard: %ALTPLL%
|
||||
// GENERATION: STANDARD
|
||||
// VERSION: WM1.0
|
||||
// MODULE: altpll
|
||||
|
||||
// ============================================================
|
||||
// File Name: pll2.v
|
||||
// Megafunction Name(s):
|
||||
// altpll
|
||||
//
|
||||
// Simulation Library Files(s):
|
||||
// altera_mf
|
||||
// ============================================================
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
//
|
||||
// 13.1.4 Build 182 03/12/2014 SJ Full Version
|
||||
// ************************************************************
|
||||
|
||||
|
||||
//Copyright (C) 1991-2014 Altera Corporation
|
||||
//Your use of Altera Corporation's design tools, logic functions
|
||||
//and other software and tools, and its AMPP partner logic
|
||||
//functions, and any output files from any of the foregoing
|
||||
//(including device programming or simulation files), and any
|
||||
//associated documentation or information are expressly subject
|
||||
//to the terms and conditions of the Altera Program License
|
||||
//Subscription Agreement, Altera MegaCore Function License
|
||||
//Agreement, or other applicable license agreement, including,
|
||||
//without limitation, that your use is for the sole purpose of
|
||||
//programming logic devices manufactured by Altera and sold by
|
||||
//Altera or its authorized distributors. Please refer to the
|
||||
//applicable agreement for further details.
|
||||
|
||||
|
||||
// synopsys translate_off
|
||||
`timescale 1 ps / 1 ps
|
||||
// synopsys translate_on
|
||||
module pll2 (
|
||||
areset,
|
||||
inclk0,
|
||||
c0,
|
||||
locked);
|
||||
|
||||
input areset;
|
||||
input inclk0;
|
||||
output c0;
|
||||
output locked;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_off
|
||||
`endif
|
||||
tri0 areset;
|
||||
`ifndef ALTERA_RESERVED_QIS
|
||||
// synopsys translate_on
|
||||
`endif
|
||||
|
||||
wire sub_wire0;
|
||||
wire [4:0] sub_wire1;
|
||||
wire [0:0] sub_wire5 = 1'h0;
|
||||
wire locked = sub_wire0;
|
||||
wire [0:0] sub_wire2 = sub_wire1[0:0];
|
||||
wire c0 = sub_wire2;
|
||||
wire sub_wire3 = inclk0;
|
||||
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
|
||||
|
||||
altpll altpll_component (
|
||||
.areset (areset),
|
||||
.inclk (sub_wire4),
|
||||
.locked (sub_wire0),
|
||||
.clk (sub_wire1),
|
||||
.activeclock (),
|
||||
.clkbad (),
|
||||
.clkena ({6{1'b1}}),
|
||||
.clkloss (),
|
||||
.clkswitch (1'b0),
|
||||
.configupdate (1'b0),
|
||||
.enable0 (),
|
||||
.enable1 (),
|
||||
.extclk (),
|
||||
.extclkena ({4{1'b1}}),
|
||||
.fbin (1'b1),
|
||||
.fbmimicbidir (),
|
||||
.fbout (),
|
||||
.fref (),
|
||||
.icdrclk (),
|
||||
.pfdena (1'b1),
|
||||
.phasecounterselect ({4{1'b1}}),
|
||||
.phasedone (),
|
||||
.phasestep (1'b1),
|
||||
.phaseupdown (1'b1),
|
||||
.pllena (1'b1),
|
||||
.scanaclr (1'b0),
|
||||
.scanclk (1'b0),
|
||||
.scanclkena (1'b1),
|
||||
.scandata (1'b0),
|
||||
.scandataout (),
|
||||
.scandone (),
|
||||
.scanread (1'b0),
|
||||
.scanwrite (1'b0),
|
||||
.sclkout0 (),
|
||||
.sclkout1 (),
|
||||
.vcooverrange (),
|
||||
.vcounderrange ());
|
||||
defparam
|
||||
altpll_component.bandwidth_type = "AUTO",
|
||||
altpll_component.clk0_divide_by = 44,
|
||||
altpll_component.clk0_duty_cycle = 50,
|
||||
altpll_component.clk0_multiply_by = 41,
|
||||
altpll_component.clk0_phase_shift = "0",
|
||||
altpll_component.compensate_clock = "CLK0",
|
||||
altpll_component.inclk0_input_frequency = 37037,
|
||||
altpll_component.intended_device_family = "Cyclone III",
|
||||
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll2",
|
||||
altpll_component.lpm_type = "altpll",
|
||||
altpll_component.operation_mode = "NORMAL",
|
||||
altpll_component.pll_type = "AUTO",
|
||||
altpll_component.port_activeclock = "PORT_UNUSED",
|
||||
altpll_component.port_areset = "PORT_USED",
|
||||
altpll_component.port_clkbad0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkbad1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkloss = "PORT_UNUSED",
|
||||
altpll_component.port_clkswitch = "PORT_UNUSED",
|
||||
altpll_component.port_configupdate = "PORT_UNUSED",
|
||||
altpll_component.port_fbin = "PORT_UNUSED",
|
||||
altpll_component.port_inclk0 = "PORT_USED",
|
||||
altpll_component.port_inclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_locked = "PORT_USED",
|
||||
altpll_component.port_pfdena = "PORT_UNUSED",
|
||||
altpll_component.port_phasecounterselect = "PORT_UNUSED",
|
||||
altpll_component.port_phasedone = "PORT_UNUSED",
|
||||
altpll_component.port_phasestep = "PORT_UNUSED",
|
||||
altpll_component.port_phaseupdown = "PORT_UNUSED",
|
||||
altpll_component.port_pllena = "PORT_UNUSED",
|
||||
altpll_component.port_scanaclr = "PORT_UNUSED",
|
||||
altpll_component.port_scanclk = "PORT_UNUSED",
|
||||
altpll_component.port_scanclkena = "PORT_UNUSED",
|
||||
altpll_component.port_scandata = "PORT_UNUSED",
|
||||
altpll_component.port_scandataout = "PORT_UNUSED",
|
||||
altpll_component.port_scandone = "PORT_UNUSED",
|
||||
altpll_component.port_scanread = "PORT_UNUSED",
|
||||
altpll_component.port_scanwrite = "PORT_UNUSED",
|
||||
altpll_component.port_clk0 = "PORT_USED",
|
||||
altpll_component.port_clk1 = "PORT_UNUSED",
|
||||
altpll_component.port_clk2 = "PORT_UNUSED",
|
||||
altpll_component.port_clk3 = "PORT_UNUSED",
|
||||
altpll_component.port_clk4 = "PORT_UNUSED",
|
||||
altpll_component.port_clk5 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena0 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena1 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena2 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena3 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena4 = "PORT_UNUSED",
|
||||
altpll_component.port_clkena5 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk0 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk1 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk2 = "PORT_UNUSED",
|
||||
altpll_component.port_extclk3 = "PORT_UNUSED",
|
||||
altpll_component.self_reset_on_loss_lock = "OFF",
|
||||
altpll_component.width_clock = 5;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// ============================================================
|
||||
// CNX file retrieval info
|
||||
// ============================================================
|
||||
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "44"
|
||||
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.159090"
|
||||
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "41"
|
||||
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.17500000"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||||
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "44"
|
||||
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "41"
|
||||
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
|
||||
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
|
||||
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.v TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.ppf TRUE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.inc FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.cmp FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll2.bsf FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_inst.v FALSE
|
||||
// Retrieval info: GEN_FILE: TYPE_NORMAL pll2_bb.v FALSE
|
||||
// Retrieval info: LIB_FILE: altera_mf
|
||||
// Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
23
Console_MiST/Supervision_MiST/rtl/ram88.sv
Normal file
23
Console_MiST/Supervision_MiST/rtl/ram88.sv
Normal file
@@ -0,0 +1,23 @@
|
||||
|
||||
module ram88 (
|
||||
input clk,
|
||||
input [12:0] addr,
|
||||
input [12:0] addrb,
|
||||
input [7:0] din,
|
||||
input we,
|
||||
input cs,
|
||||
output reg [7:0] dout,
|
||||
output reg [7:0] doutb
|
||||
);
|
||||
|
||||
reg [7:0] memory[8191:0] /*verilator public_flat_rd*/;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (~cs) begin
|
||||
if (~we) memory[addr] <= din;
|
||||
dout <= memory[addr];
|
||||
end
|
||||
doutb <= memory[addrb];
|
||||
end
|
||||
|
||||
endmodule
|
||||
22
Console_MiST/Supervision_MiST/rtl/rom.v
Normal file
22
Console_MiST/Supervision_MiST/rtl/rom.v
Normal file
@@ -0,0 +1,22 @@
|
||||
|
||||
module rom (
|
||||
input clk,
|
||||
input [15:0] addr,
|
||||
output reg [7:0] dout,
|
||||
input cs,
|
||||
input rom_init,
|
||||
input rom_init_clk,
|
||||
input [15:0] rom_init_address,
|
||||
input [7:0] rom_init_data
|
||||
);
|
||||
|
||||
reg [7:0] memory[65535:0];
|
||||
|
||||
always @(posedge clk)
|
||||
if (~cs) dout <= memory[addr];
|
||||
|
||||
always @(posedge rom_init_clk)
|
||||
if (rom_init)
|
||||
memory[rom_init_address] <= rom_init_data;
|
||||
|
||||
endmodule
|
||||
242
Console_MiST/Supervision_MiST/rtl/sdram.sv
Normal file
242
Console_MiST/Supervision_MiST/rtl/sdram.sv
Normal file
@@ -0,0 +1,242 @@
|
||||
//
|
||||
// sdram.v
|
||||
//
|
||||
// sdram controller implementation for the MiST board
|
||||
// https://github.com/mist-devel/mist-board
|
||||
//
|
||||
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
|
||||
// Copyright (c) 2019 Gyorgy Szombathelyi
|
||||
//
|
||||
// This source file is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published
|
||||
// by the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This source file is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
|
||||
module sdram (
|
||||
|
||||
// interface to the MT48LC16M16 chip
|
||||
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
|
||||
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
|
||||
output reg SDRAM_DQML, // two byte masks
|
||||
output reg SDRAM_DQMH, // two byte masks
|
||||
output reg [1:0] SDRAM_BA, // two banks
|
||||
output SDRAM_nCS, // a single chip select
|
||||
output SDRAM_nWE, // write enable
|
||||
output SDRAM_nRAS, // row address select
|
||||
output SDRAM_nCAS, // columns address select
|
||||
|
||||
// cpu/chipset interface
|
||||
input init_n, // init signal after FPGA config to initialize RAM
|
||||
input clk, // sdram clock
|
||||
|
||||
input port1_req,
|
||||
output reg port1_ack,
|
||||
input port1_we,
|
||||
input [23:1] port1_a,
|
||||
input [1:0] port1_ds,
|
||||
input [15:0] port1_d,
|
||||
output [15:0] port1_q,
|
||||
|
||||
input [17:1] cpu1_addr,
|
||||
output reg [15:0] cpu1_q
|
||||
);
|
||||
|
||||
parameter MHZ = 80; // 80 MHz default clock, adjust to calculate the refresh rate correctly
|
||||
|
||||
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
|
||||
localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
|
||||
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
|
||||
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
|
||||
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
|
||||
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
|
||||
|
||||
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
|
||||
|
||||
// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
|
||||
localparam RFRSH_CYCLES = 16'd78*MHZ/10;
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// ------------------------ cycle state machine ------------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
/*
|
||||
SDRAM state machine
|
||||
1 word burst, CL2
|
||||
cmd issued registered
|
||||
0 RAS0 data ready
|
||||
1
|
||||
2 CAS0
|
||||
3
|
||||
4
|
||||
5 DATA0
|
||||
*/
|
||||
|
||||
localparam STATE_RAS0 = 3'd0; // first state in cycle
|
||||
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 2
|
||||
localparam STATE_READ0 = 3'd0; //STATE_CAS0 + CAS_LATENCY + 2'd2; // 6
|
||||
localparam STATE_LAST = 3'd5;
|
||||
|
||||
reg [2:0] t;
|
||||
|
||||
always @(posedge clk) begin
|
||||
t <= t + 1'd1;
|
||||
if (t == STATE_LAST) t <= STATE_RAS0;
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// --------------------------- startup/reset ---------------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
|
||||
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
|
||||
reg [4:0] reset;
|
||||
reg init = 1'b1;
|
||||
always @(posedge clk, negedge init_n) begin
|
||||
if(!init_n) begin
|
||||
reset <= 5'h1f;
|
||||
init <= 1'b1;
|
||||
end else begin
|
||||
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
|
||||
init <= !(reset == 0);
|
||||
end
|
||||
end
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// ------------------ generate ram control signals ---------------------
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
// all possible commands
|
||||
localparam CMD_INHIBIT = 4'b1111;
|
||||
localparam CMD_NOP = 4'b0111;
|
||||
localparam CMD_ACTIVE = 4'b0011;
|
||||
localparam CMD_READ = 4'b0101;
|
||||
localparam CMD_WRITE = 4'b0100;
|
||||
localparam CMD_BURST_TERMINATE = 4'b0110;
|
||||
localparam CMD_PRECHARGE = 4'b0010;
|
||||
localparam CMD_AUTO_REFRESH = 4'b0001;
|
||||
localparam CMD_LOAD_MODE = 4'b0000;
|
||||
|
||||
reg [3:0] sd_cmd; // current command sent to sd ram
|
||||
reg [15:0] sd_din;
|
||||
// drive control signals according to current command
|
||||
assign SDRAM_nCS = sd_cmd[3];
|
||||
assign SDRAM_nRAS = sd_cmd[2];
|
||||
assign SDRAM_nCAS = sd_cmd[1];
|
||||
assign SDRAM_nWE = sd_cmd[0];
|
||||
|
||||
reg [24:1] addr_latch;
|
||||
reg [24:1] addr_latch_next;
|
||||
reg [17:1] addr_last;
|
||||
reg [15:0] din_latch;
|
||||
reg oe_latch;
|
||||
reg we_latch;
|
||||
reg [1:0] ds;
|
||||
|
||||
localparam PORT_NONE = 2'd0;
|
||||
localparam PORT_CPU1 = 2'd1;
|
||||
localparam PORT_REQ = 2'd2;
|
||||
|
||||
reg [2:0] next_port;
|
||||
reg [2:0] port;
|
||||
reg port1_state;
|
||||
|
||||
// PORT1
|
||||
always @(*) begin
|
||||
if (port1_req ^ port1_state) begin
|
||||
next_port = PORT_REQ;
|
||||
addr_latch_next = { 1'b0, port1_a };
|
||||
end else if (cpu1_addr != addr_last) begin
|
||||
next_port = PORT_CPU1;
|
||||
addr_latch_next = { 7'd0, cpu1_addr };
|
||||
end else begin
|
||||
next_port = PORT_NONE;
|
||||
addr_latch_next = addr_latch;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
||||
// permanently latch ram data to reduce delays
|
||||
sd_din <= SDRAM_DQ;
|
||||
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
|
||||
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
|
||||
sd_cmd <= CMD_NOP; // default: idle
|
||||
|
||||
if(init) begin
|
||||
// initialization takes place at the end of the reset phase
|
||||
if(t == STATE_RAS0) begin
|
||||
|
||||
if(reset == 15) begin
|
||||
sd_cmd <= CMD_PRECHARGE;
|
||||
SDRAM_A[10] <= 1'b1; // precharge all banks
|
||||
end
|
||||
|
||||
if(reset == 10 || reset == 8) begin
|
||||
sd_cmd <= CMD_AUTO_REFRESH;
|
||||
end
|
||||
|
||||
if(reset == 2) begin
|
||||
sd_cmd <= CMD_LOAD_MODE;
|
||||
SDRAM_A <= MODE;
|
||||
SDRAM_BA <= 2'b00;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
// RAS phase
|
||||
if(t == STATE_RAS0) begin
|
||||
addr_latch <= addr_latch_next;
|
||||
port <= next_port;
|
||||
{ oe_latch, we_latch } <= 2'b00;
|
||||
|
||||
if (next_port != PORT_NONE) begin
|
||||
sd_cmd <= CMD_ACTIVE;
|
||||
SDRAM_A <= addr_latch_next[22:10];
|
||||
SDRAM_BA <= addr_latch_next[24:23];
|
||||
if (next_port == PORT_REQ) begin
|
||||
{ oe_latch, we_latch } <= { ~port1_we, port1_we };
|
||||
ds <= port1_ds;
|
||||
din_latch <= port1_d;
|
||||
port1_state <= port1_req;
|
||||
end else begin
|
||||
{ oe_latch, we_latch } <= 2'b10;
|
||||
ds <= 2'b11;
|
||||
addr_last <= cpu1_addr;
|
||||
end
|
||||
end else begin
|
||||
sd_cmd <= CMD_AUTO_REFRESH;
|
||||
end
|
||||
end
|
||||
|
||||
// CAS phase
|
||||
if(t == STATE_CAS0 && (we_latch || oe_latch)) begin
|
||||
sd_cmd <= we_latch?CMD_WRITE:CMD_READ;
|
||||
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds;
|
||||
if (we_latch) begin
|
||||
SDRAM_DQ <= din_latch;
|
||||
port1_ack <= port1_req;
|
||||
end
|
||||
SDRAM_A <= { 4'b0010, addr_latch[9:1] }; // auto precharge
|
||||
SDRAM_BA <= addr_latch[24:23];
|
||||
end
|
||||
|
||||
// Data returned
|
||||
if(t == STATE_READ0 && oe_latch) begin
|
||||
case(port)
|
||||
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
|
||||
PORT_CPU1: begin cpu1_q <= sd_din; end
|
||||
default: ;
|
||||
endcase;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
88
Console_MiST/Supervision_MiST/rtl/video.sv
Normal file
88
Console_MiST/Supervision_MiST/rtl/video.sv
Normal file
@@ -0,0 +1,88 @@
|
||||
|
||||
module video(
|
||||
|
||||
input clk,//vga
|
||||
input clk7p16,//rgb
|
||||
output ce_pxl,
|
||||
input white,
|
||||
// from lcd ctrl registers
|
||||
input ce,
|
||||
input [7:0] lcd_xsize,
|
||||
input [7:0] lcd_ysize,
|
||||
input [7:0] lcd_xscroll,
|
||||
input [7:0] lcd_yscroll,
|
||||
output lcd_pulse,
|
||||
|
||||
// to/from vram
|
||||
output [12:0] addr,
|
||||
input [7:0] data,
|
||||
|
||||
// to vga interface
|
||||
output hsync,
|
||||
output vsync,
|
||||
output hblank,
|
||||
output vblank,
|
||||
output reg [7:0] red,
|
||||
output reg [7:0] green,
|
||||
output reg [7:0] blue
|
||||
);
|
||||
|
||||
reg [9:0] hcount;
|
||||
reg [9:0] vcount;
|
||||
assign lcd_pulse = ce_pxl;
|
||||
// VGA industry standard 640x480@60 800 525 31.5 - - 25.2 16 96 48 10 2 33 MHi modelines table
|
||||
// visible area | front porch <sync pulse> back porch
|
||||
// 640 | 32 < 48 > 112
|
||||
assign hsync = ~((hcount >= 672) && (hcount < 720));
|
||||
assign vsync = ~((vcount >= 481) && (vcount < 484));
|
||||
assign hblank = hcount > 639;
|
||||
assign vblank = vcount > 479;
|
||||
|
||||
|
||||
// convert vga coordinates to lcd coordinates (with borders)
|
||||
wire [8:0] vgax = hcount < 640 ? hcount[9:1] : 9'd0; // 0 - 319
|
||||
wire [8:0] vgay = vcount < 480 ? vcount[9:1] : 9'd0; // 0 - 239
|
||||
wire [7:0] lcdx = vgax >= 80 && vgax < 240 ? vgax - 8'd80 : 8'd0; // 0-79(80)|80-239(160)|240-319(80)
|
||||
wire [7:0] lcdy = vgay >= 40 && vgay < 200 ? vgay - 8'd40 : 8'd0; // 0-39(40)|40-199(160)|200-239(40)
|
||||
|
||||
|
||||
// calcul vram address (TODO include xsize, ysize, xscroll[1:0] in calculation)
|
||||
//assign addr = lcd_yscroll * 8'h30 + lcd_xscroll[7:2] + lcdy * 8'h30 + lcdx[7:2];
|
||||
assign addr = lcdy * 8'h30 + lcdx[7:2];
|
||||
|
||||
assign ce_pxl = hcount[0] == 1;
|
||||
|
||||
// assign colors
|
||||
wire [2:0] index = { lcdx[1:0], 1'b0 };
|
||||
|
||||
always @(posedge clk)
|
||||
if (ce && lcdx != 0 && lcdy != 0) begin
|
||||
if (ce_pxl) begin
|
||||
case ({white,data[index+:2]})
|
||||
3'b000: { red, green, blue } <= 24'h87BA6B;
|
||||
3'b001: { red, green, blue } <= 24'h6BA378;
|
||||
3'b010: { red, green, blue } <= 24'h386B82;
|
||||
3'b011: { red, green, blue } <= 24'h384052;
|
||||
|
||||
3'b100: { red, green, blue } <= 24'hFFFFFF;//white
|
||||
3'b101: { red, green, blue } <= 24'hC0C0C0;//silver
|
||||
3'b110: { red, green, blue } <= 24'h808080;//gray
|
||||
3'b111: { red, green, blue } <= 24'h000000;//black
|
||||
endcase
|
||||
end
|
||||
end
|
||||
else
|
||||
{ red, green, blue } <= 24'h0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
hcount <= hcount + 10'd1;
|
||||
if (hcount == 10'd799) hcount <= 0;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
if (hcount == 10'd799)
|
||||
vcount <= vcount + 10'd1;
|
||||
else if (vcount == 10'd509)
|
||||
vcount <= 0;
|
||||
|
||||
endmodule
|
||||
BIN
common/Nibbler.exe
Normal file
BIN
common/Nibbler.exe
Normal file
Binary file not shown.
Reference in New Issue
Block a user