mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-02-21 06:45:13 +00:00
181 lines
4.0 KiB
VHDL
181 lines
4.0 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity keymap is
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port(
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A : in std_logic_vector(7 downto 0);
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clk_sys: in std_logic;
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ROW : out std_logic_vector(2 downto 0);
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COL : out std_logic_vector(2 downto 0);
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EN : out std_logic
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);
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end keymap;
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architecture arch of keymap is
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begin
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ROM256X1_ROW2 : entity work.sprom
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generic map
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(
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init_file => "roms/key1.hex",
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widthad_a => 8,
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width_a => 1
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)
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port map
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(
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clock => clk_sys,
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address => A,
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q(0) => ROW(2)
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);
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-- ROWS
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-- ROM256X1_ROW2 : ROM256X1
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-- generic map (
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-- INIT => X"00140800000000000000000000000000004000402E3400000000004E7C760000")
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-- port map (
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-- q => ROW(2), -- ROM output
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-- address => A
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-- );
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ROM256X1_ROW1 : entity work.sprom
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generic map
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(
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init_file => "roms/key2.hex",
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widthad_a => 8,
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width_a => 1
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)
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port map
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(
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clock => clk_sys,
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address => A,
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q(0) => ROW(1)
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);
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-- ROM256X1_ROW1 : ROM256X1
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-- generic map (
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-- INIT => X"00340000000000000000000000000000000000002834763000146C7E68200000")
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-- port map (
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-- q => ROW(1), -- ROM output
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-- address => A
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-- );
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ROM256X1_ROW0 : entity work.sprom
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generic map
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(
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init_file => "roms/key3.hex",
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widthad_a => 8,
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width_a => 1
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)
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port map
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(
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clock => clk_sys,
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address => A,
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q(0) => ROW(0)
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);
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-- ROM256X1_ROW0 : ROM256X1
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-- generic map (
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-- INIT => X"003008000000000000000000000000000040004004346C4A004A1C7A34400000")
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-- port map (
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-- q => ROW(0), -- ROM output
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-- address => A -- ROM address
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-- );
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-- COLUMNS
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ROM256X1_COL2 : entity work.sprom
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generic map
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(
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init_file => "roms/key4.hex",
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widthad_a => 8,
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width_a => 1
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)
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port map
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(
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clock => clk_sys,
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address => A,
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q(0) => COL(2)
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);
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-- ROM256X1_COL2 : ROM256X1
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-- generic map (
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-- INIT => X"00340800000000000000000000000000000000400E302E3A5038021038060000")
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-- port map (
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-- q => COL(2), -- ROM output
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-- address => A -- ROM address[7]
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-- );
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ROM256X1_COL1 : entity work.sprom
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generic map
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(
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init_file => "roms/key5.hex",
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widthad_a => 8,
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width_a => 1
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)
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port map
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(
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clock => clk_sys,
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address => A,
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q(0) => COL(1)
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);
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-- ROM256X1_COL1 : ROM256X1
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-- generic map (
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-- INIT => X"000000000000000000000000000000000000000026245C64447C00327C100000")
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-- port map (
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-- q => COL(1), -- ROM output
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-- address => A -- ROM address[7]
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-- );
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ROM256X1_COL0 : entity work.sprom
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generic map
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(
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init_file => "roms/key6.hex",
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widthad_a => 8,
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width_a => 1
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)
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port map
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(
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clock => clk_sys,
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address => A,
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q(0) => COL(0)
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);
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-- ROM256X1_COL0 : ROM256X1
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-- generic map (
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-- INIT => X"00000000000000000000000000000000004000402E347C7C5800380800220000")
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-- port map (
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-- q => COL(0), -- ROM output
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-- address => A -- ROM address[7]
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-- );
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-- ENABLE
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ROM256X1_EN : entity work.sprom
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generic map
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(
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init_file => "roms/key7.hex",
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widthad_a => 8,
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width_a => 1
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)
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port map
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(
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clock => clk_sys,
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address => A,
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q(0) => EN
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);
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-- ROM256X1_EN : ROM256X1
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-- generic map (
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-- INIT => X"00340800000000000000000000000000004000402E347E7E7C7E7E7E7C760000")
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-- port map (
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-- q => EN, -- ROM output
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-- address => A -- ROM address[7]
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-- );
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end arch;
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