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https://github.com/Gehstock/Mist_FPGA.git
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120 lines
2.3 KiB
VHDL
120 lines
2.3 KiB
VHDL
-- base sur les infos des pages suivantes :
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-- http://www.computer-engineering.org/ps2protocol/
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-- http://www.computer-engineering.org/ps2keyboard/
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity ps2key is
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generic (
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FREQ : integer := 24
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);
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port(
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CLK : in std_logic;
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RESET : in std_logic;
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PS2CLK : in std_logic;
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PS2DATA : in std_logic;
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BREAK : out std_logic;
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EXTENDED : out std_logic;
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CODE : out std_logic_vector(6 downto 0);
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LATCH : out std_logic
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);
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end ps2key;
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architecture rtl of ps2key is
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constant CLKCNT_SAMPLE : integer := FREQ * 20; -- 20us apres transition de l'horloge
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-- Sampling
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signal clkcnt : std_logic_vector(15 downto 0);
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signal shift : std_logic;
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signal idlcnt : std_logic_vector(15 downto 0);
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-- Shifting
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signal bitcnt : std_logic_vector(3 downto 0);
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signal cready : std_logic;
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signal char : std_logic_vector(10 downto 0);
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-- Decodage
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signal brkcode : std_logic;
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signal extcode : std_logic;
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-- Signal de controle
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signal kready : std_logic;
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begin
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process(RESET, CLK, PS2CLK, PS2DATA)
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begin
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if RESET = '1' then
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clkcnt <= (others => '0');
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shift <= '0';
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bitcnt <= x"0";
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cready <= '0';
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char <= (others => '0');
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brkcode <= '0';
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extcode <= '0';
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kready <= '0';
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elsif rising_edge(CLK) then
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-- Sampling des bits
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if PS2CLK = '1' then
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shift <= '0';
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clkcnt <= (others => '0');
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else
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clkcnt <= clkcnt + 1;
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if clkcnt = CLKCNT_SAMPLE then
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shift <= '1';
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else
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shift <= '0';
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end if;
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end if;
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-- Bit-shifting
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if shift = '1' then
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char <= PS2DATA & char(10 downto 1);
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if bitcnt = x"A" then
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bitcnt <= x"0";
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cready <= '1';
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else
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bitcnt <= bitcnt + 1;
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end if;
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end if;
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-- Decodage sequence
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if cready = '1' then
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cready <= '0';
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if char(8 downto 1) = x"E0" then
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extcode <= '1';
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kready <= '0';
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elsif char(8 downto 1) = x"F0" then
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brkcode <= '1';
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kready <= '0';
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elsif char(8) = '1' then -- les codes > 0x7F sont reserves apparemment
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kready <= '0';
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else
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kready <= '1';
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end if;
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else
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if kready = '1' then
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brkcode <= '0';
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extcode <= '0';
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kready <= '0';
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end if;
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end if;
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end if;
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end process;
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BREAK <= brkcode;
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EXTENDED <= extcode;
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CODE <= char(7 downto 1);
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LATCH <= kready;
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end rtl; |