mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-02-07 00:27:10 +00:00
140 lines
3.3 KiB
Verilog
140 lines
3.3 KiB
Verilog
// A video pipeline for MiST. Just insert between the core video output and the VGA pins
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// Provides an optional scandoubler, a rotateable OSD and (optional) RGb->YPbPr conversion
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module mist_video
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(
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// master clock
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// it should be 4xpixel clock for the scandoubler
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input clk_sys,
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// OSD SPI interface
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input SPI_SCK,
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input SPI_SS3,
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input SPI_DI,
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// scanlines (00-none 01-25% 10-50% 11-75%)
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input [1:0] scanlines,
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// 0 = HVSync 31KHz, 1 = CSync 15KHz
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input scandoubler_disable,
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// YPbPr always uses composite sync
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input ypbpr,
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// Rotate OSD [0] - rotate [1] - left or right
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input [1:0] rotate,
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// video in
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input [COLOR_DEPTH-1:0] R,
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input [COLOR_DEPTH-1:0] G,
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input [COLOR_DEPTH-1:0] B,
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input HSync,
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input VSync,
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// MiST video output signals
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output [5:0] VGA_R,
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output [5:0] VGA_G,
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output [5:0] VGA_B,
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output VGA_VS,
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output VGA_HS
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);
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parameter OSD_COLOR = 3'd4;
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parameter OSD_X_OFFSET = 10'd0;
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parameter OSD_Y_OFFSET = 10'd0;
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parameter SD_HCNT_WIDTH = 9;
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parameter COLOR_DEPTH = 6; // 1-6
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wire [5:0] SD_R_O;
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wire [5:0] SD_G_O;
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wire [5:0] SD_B_O;
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wire SD_HS_O;
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wire SD_VS_O;
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reg [5:0] R_full;
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reg [5:0] G_full;
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reg [5:0] B_full;
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always @(*) begin
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if (COLOR_DEPTH == 6) begin
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R_full = R;
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G_full = G;
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B_full = B;
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end else if (COLOR_DEPTH == 2) begin
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R_full = {3{R}};
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G_full = {3{G}};
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B_full = {3{B}};
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end else if (COLOR_DEPTH == 1) begin
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R_full = {6{R}};
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G_full = {6{G}};
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B_full = {6{B}};
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end else begin
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R_full = { R, R[COLOR_DEPTH-1 -:(6-COLOR_DEPTH)] };
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G_full = { G, G[COLOR_DEPTH-1 -:(6-COLOR_DEPTH)] };
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B_full = { B, B[COLOR_DEPTH-1 -:(6-COLOR_DEPTH)] };
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end
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end
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scandoubler #(SD_HCNT_WIDTH, COLOR_DEPTH) scandoubler
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(
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.clk_sys ( clk_sys ),
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.scanlines ( scanlines ),
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.hs_in ( HSync ),
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.vs_in ( VSync ),
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.r_in ( R ),
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.g_in ( G ),
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.b_in ( B ),
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.hs_out ( SD_HS_O ),
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.vs_out ( SD_VS_O ),
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.r_out ( SD_R_O ),
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.g_out ( SD_G_O ),
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.b_out ( SD_B_O )
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);
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wire [5:0] osd_r_o;
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wire [5:0] osd_g_o;
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wire [5:0] osd_b_o;
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osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
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(
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.clk_sys ( clk_sys ),
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.rotate ( rotate ),
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.SPI_DI ( SPI_DI ),
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.SPI_SCK ( SPI_SCK ),
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.SPI_SS3 ( SPI_SS3 ),
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.R_in ( scandoubler_disable ? R_full : SD_R_O ),
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.G_in ( scandoubler_disable ? G_full : SD_G_O ),
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.B_in ( scandoubler_disable ? B_full : SD_B_O ),
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.HSync ( scandoubler_disable ? HSync : SD_HS_O ),
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.VSync ( scandoubler_disable ? VSync : SD_VS_O ),
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.R_out ( osd_r_o ),
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.G_out ( osd_g_o ),
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.B_out ( osd_b_o )
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);
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wire [5:0] y, pb, pr;
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rgb2ypbpr rgb2ypbpr
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(
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.red ( osd_r_o ),
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.green ( osd_g_o ),
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.blue ( osd_b_o ),
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.y ( y ),
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.pb ( pb ),
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.pr ( pr )
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);
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assign VGA_R = ypbpr?pr:osd_r_o;
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assign VGA_G = ypbpr? y:osd_g_o;
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assign VGA_B = ypbpr?pb:osd_b_o;
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wire cs = scandoubler_disable ? ~(HSync ^ VSync) : ~(SD_HS_O ^ SD_VS_O);
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wire hs = scandoubler_disable ? HSync : SD_HS_O;
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wire vs = scandoubler_disable ? VSync : SD_VS_O;
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// a minimig vga->scart cable expects a composite sync signal on the VGA_HS output.
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// and VCC on VGA_VS (to switch into rgb mode)
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assign VGA_HS = (scandoubler_disable || ypbpr)? cs : hs;
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assign VGA_VS = (scandoubler_disable || ypbpr)? 1'b1 : vs;
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endmodule
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