mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-02-26 08:33:31 +00:00
237 lines
6.5 KiB
VHDL
237 lines
6.5 KiB
VHDL
--------------------------------------------------------------
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-- Single port Block RAM
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--------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.altera_mf_components.all;
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ENTITY spram IS
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generic (
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addr_width : integer := 8;
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data_width : integer := 8;
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mem_init_file : string := " ";
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mem_name : string := "MEM" -- for InSystem Memory content editor.
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);
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PORT
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(
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clock : in STD_LOGIC;
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address : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0);
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data : in STD_LOGIC_VECTOR (data_width-1 DOWNTO 0) := (others => '0');
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enable : in STD_LOGIC := '1';
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wren : in STD_LOGIC := '0';
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q : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0);
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cs : in std_logic := '1'
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);
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END spram;
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ARCHITECTURE SYN OF spram IS
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BEGIN
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spram_sz : work.spram_sz
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generic map(addr_width, data_width, 2**addr_width, mem_init_file, mem_name)
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port map(clock,address,data,enable,wren,q,cs);
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END SYN;
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--------------------------------------------------------------
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-- Single port Block RAM with specific size
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--------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.altera_mf_components.all;
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ENTITY spram_sz IS
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generic (
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addr_width : integer := 8;
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data_width : integer := 8;
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numwords : integer := 2**8;
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mem_init_file : string := " ";
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mem_name : string := "MEM" -- for InSystem Memory content editor.
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);
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PORT
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(
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clock : in STD_LOGIC;
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address : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0);
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data : in STD_LOGIC_VECTOR (data_width-1 DOWNTO 0) := (others => '0');
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enable : in STD_LOGIC := '1';
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wren : in STD_LOGIC := '0';
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q : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0);
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cs : in std_logic := '1'
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);
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END ENTITY;
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ARCHITECTURE SYN OF spram_sz IS
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signal q0 : std_logic_vector((data_width - 1) downto 0);
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BEGIN
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q<= q0 when cs = '1' else (others => '1');
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altsyncram_component : altsyncram
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GENERIC MAP (
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clock_enable_input_a => "BYPASS",
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clock_enable_output_a => "BYPASS",
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intended_device_family => "Cyclone V",
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lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME="&mem_name,
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lpm_type => "altsyncram",
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numwords_a => numwords,
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operation_mode => "SINGLE_PORT",
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outdata_aclr_a => "NONE",
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outdata_reg_a => "UNREGISTERED",
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power_up_uninitialized => "FALSE",
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read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
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init_file => mem_init_file,
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widthad_a => addr_width,
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width_a => data_width,
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width_byteena_a => 1
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)
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PORT MAP (
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address_a => address,
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clock0 => clock,
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data_a => data,
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wren_a => wren and cs,
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q_a => q0
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);
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END SYN;
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--------------------------------------------------------------
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-- Dual port Block RAM same parameters on both ports
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--------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.altera_mf_components.all;
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entity dpram is
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generic (
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addr_width : integer := 8;
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data_width : integer := 8;
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mem_init_file : string := " "
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);
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PORT
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(
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clock : in STD_LOGIC;
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address_a : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0);
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data_a : in STD_LOGIC_VECTOR (data_width-1 DOWNTO 0) := (others => '0');
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enable_a : in STD_LOGIC := '1';
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wren_a : in STD_LOGIC := '0';
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q_a : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0);
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cs_a : in std_logic := '1';
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address_b : in STD_LOGIC_VECTOR (addr_width-1 DOWNTO 0) := (others => '0');
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data_b : in STD_LOGIC_VECTOR (data_width-1 DOWNTO 0) := (others => '0');
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enable_b : in STD_LOGIC := '1';
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wren_b : in STD_LOGIC := '0';
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q_b : out STD_LOGIC_VECTOR (data_width-1 DOWNTO 0);
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cs_b : in std_logic := '1'
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);
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end entity;
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ARCHITECTURE SYN OF dpram IS
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BEGIN
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ram : work.dpram_dif generic map(addr_width,data_width,addr_width,data_width,mem_init_file)
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port map(clock,address_a,data_a,enable_a,wren_a,q_a,cs_a,address_b,data_b,enable_b,wren_b,q_b,cs_b);
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END SYN;
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--------------------------------------------------------------
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-- Dual port Block RAM different parameters on ports
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--------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera_mf;
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USE altera_mf.altera_mf_components.all;
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entity dpram_dif is
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generic (
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addr_width_a : integer := 8;
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data_width_a : integer := 8;
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addr_width_b : integer := 8;
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data_width_b : integer := 8;
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mem_init_file : string := " "
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);
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PORT
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(
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clock : in STD_LOGIC;
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address_a : in STD_LOGIC_VECTOR (addr_width_a-1 DOWNTO 0);
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data_a : in STD_LOGIC_VECTOR (data_width_a-1 DOWNTO 0) := (others => '0');
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enable_a : in STD_LOGIC := '1';
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wren_a : in STD_LOGIC := '0';
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q_a : out STD_LOGIC_VECTOR (data_width_a-1 DOWNTO 0);
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cs_a : in std_logic := '1';
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address_b : in STD_LOGIC_VECTOR (addr_width_b-1 DOWNTO 0) := (others => '0');
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data_b : in STD_LOGIC_VECTOR (data_width_b-1 DOWNTO 0) := (others => '0');
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enable_b : in STD_LOGIC := '1';
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wren_b : in STD_LOGIC := '0';
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q_b : out STD_LOGIC_VECTOR (data_width_b-1 DOWNTO 0);
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cs_b : in std_logic := '1'
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);
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end entity;
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ARCHITECTURE SYN OF dpram_dif IS
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signal q0 : std_logic_vector((data_width_a - 1) downto 0);
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signal q1 : std_logic_vector((data_width_b - 1) downto 0);
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BEGIN
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q_a<= q0 when cs_a = '1' else (others => '1');
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q_b<= q1 when cs_b = '1' else (others => '1');
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altsyncram_component : altsyncram
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GENERIC MAP (
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address_reg_b => "CLOCK1",
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clock_enable_input_a => "NORMAL",
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clock_enable_input_b => "NORMAL",
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clock_enable_output_a => "BYPASS",
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clock_enable_output_b => "BYPASS",
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indata_reg_b => "CLOCK1",
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intended_device_family => "Cyclone V",
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lpm_type => "altsyncram",
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numwords_a => 2**addr_width_a,
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numwords_b => 2**addr_width_b,
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operation_mode => "BIDIR_DUAL_PORT",
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outdata_aclr_a => "NONE",
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outdata_aclr_b => "NONE",
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outdata_reg_a => "UNREGISTERED",
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outdata_reg_b => "UNREGISTERED",
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power_up_uninitialized => "FALSE",
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read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
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read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
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init_file => mem_init_file,
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widthad_a => addr_width_a,
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widthad_b => addr_width_b,
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width_a => data_width_a,
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width_b => data_width_b,
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width_byteena_a => 1,
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width_byteena_b => 1,
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wrcontrol_wraddress_reg_b => "CLOCK1"
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)
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PORT MAP (
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address_a => address_a,
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address_b => address_b,
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clock0 => clock,
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clock1 => clock,
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clocken0 => enable_a,
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clocken1 => enable_b,
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data_a => data_a,
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data_b => data_b,
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wren_a => wren_a and cs_a,
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wren_b => wren_b and cs_b,
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q_a => q0,
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q_b => q1
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);
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END SYN;
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