mirror of
https://github.com/Gehstock/Mist_FPGA.git
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288 lines
8.1 KiB
Systemverilog
288 lines
8.1 KiB
Systemverilog
//
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// sdram.v
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// This version issues refresh only when 8bit channel reads the same 16bit word 2 times
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//
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// sdram controller implementation
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// Copyright (c) 2018 Sorgelig
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module sdram
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(
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// interface to the MT48LC16M16 chip
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inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
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output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
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output reg SDRAM_DQML, // byte mask
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output reg SDRAM_DQMH, // byte mask
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output reg [1:0] SDRAM_BA, // two banks
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output reg SDRAM_nCS, // a single chip select
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output reg SDRAM_nWE, // write enable
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output reg SDRAM_nRAS, // row address select
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output reg SDRAM_nCAS, // columns address select
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output SDRAM_CLK,
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output SDRAM_CKE,
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// cpu/chipset interface
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input init, // init signal after FPGA config to initialize RAM
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input clk, // sdram is accessed at up to 128MHz
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input [24:0] ch0_addr,
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input ch0_rd,
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input ch0_wr,
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input [7:0] ch0_din,
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output reg [7:0] ch0_dout,
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output reg ch0_busy,
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input [24:0] ch1_addr,
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input ch1_rd,
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input ch1_wr,
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input [7:0] ch1_din,
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output reg [7:0] ch1_dout,
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output reg ch1_busy,
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input [24:0] ch2_addr,
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input ch2_rd,
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input ch2_wr,
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input [7:0] ch2_din,
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output reg [7:0] ch2_dout,
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output reg ch2_busy
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);
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assign SDRAM_nCS = 0;
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assign SDRAM_CKE = 1;
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assign {SDRAM_DQMH,SDRAM_DQML} = SDRAM_A[12:11];
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localparam RASCAS_DELAY = 3'd1; // tRCD=20ns -> 2 cycles@85MHz
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localparam BURST_LENGTH = 3'd0; // 0=1, 1=2, 2=4, 3=8, 7=full page
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localparam ACCESS_TYPE = 1'd0; // 0=sequential, 1=interleaved
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localparam CAS_LATENCY = 3'd2; // 2/3 allowed
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localparam OP_MODE = 2'd0; // only 0 (standard operation) allowed
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localparam NO_WRITE_BURST = 1'd1; // 0=write burst enabled, 1=only single access write
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localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
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localparam STATE_IDLE = 3'd0; // state to check the requests
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localparam STATE_START = STATE_IDLE+1'd1; // state in which a new command is started
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localparam STATE_NEXT = STATE_START+1'd1; // state in which a new command is started
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localparam STATE_CONT = STATE_START+RASCAS_DELAY;
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localparam STATE_READY = STATE_CONT+CAS_LATENCY+2'd2;
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localparam STATE_LAST = STATE_READY; // last state in cycle
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reg [2:0] state;
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reg [22:0] a;
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reg [1:0] bank;
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reg [15:0] data;
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reg we;
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reg ram_req=0;
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wire [2:0] rd,wr;
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assign rd = {ch2_rd, ch1_rd, ch0_rd};
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assign wr = {ch2_wr, ch1_wr, ch0_wr};
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// access manager
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always @(posedge clk) begin
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reg old_ref;
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reg [2:0] old_rd,old_wr;//,rd,wr;
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reg [24:1] last_a[3] = '{'1,'1,'1};
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old_rd <= old_rd & rd;
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old_wr <= old_wr & wr;
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if(state == STATE_IDLE && mode == MODE_NORMAL) begin
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ram_req <= 0;
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we <= 0;
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ch0_busy <= 0;
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ch1_busy <= 0;
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ch2_busy <= 0;
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if((~old_rd[0] & rd[0]) | (~old_wr[0] & wr[0])) begin
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old_rd[0] <= rd[0];
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old_wr[0] <= wr[0];
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we <= wr[0];
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{bank,a} <= ch0_addr;
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data <= {ch0_din,ch0_din};
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ram_req <= wr[0] || (last_a[0] != ch0_addr[24:1]);
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last_a[0] <= wr[0] ? '1 : ch0_addr[24:1];
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ch0_busy <= 1;
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state <= STATE_START;
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end
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else if((~old_rd[1] & rd[1]) | (~old_wr[1] & wr[1])) begin
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old_rd[1] <= rd[1];
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old_wr[1] <= wr[1];
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we <= wr[1];
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{bank,a} <= ch1_addr;
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data <= {ch1_din,ch1_din};
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ram_req <= wr[1] || (last_a[1] != ch1_addr[24:1]);
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last_a[1] <= wr[1] ? '1 : ch1_addr[24:1];
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ch1_busy <= 1;
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state <= STATE_START;
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end
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else if((~old_rd[2] & rd[2]) | (~old_wr[2] & wr[2])) begin
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old_rd[2] <= rd[2];
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old_wr[2] <= wr[2];
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we <= wr[2];
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{bank,a} <= ch2_addr;
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data <= {ch2_din,ch2_din};
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ram_req <= wr[2] || (last_a[2] != ch2_addr[24:1]);
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last_a[2] <= wr[2] ? '1 : ch2_addr[24:1];
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ch2_busy <= 1;
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state <= STATE_START;
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end
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end
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if (state == STATE_READY) begin
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ch0_busy <= 0;
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ch1_busy <= 0;
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ch2_busy <= 0;
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end
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if(mode != MODE_NORMAL || state != STATE_IDLE || reset) begin
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state <= state + 1'd1;
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if(state == STATE_LAST) state <= STATE_IDLE;
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end
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end
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localparam MODE_NORMAL = 2'b00;
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localparam MODE_RESET = 2'b01;
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localparam MODE_LDM = 2'b10;
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localparam MODE_PRE = 2'b11;
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// initialization
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reg [1:0] mode;
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reg [4:0] reset=5'h1f;
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always @(posedge clk) begin
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reg init_old=0;
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init_old <= init;
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if(init_old & ~init) reset <= 5'h1f;
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else if(state == STATE_LAST) begin
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if(reset != 0) begin
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reset <= reset - 5'd1;
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if(reset == 14) mode <= MODE_PRE;
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else if(reset == 3) mode <= MODE_LDM;
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else mode <= MODE_RESET;
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end
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else mode <= MODE_NORMAL;
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end
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end
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localparam CMD_NOP = 3'b111;
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localparam CMD_ACTIVE = 3'b011;
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localparam CMD_READ = 3'b101;
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localparam CMD_WRITE = 3'b100;
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localparam CMD_BURST_TERMINATE = 3'b110;
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localparam CMD_PRECHARGE = 3'b010;
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localparam CMD_AUTO_REFRESH = 3'b001;
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localparam CMD_LOAD_MODE = 3'b000;
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wire [1:0] dqm = {we & ~a[0], we & a[0]};
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// SDRAM state machines
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always @(posedge clk) begin
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reg [15:0] last_data[3];
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reg [15:0] data_reg;
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if(state == STATE_START) SDRAM_BA <= (mode == MODE_NORMAL) ? bank : 2'b00;
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SDRAM_DQ <= 'Z;
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casex({ram_req,we,mode,state})
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{2'b1X, MODE_NORMAL, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_ACTIVE;
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{2'b11, MODE_NORMAL, STATE_CONT }: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE, SDRAM_DQ} <= {CMD_WRITE, data};
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{2'b10, MODE_NORMAL, STATE_CONT }: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_READ;
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{2'b0X, MODE_NORMAL, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_AUTO_REFRESH;
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// init
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{2'bXX, MODE_LDM, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_LOAD_MODE;
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{2'bXX, MODE_PRE, STATE_START}: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_PRECHARGE;
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default: {SDRAM_nRAS, SDRAM_nCAS, SDRAM_nWE} <= CMD_NOP;
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endcase
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casex({ram_req,mode,state})
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{1'b1, MODE_NORMAL, STATE_START}: SDRAM_A <= a[13:1];
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{1'b1, MODE_NORMAL, STATE_CONT }: SDRAM_A <= {dqm, 2'b10, a[22:14]};
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// init
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{1'bX, MODE_LDM, STATE_START}: SDRAM_A <= MODE;
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{1'bX, MODE_PRE, STATE_START}: SDRAM_A <= 13'b0010000000000;
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default: SDRAM_A <= 13'b0000000000000;
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endcase
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data_reg <= SDRAM_DQ;
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if(state == STATE_READY) begin
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if(ch0_busy) begin
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if(ram_req) begin
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if(we) ch0_dout <= data[7:0];
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else begin
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ch0_dout <= a[0] ? data_reg[15:8] : data_reg[7:0];
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last_data[0] <= data_reg;
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end
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end
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else ch0_dout <= a[0] ? last_data[0][15:8] : last_data[0][7:0];
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end
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if(ch1_busy) begin
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if(ram_req) begin
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if(we) ch1_dout <= data[7:0];
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else begin
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ch1_dout <= a[0] ? data_reg[15:8] : data_reg[7:0];
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last_data[1] <= data_reg;
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end
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end
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else ch1_dout <= a[0] ? last_data[1][15:8] : last_data[1][7:0];
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end
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if(ch2_busy) begin
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if(ram_req) begin
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if(we) ch2_dout <= data[7:0];
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else begin
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ch2_dout <= a[0] ? data_reg[15:8] : data_reg[7:0];
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last_data[2] <= data_reg;
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end
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end
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else ch2_dout <= a[0] ? last_data[2][15:8] : last_data[2][7:0];
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end
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end
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end
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altddio_out
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#(
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.extend_oe_disable("OFF"),
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.intended_device_family("Cyclone V"),
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.invert_output("OFF"),
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.lpm_hint("UNUSED"),
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.lpm_type("altddio_out"),
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.oe_reg("UNREGISTERED"),
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.power_up_high("OFF"),
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.width(1)
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)
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sdramclk_ddr
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(
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.datain_h(1'b0),
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.datain_l(1'b1),
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.outclock(clk),
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.dataout(SDRAM_CLK),
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.aclr(1'b0),
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.aset(1'b0),
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.oe(1'b1),
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.outclocken(1'b1),
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.sclr(1'b0),
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.sset(1'b0)
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);
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endmodule
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