mirror of
https://github.com/Gehstock/Mist_FPGA.git
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103 lines
3.3 KiB
VHDL
103 lines
3.3 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity keymatrix is
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port(
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CLK : in std_logic;
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wROW : in std_logic_vector(2 downto 0);
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wCOL : in std_logic_vector(2 downto 0);
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wVAL : in std_logic;
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wEN : in std_logic;
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WE : in std_logic;
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rCOL : in std_logic_vector(2 downto 0);
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rROWbit : out std_logic_vector(7 downto 0)
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);
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end keymatrix;
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architecture arch of keymatrix is
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signal WEi : std_logic_vector(7 downto 0);
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-- inutilise
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signal SPOi : std_logic_vector(7 downto 0);
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begin
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WEi(0) <= WE when wEN = '1' and wROW = "000" else '0';
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WEi(1) <= WE when wEN = '1' and wROW = "001" else '0';
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WEi(2) <= WE when wEN = '1' and wROW = "010" else '0';
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WEi(3) <= WE when wEN = '1' and wROW = "011" else '0';
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WEi(4) <= WE when wEN = '1' and wROW = "100" else '0';
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WEi(5) <= WE when wEN = '1' and wROW = "101" else '0';
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WEi(6) <= WE when wEN = '1' and wROW = "110" else '0';
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WEi(7) <= WE when wEN = '1' and wROW = "111" else '0';
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--ROWBit : for i in 0 to 7 generate
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-- RAM16X1D_ROWBit : RAM16X1D
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-- generic map (
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-- INIT => X"FFFF")
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-- port map (
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-- D => wVAL, -- Write 1-bit data input---------------------------data
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-- SPO => SPOi(i), -- R/W 1-bit data output for A0-A3
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-- A0 => wCOL(0), -- R/W address[0] input bit--------------------------waddress
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-- A1 => wCOL(1), -- R/W address[1] input bit
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-- A2 => wCOL(2), -- R/W address[2] input bit
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-- A3 => '0', -- R/W ddress[3] input bit
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-- DPO => rROWBit(i), -- Read-only 1-bit data output for DPRA--------------q
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-- DPRA0 => rCOL(0), -- Read-only address[0] input bit--------------------------raddress
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-- DPRA1 => rCOL(1), -- Read-only address[1] input bit
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-- DPRA2 => rCOL(2), -- Read-only address[2] input bit
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-- DPRA3 => '0', -- Read-only address[3] input bit
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-- WCLK => CLK, -- Write clock input-----------------------------------clock
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-- WE => WEi(i) -- Write enable input----------------------------------wren
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-- );
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--end generate;
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ROWBit : for i in 0 to 7 generate
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RAM16X1D_ROWBit : entity work.RAM8X1D
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-- generic map (
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-- INIT => X"FFFF")
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port map (
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data(0) => wVAL, -- Write 1-bit data input---------------------------data
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enable => SPOi(i), -- R/W 1-bit data output for A0-A3
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wraddress => wCOL,
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-- A0 => wCOL(0), -- R/W address[0] input bit--------------------------waddress
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-- A1 => wCOL(1), -- R/W address[1] input bit
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-- A2 => wCOL(2), -- R/W address[2] input bit
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-- A3 => '0', -- R/W ddress[3] input bit
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-- rden => rROWBit(i), -- Read-only 1-bit data output for DPRA--------------q
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rdaddress => rCOL,
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-- DPRA0 => rCOL(0), -- Read-only address[0] input bit--------------------------raddress
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-- DPRA1 => rCOL(1), -- Read-only address[1] input bit
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-- DPRA2 => rCOL(2), -- Read-only address[2] input bit
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-- DPRA3 => '0', -- Read-only address[3] input bit
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clock => CLK,
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-- WCLK => CLK, -- Write clock input-----------------------------------clock
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wren => WEi(i) -- Write enable input----------------------------------wren
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);
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end generate;
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end arch;
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