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https://github.com/Gehstock/Mist_FPGA.git
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111 lines
3.8 KiB
Verilog
111 lines
3.8 KiB
Verilog
/*******************************************************************************
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* This file is owned and controlled by Xilinx and must be used *
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* solely for design, simulation, implementation and creation of *
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* design files limited to Xilinx devices or technologies. Use *
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* with non-Xilinx devices or technologies is expressly prohibited *
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* and immediately terminates your license. *
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* *
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
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* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
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* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
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* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
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* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
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* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
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* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
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* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
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* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
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* FOR A PARTICULAR PURPOSE. *
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* *
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* Xilinx products are not intended for use in life support *
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* appliances, devices, or systems. Use in such applications are *
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* expressly prohibited. *
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* *
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* (c) Copyright 1995-2007 Xilinx, Inc. *
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* All rights reserved. *
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*******************************************************************************/
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// The synthesis directives "translate_off/translate_on" specified below are
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// supported by Xilinx, Mentor Graphics and Synplicity synthesis
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// tools. Ensure they are correct for your synthesis tool(s).
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// You must compile the wrapper file monrom.v when simulating
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// the core, monrom. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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`timescale 1ns/1ps
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module monrom(
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addr,
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clk,
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din,
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dout,
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en,
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we);
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input [15 : 0] addr;
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input clk;
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input [7 : 0] din;
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output [7 : 0] dout;
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input en;
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input we;
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// synthesis translate_off
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BLKMEMSP_V6_2 #(
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.c_addr_width(16),
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.c_default_data("0"),
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.c_depth(36864),
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.c_enable_rlocs(0),
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.c_has_default_data(0),
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.c_has_din(1),
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.c_has_en(1),
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.c_has_limit_data_pitch(0),
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.c_has_nd(0),
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.c_has_rdy(0),
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.c_has_rfd(0),
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.c_has_sinit(0),
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.c_has_we(1),
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.c_limit_data_pitch(18),
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.c_mem_init_file("monrom.mif"),
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.c_pipe_stages(0),
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.c_reg_inputs(0),
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.c_sinit_value("0"),
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.c_width(8),
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.c_write_mode(0),
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.c_ybottom_addr("0"),
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.c_yclk_is_rising(1),
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.c_yen_is_high(1),
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.c_yhierarchy("hierarchy1"),
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.c_ymake_bmm(0),
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.c_yprimitive_type("16kx1"),
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.c_ysinit_is_high(1),
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.c_ytop_addr("1024"),
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.c_yuse_single_primitive(0),
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.c_ywe_is_high(1),
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.c_yydisable_warnings(1))
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inst (
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.ADDR(addr),
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.CLK(clk),
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.DIN(din),
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.DOUT(dout),
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.EN(en),
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.WE(we),
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.ND(),
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.RFD(),
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.RDY(),
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.SINIT());
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// synthesis translate_on
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// XST black box declaration
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// box_type "black_box"
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// synthesis attribute box_type of monrom is "black_box"
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endmodule
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