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New Try with MZ80K

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Gehstock
2018-06-24 13:33:25 +02:00
parent 4cca7bb163
commit bb2ee068da
80 changed files with 26744 additions and 855 deletions
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128
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Assembler report for mz80k_mist
Sun Jun 24 13:31:13 2018
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/Output/mz80k_mist.sof
6. Assembler Device Options: D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/Output/mz80k_mist.rbf
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sun Jun 24 13:31:13 2018 ;
; Revision Name ; mz80k_mist ;
; Top-level Entity Name ; mz80k_mist ;
; Family ; Cyclone III ;
; Device ; EP3C25E144C8 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Generate Raw Binary File (.rbf) For Target Device ; On ; Off ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Generate compressed bitstreams ; On ; On ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Auto user code ; On ; On ;
; Use configuration device ; Off ; Off ;
; Configuration device ; Auto ; Auto ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Enable OCT_DONE ; Off ; Off ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+----------+---------------+
+---------------------------------------------------------------+
; Assembler Generated Files ;
+---------------------------------------------------------------+
; File Name ;
+---------------------------------------------------------------+
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/Output/mz80k_mist.sof ;
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/Output/mz80k_mist.rbf ;
+---------------------------------------------------------------+
+-----------------------------------------------------------------------------------------+
; Assembler Device Options: D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/Output/mz80k_mist.sof ;
+----------------+------------------------------------------------------------------------+
; Option ; Setting ;
+----------------+------------------------------------------------------------------------+
; Device ; EP3C25E144C8 ;
; JTAG usercode ; 0x003EEC1B ;
; Checksum ; 0x003EEC1B ;
+----------------+------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------+
; Assembler Device Options: D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/Output/mz80k_mist.rbf ;
+---------------------+-------------------------------------------------------------------+
; Option ; Setting ;
+---------------------+-------------------------------------------------------------------+
; Raw Binary File ; ;
; Compression Ratio ; 2 ;
+---------------------+-------------------------------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Sun Jun 24 13:31:10 2018
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off mz80k_mist -c mz80k_mist
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4635 megabytes
Info: Processing ended: Sun Jun 24 13:31:13 2018
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:03

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/* Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EP3C25E144) Path("D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/Output/") File("mz80k_mist.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

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Sun Jun 24 13:31:33 2018

107
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EDA Netlist Writer report for mz80k_mist
Sun Jun 24 13:31:32 2018
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. EDA Netlist Writer Summary
3. Simulation Settings
4. Simulation Generated Files
5. EDA Netlist Writer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Sun Jun 24 13:31:32 2018 ;
; Revision Name ; mz80k_mist ;
; Top-level Entity Name ; mz80k_mist ;
; Family ; Cyclone III ;
; Simulation Files Creation ; Successful ;
+---------------------------+---------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------+
; Simulation Settings ;
+---------------------------------------------------------------------------------------------------+------------------------+
; Option ; Setting ;
+---------------------------------------------------------------------------------------------------+------------------------+
; Tool Name ; ModelSim-Altera (VHDL) ;
; Generate netlist for functional simulation only ; Off ;
; Time scale ; 1 ps ;
; Truncate long hierarchy paths ; Off ;
; Map illegal HDL characters ; Off ;
; Flatten buses into individual nodes ; Off ;
; Maintain hierarchy ; Off ;
; Bring out device-wide set/reset signals as ports ; Off ;
; Enable glitch filtering ; Off ;
; Do not write top level VHDL entity ; Off ;
; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
; Architecture name in VHDL output netlist ; structure ;
; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
; Generate third-party EDA tool command script for gate-level simulation ; Off ;
+---------------------------------------------------------------------------------------------------+------------------------+
+---------------------------------------------------------------------------------------------------+
; Simulation Generated Files ;
+---------------------------------------------------------------------------------------------------+
; Generated Files ;
+---------------------------------------------------------------------------------------------------+
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/mz80k_mist_8_1200mv_85c_slow.vho ;
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/mz80k_mist_8_1200mv_0c_slow.vho ;
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/mz80k_mist_min_1200mv_0c_fast.vho ;
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/mz80k_mist.vho ;
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/mz80k_mist_8_1200mv_85c_vhd_slow.sdo ;
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/mz80k_mist_8_1200mv_0c_vhd_slow.sdo ;
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/mz80k_mist_min_1200mv_0c_vhd_fast.sdo ;
; D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/mz80k_mist_vhd.sdo ;
+---------------------------------------------------------------------------------------------------+
+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit EDA Netlist Writer
Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
Info: Processing started: Sun Jun 24 13:31:27 2018
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off mz80k_mist -c mz80k_mist
Info (204019): Generated file mz80k_mist_8_1200mv_85c_slow.vho in folder "D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file mz80k_mist_8_1200mv_0c_slow.vho in folder "D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file mz80k_mist_min_1200mv_0c_fast.vho in folder "D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file mz80k_mist.vho in folder "D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file mz80k_mist_8_1200mv_85c_vhd_slow.sdo in folder "D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file mz80k_mist_8_1200mv_0c_vhd_slow.sdo in folder "D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file mz80k_mist_min_1200mv_0c_vhd_fast.sdo in folder "D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/" for EDA simulation tool
Info (204019): Generated file mz80k_mist_vhd.sdo in folder "D:/Github/Mist_FPGA/Sharp - MZ-80K_MiST/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 4636 megabytes
Info: Processing ended: Sun Jun 24 13:31:32 2018
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:04

7777
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Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
Extra Info (176236): Started Fast Input/Output/OE register processing
Extra Info (176237): Finished Fast Input/Output/OE register processing
Extra Info (176238): Start inferring scan chains for DSP blocks
Extra Info (176239): Inferring scan chains for DSP blocks is complete
Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks

16
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Fitter Status : Successful - Sun Jun 24 13:31:05 2018
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : mz80k_mist
Top-level Entity Name : mz80k_mist
Family : Cyclone III
Device : EP3C25E144C8
Timing Models : Final
Total logic elements : 3,012 / 24,624 ( 12 % )
Total combinational functions : 2,886 / 24,624 ( 12 % )
Dedicated logic registers : 891 / 24,624 ( 4 % )
Total registers : 891
Total pins : 31 / 83 ( 37 % )
Total virtual pins : 0
Total memory bits : 311,296 / 608,256 ( 51 % )
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
Total PLLs : 1 / 4 ( 25 % )

136
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Flow report for mz80k_mist
Sun Jun 24 13:31:32 2018
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+--------------------------------------------+
; Flow Status ; Successful - Sun Jun 24 13:31:32 2018 ;
; Quartus II 64-Bit Version ; 13.1.0 Build 162 10/23/2013 SJ Web Edition ;
; Revision Name ; mz80k_mist ;
; Top-level Entity Name ; mz80k_mist ;
; Family ; Cyclone III ;
; Device ; EP3C25E144C8 ;
; Timing Models ; Final ;
; Total logic elements ; 3,012 / 24,624 ( 12 % ) ;
; Total combinational functions ; 2,886 / 24,624 ( 12 % ) ;
; Dedicated logic registers ; 891 / 24,624 ( 4 % ) ;
; Total registers ; 891 ;
; Total pins ; 31 / 83 ( 37 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 311,296 / 608,256 ( 51 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 132 ( 0 % ) ;
; Total PLLs ; 1 / 4 ( 25 % ) ;
+------------------------------------+--------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 06/24/2018 13:29:56 ;
; Main task ; Compilation ;
; Revision Name ; mz80k_mist ;
+-------------------+---------------------+
+----------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+---------------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+---------------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 84440844040061.152983979606548 ; -- ; -- ; -- ;
; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; <None> ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; OUTPUT_IO_TIMING_FAR_END_VMEAS ; Half Signal Swing ; -- ; -- ; -- ;
; OUTPUT_IO_TIMING_FAR_END_VMEAS ; Half Signal Swing ; -- ; -- ; -- ;
; OUTPUT_IO_TIMING_NEAR_END_VMEAS ; Half Vccio ; -- ; -- ; -- ;
; OUTPUT_IO_TIMING_NEAR_END_VMEAS ; Half Vccio ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
; PRE_FLOW_SCRIPT_FILE ; quartus_sh:rtl/build_id.tcl ; -- ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; Output ; -- ; -- ; -- ;
; VERILOG_INPUT_VERSION ; SystemVerilog_2005 ; Verilog_2001 ; -- ; -- ;
; VERILOG_SHOW_LMF_MAPPING_MESSAGES ; Off ; -- ; -- ; -- ;
+-------------------------------------+---------------------------------------+---------------+-------------+----------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:17 ; 1.0 ; 4725 MB ; 00:00:17 ;
; Fitter ; 00:00:51 ; 2.0 ; 5526 MB ; 00:01:06 ;
; Assembler ; 00:00:03 ; 1.0 ; 4627 MB ; 00:00:03 ;
; TimeQuest Timing Analyzer ; 00:00:10 ; 1.3 ; 4795 MB ; 00:00:12 ;
; EDA Netlist Writer ; 00:00:05 ; 1.0 ; 4636 MB ; 00:00:04 ;
; Total ; 00:01:26 ; -- ; -- ; 00:01:42 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; DESKTOP-BA4AA0D ; Windows 7 ; 6.2 ; x86_64 ;
; Fitter ; DESKTOP-BA4AA0D ; Windows 7 ; 6.2 ; x86_64 ;
; Assembler ; DESKTOP-BA4AA0D ; Windows 7 ; 6.2 ; x86_64 ;
; TimeQuest Timing Analyzer ; DESKTOP-BA4AA0D ; Windows 7 ; 6.2 ; x86_64 ;
; EDA Netlist Writer ; DESKTOP-BA4AA0D ; Windows 7 ; 6.2 ; x86_64 ;
+---------------------------+------------------+-----------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off mz80k_mist -c mz80k_mist
quartus_fit --read_settings_files=off --write_settings_files=off mz80k_mist -c mz80k_mist
quartus_asm --read_settings_files=off --write_settings_files=off mz80k_mist -c mz80k_mist
quartus_sta mz80k_mist -c mz80k_mist
quartus_eda --read_settings_files=off --write_settings_files=off mz80k_mist -c mz80k_mist

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<sld_project_info>
<project>
<hash md5_digest_80b="29cd8da6179e01d6df0f"/>
</project>
<file_info>
<file device="EP3C25E144C8" path="mz80k_mist.sof" usercode="0xFFFFFFFF"/>
</file_info>
</sld_project_info>

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Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_if2" differs only in case from object "S_IF2" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_imm1" differs only in case from object "S_IMM1" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_imm2" differs only in case from object "S_IMM2" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_mr1" differs only in case from object "S_MR1" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_mr2" differs only in case from object "S_MR2" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_disp" differs only in case from object "S_DISP" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_in" differs only in case from object "S_IN" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_iack" differs only in case from object "S_IACK" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_mw1" differs only in case from object "S_MW1" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_mw2" differs only in case from object "S_MW2" in the same scope
Info (10281): Verilog HDL Declaration information at fz80.v(893): object "s_out" differs only in case from object "S_OUT" in the same scope
Warning (10268): Verilog HDL information at scandoubler.v(114): always construct contains both blocking and non-blocking assignments
Info (10281): Verilog HDL Declaration information at scandoubler.v(41): object "hq2x" differs only in case from object "Hq2x" in the same scope
Info (10281): Verilog HDL Declaration information at mist_io.v(47): object "SPI_DO" differs only in case from object "spi_do" in the same scope
Warning (10273): Verilog HDL warning at hq2x.sv(247): extended using "x" or "z"
Warning (10230): Verilog HDL assignment warning at mz80k_top.v(30): truncated value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at mz80k_top.v(31): truncated value with size 32 to match size of target (11)
Warning (10230): Verilog HDL assignment warning at fz80.v(1085): truncated value with size 16 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at fz80.v(1128): truncated value with size 8 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at fz80.v(1129): truncated value with size 8 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at fz80.v(1458): truncated value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at i8253.v(80): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i8253.v(81): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i8253.v(84): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i8253.v(85): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i8253.v(88): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i8253.v(89): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i8253.v(106): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at i8253.v(122): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at i8253.v(138): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at vga.v(42): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at vga.v(44): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at vga.v(45): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at vga.v(49): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at vga.v(53): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at vga.v(71): truncated value with size 10 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at vga.v(72): truncated value with size 10 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at vga.v(73): truncated value with size 32 to match size of target (12)
Warning (10230): Verilog HDL assignment warning at vga.v(80): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at vga.v(82): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at vga.v(83): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at vga.v(84): truncated value with size 32 to match size of target (1)

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Analysis & Synthesis Status : Successful - Sun Jun 24 13:30:13 2018
Quartus II 64-Bit Version : 13.1.0 Build 162 10/23/2013 SJ Web Edition
Revision Name : mz80k_mist
Top-level Entity Name : mz80k_mist
Family : Cyclone III
Total logic elements : 3,152
Total combinational functions : 2,886
Dedicated logic registers : 891
Total registers : 891
Total pins : 31
Total virtual pins : 0
Total memory bits : 311,296
Embedded Multiplier 9-bit elements : 0
Total PLLs : 1

215
Sharp - MZ-80K_MiST/Output/mz80k_mist.pin Normal file
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@@ -0,0 +1,215 @@
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- Bank 5: 3.3V
-- Bank 6: 3.3V
-- Bank 7: 3.3V
-- Bank 8: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
-- or leave it unconnected.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Pin directions (input, output or bidir) are based on device operating in user mode.
---------------------------------------------------------------------------------
Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
CHIP "mz80k_mist" ASSIGNED TO AN: EP3C25E144C8
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
VCCD_PLL3 : 1 : power : : 1.2V : :
GNDA3 : 2 : gnd : : : :
VCCA3 : 3 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 4 : : : : 1 :
VCCINT : 5 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 6 : : : : 1 :
LED : 7 : output : 3.3-V LVTTL : : 1 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : 8 : : : : 1 :
nSTATUS : 9 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 10 : : : : 1 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 11 : : : : 1 :
~ALTERA_DCLK~ / RESERVED_INPUT : 12 : input : 3.3-V LVTTL : : 1 : N
CONF_DATA0 : 13 : input : 3.3-V LVTTL : : 1 : Y
nCONFIG : 14 : : : : 1 :
TDI : 15 : input : : : 1 :
TCK : 16 : input : : : 1 :
VCCIO1 : 17 : power : : 3.3V : 1 :
TMS : 18 : input : : : 1 :
GND : 19 : gnd : : : :
TDO : 20 : output : : : 1 :
nCE : 21 : : : : 1 :
GND+ : 22 : : : : 1 :
GND+ : 23 : : : : 1 :
GND+ : 24 : : : : 2 :
GND+ : 25 : : : : 2 :
VCCIO2 : 26 : power : : 3.3V : 2 :
GND : 27 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 28 : : : : 2 :
VCCINT : 29 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 30 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 31 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 32 : : : : 2 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 33 : : : : 2 :
VCCINT : 34 : power : : 1.2V : :
VCCA1 : 35 : power : : 2.5V : :
GNDA1 : 36 : gnd : : : :
VCCD_PLL1 : 37 : power : : 1.2V : :
VCCINT : 38 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 39 : : : : 3 :
VCCIO3 : 40 : power : : 3.3V : 3 :
GND : 41 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 42 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 43 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 44 : : : : 3 :
VCCINT : 45 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 46 : : : : 3 :
VCCIO3 : 47 : power : : 3.3V : 3 :
GND : 48 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 49 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 50 : : : : 3 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 51 : : : : 3 :
GND+ : 52 : : : : 3 :
GND+ : 53 : : : : 3 :
CLOCK_27 : 54 : input : 3.3-V LVTTL : : 4 : Y
GND+ : 55 : : : : 4 :
VCCIO4 : 56 : power : : 3.3V : 4 :
GND : 57 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 58 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 59 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 60 : : : : 4 :
VCCINT : 61 : power : : 1.2V : :
VCCIO4 : 62 : power : : 3.3V : 4 :
GND : 63 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 64 : : : : 4 :
AUDIO_L : 65 : output : 3.3-V LVTTL : : 4 : Y
RESERVED_INPUT_WITH_WEAK_PULLUP : 66 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 67 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 68 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 69 : : : : 4 :
VCCINT : 70 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 71 : : : : 4 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 72 : : : : 4 :
VCCD_PLL4 : 73 : power : : 1.2V : :
GNDA4 : 74 : gnd : : : :
VCCA4 : 75 : power : : 2.5V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 76 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 77 : : : : 5 :
VCCINT : 78 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 79 : : : : 5 :
AUDIO_R : 80 : output : 3.3-V LVTTL : : 5 : Y
VCCIO5 : 81 : power : : 3.3V : 5 :
GND : 82 : gnd : : : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 83 : : : : 5 :
VCCINT : 84 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 85 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 86 : : : : 5 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 87 : : : : 5 :
SPI_DI : 88 : input : 3.3-V LVTTL : : 5 : Y
GND+ : 89 : : : : 5 :
SPI_SS4 : 90 : input : 3.3-V LVTTL : : 6 : Y
SPI_SS3 : 91 : input : 3.3-V LVTTL : : 6 : Y
CONF_DONE : 92 : : : : 6 :
VCCIO6 : 93 : power : : 3.3V : 6 :
MSEL0 : 94 : : : : 6 :
GND : 95 : gnd : : : :
MSEL1 : 96 : : : : 6 :
MSEL2 : 97 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 98 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 99 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 100 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 101 : : : : 6 :
VCCINT : 102 : power : : 1.2V : :
RESERVED_INPUT_WITH_WEAK_PULLUP : 103 : : : : 6 :
RESERVED_INPUT_WITH_WEAK_PULLUP : 104 : : : : 6 :
SPI_DO : 105 : output : 3.3-V LVTTL : : 6 : Y
VGA_G[0] : 106 : output : 3.3-V LVTTL : : 6 : Y
VCCA2 : 107 : power : : 2.5V : :
GNDA2 : 108 : gnd : : : :
VCCD_PLL2 : 109 : power : : 1.2V : :
VGA_G[1] : 110 : output : 3.3-V LVTTL : : 7 : Y
VGA_G[2] : 111 : output : 3.3-V LVTTL : : 7 : Y
VGA_G[3] : 112 : output : 3.3-V LVTTL : : 7 : Y
VGA_G[4] : 113 : output : 3.3-V LVTTL : : 7 : Y
VGA_G[5] : 114 : output : 3.3-V LVTTL : : 7 : Y
VGA_B[0] : 115 : output : 3.3-V LVTTL : : 7 : Y
VCCINT : 116 : power : : 1.2V : :
VCCIO7 : 117 : power : : 3.3V : 7 :
GND : 118 : gnd : : : :
VGA_HS : 119 : output : 3.3-V LVTTL : : 7 : Y
VGA_B[1] : 120 : output : 3.3-V LVTTL : : 7 : Y
VGA_B[2] : 121 : output : 3.3-V LVTTL : : 7 : Y
VCCIO7 : 122 : power : : 3.3V : 7 :
GND : 123 : gnd : : : :
VCCINT : 124 : power : : 1.2V : :
VGA_B[3] : 125 : output : 3.3-V LVTTL : : 7 : Y
SPI_SCK : 126 : input : 3.3-V LVTTL : : 7 : Y
SPI_SS2 : 127 : input : 3.3-V LVTTL : : 7 : Y
GND+ : 128 : : : : 8 :
GND+ : 129 : : : : 8 :
VCCIO8 : 130 : power : : 3.3V : 8 :
GND : 131 : gnd : : : :
VGA_B[4] : 132 : output : 3.3-V LVTTL : : 8 : Y
VGA_B[5] : 133 : output : 3.3-V LVTTL : : 8 : Y
VCCINT : 134 : power : : 1.2V : :
VGA_R[0] : 135 : output : 3.3-V LVTTL : : 8 : Y
VGA_VS : 136 : output : 3.3-V LVTTL : : 8 : Y
VGA_R[1] : 137 : output : 3.3-V LVTTL : : 8 : Y
VCCINT : 138 : power : : 1.2V : :
VCCIO8 : 139 : power : : 3.3V : 8 :
GND : 140 : gnd : : : :
VGA_R[2] : 141 : output : 3.3-V LVTTL : : 8 : Y
VGA_R[3] : 142 : output : 3.3-V LVTTL : : 8 : Y
VGA_R[4] : 143 : output : 3.3-V LVTTL : : 8 : Y
VGA_R[5] : 144 : output : 3.3-V LVTTL : : 8 : Y
GND : EPAD : : : : :

BIN
Sharp - MZ-80K_MiST/Output/mz80k_mist.sof Normal file
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10537
Sharp - MZ-80K_MiST/Output/mz80k_mist.sta.rpt Normal file
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317
Sharp - MZ-80K_MiST/Output/mz80k_mist.sta.summary Normal file
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------------------------------------------------------------
TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Slow 1200mV 85C Model Setup 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -34.936
TNS : -9377.424
Type : Slow 1200mV 85C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -32.140
TNS : -3694.987
Type : Slow 1200mV 85C Model Setup 'mz80k_top:mz80k_top|CLK_2M'
Slack : -7.401
TNS : -121.075
Type : Slow 1200mV 85C Model Setup 'SPI_SCK'
Slack : -7.006
TNS : -594.451
Type : Slow 1200mV 85C Model Setup 'mz80k_top:mz80k_top|CLK_31250'
Slack : -6.618
TNS : -110.932
Type : Slow 1200mV 85C Model Setup 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : -4.583
TNS : -71.203
Type : Slow 1200mV 85C Model Setup 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : -2.023
TNS : -36.640
Type : Slow 1200mV 85C Model Hold 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -0.877
TNS : -2.243
Type : Slow 1200mV 85C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -0.412
TNS : -1.310
Type : Slow 1200mV 85C Model Hold 'mz80k_top:mz80k_top|CLK_31250'
Slack : -0.029
TNS : -0.029
Type : Slow 1200mV 85C Model Hold 'SPI_SCK'
Slack : 0.449
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'mz80k_top:mz80k_top|CLK_2M'
Slack : 0.453
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : 0.675
TNS : 0.000
Type : Slow 1200mV 85C Model Hold 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : 0.735
TNS : 0.000
Type : Slow 1200mV 85C Model Recovery 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -2.223
TNS : -153.204
Type : Slow 1200mV 85C Model Recovery 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 14.024
TNS : 0.000
Type : Slow 1200mV 85C Model Removal 'mz80k_top:mz80k_top|clk_count[2]'
Slack : 0.336
TNS : 0.000
Type : Slow 1200mV 85C Model Removal 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 4.796
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'SPI_SCK'
Slack : -3.201
TNS : -217.003
Type : Slow 1200mV 85C Model Minimum Pulse Width 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -1.487
TNS : -486.249
Type : Slow 1200mV 85C Model Minimum Pulse Width 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : -1.487
TNS : -29.740
Type : Slow 1200mV 85C Model Minimum Pulse Width 'mz80k_top:mz80k_top|CLK_2M'
Slack : -1.487
TNS : -25.279
Type : Slow 1200mV 85C Model Minimum Pulse Width 'mz80k_top:mz80k_top|CLK_31250'
Slack : -1.487
TNS : -25.279
Type : Slow 1200mV 85C Model Minimum Pulse Width 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : -1.487
TNS : -23.792
Type : Slow 1200mV 85C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 9.666
TNS : 0.000
Type : Slow 1200mV 85C Model Minimum Pulse Width 'CLOCK_27'
Slack : 18.366
TNS : 0.000
Type : Slow 1200mV 0C Model Setup 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -33.231
TNS : -8921.813
Type : Slow 1200mV 0C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -30.351
TNS : -3422.841
Type : Slow 1200mV 0C Model Setup 'mz80k_top:mz80k_top|CLK_2M'
Slack : -6.888
TNS : -112.587
Type : Slow 1200mV 0C Model Setup 'SPI_SCK'
Slack : -6.568
TNS : -550.906
Type : Slow 1200mV 0C Model Setup 'mz80k_top:mz80k_top|CLK_31250'
Slack : -6.055
TNS : -101.552
Type : Slow 1200mV 0C Model Setup 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : -4.189
TNS : -65.009
Type : Slow 1200mV 0C Model Setup 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : -1.811
TNS : -32.260
Type : Slow 1200mV 0C Model Hold 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -0.741
TNS : -2.003
Type : Slow 1200mV 0C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -0.535
TNS : -1.806
Type : Slow 1200mV 0C Model Hold 'mz80k_top:mz80k_top|CLK_31250'
Slack : 0.024
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'SPI_SCK'
Slack : 0.402
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'mz80k_top:mz80k_top|CLK_2M'
Slack : 0.403
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : 0.615
TNS : 0.000
Type : Slow 1200mV 0C Model Hold 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : 0.658
TNS : 0.000
Type : Slow 1200mV 0C Model Recovery 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -2.150
TNS : -148.220
Type : Slow 1200mV 0C Model Recovery 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 14.497
TNS : 0.000
Type : Slow 1200mV 0C Model Removal 'mz80k_top:mz80k_top|clk_count[2]'
Slack : 0.319
TNS : 0.000
Type : Slow 1200mV 0C Model Removal 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 4.316
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'SPI_SCK'
Slack : -3.201
TNS : -217.003
Type : Slow 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -1.487
TNS : -486.596
Type : Slow 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : -1.487
TNS : -29.740
Type : Slow 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|CLK_2M'
Slack : -1.487
TNS : -25.279
Type : Slow 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|CLK_31250'
Slack : -1.487
TNS : -25.279
Type : Slow 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : -1.487
TNS : -23.792
Type : Slow 1200mV 0C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 9.638
TNS : 0.000
Type : Slow 1200mV 0C Model Minimum Pulse Width 'CLOCK_27'
Slack : 18.351
TNS : 0.000
Type : Fast 1200mV 0C Model Setup 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -14.921
TNS : -4020.444
Type : Fast 1200mV 0C Model Setup 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -14.623
TNS : -1714.893
Type : Fast 1200mV 0C Model Setup 'mz80k_top:mz80k_top|CLK_2M'
Slack : -2.558
TNS : -41.495
Type : Fast 1200mV 0C Model Setup 'SPI_SCK'
Slack : -2.408
TNS : -184.558
Type : Fast 1200mV 0C Model Setup 'mz80k_top:mz80k_top|CLK_31250'
Slack : -2.296
TNS : -38.342
Type : Fast 1200mV 0C Model Setup 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : -1.305
TNS : -20.020
Type : Fast 1200mV 0C Model Setup 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : -0.305
TNS : -4.130
Type : Fast 1200mV 0C Model Hold 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -0.646
TNS : -4.158
Type : Fast 1200mV 0C Model Hold 'mz80k_top:mz80k_top|CLK_31250'
Slack : -0.187
TNS : -0.187
Type : Fast 1200mV 0C Model Hold 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : -0.063
TNS : -0.175
Type : Fast 1200mV 0C Model Hold 'SPI_SCK'
Slack : 0.147
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'mz80k_top:mz80k_top|CLK_2M'
Slack : 0.187
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : 0.275
TNS : 0.000
Type : Fast 1200mV 0C Model Hold 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : 0.280
TNS : 0.000
Type : Fast 1200mV 0C Model Recovery 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -0.886
TNS : -60.997
Type : Fast 1200mV 0C Model Recovery 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 17.326
TNS : 0.000
Type : Fast 1200mV 0C Model Removal 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -0.025
TNS : -1.350
Type : Fast 1200mV 0C Model Removal 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 2.184
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'SPI_SCK'
Slack : -3.000
TNS : -181.072
Type : Fast 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|clk_count[2]'
Slack : -1.000
TNS : -327.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|vga:vga1|counter[0]'
Slack : -1.000
TNS : -20.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|CLK_2M'
Slack : -1.000
TNS : -17.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|CLK_31250'
Slack : -1.000
TNS : -17.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'mz80k_top:mz80k_top|i8253:i8253_1|signal1'
Slack : -1.000
TNS : -16.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'pll|altpll_component|auto_generated|pll1|clk[0]'
Slack : 9.746
TNS : 0.000
Type : Fast 1200mV 0C Model Minimum Pulse Width 'CLOCK_27'
Slack : 17.928
TNS : 0.000
------------------------------------------------------------

2
Sharp - MZ-80K_MiST/clean.bat
View File

@@ -5,7 +5,7 @@ del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q output
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output

6
Sharp - MZ-80K_MiST/mz80k.qpf → Sharp - MZ-80K_MiST/mz80k_mist.qpf
View File

@@ -18,13 +18,13 @@
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 20:08:26 November 23, 2017
# Date created = 23:59:05 March 16, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "20:08:26 November 23, 2017"
DATE = "23:59:05 March 16, 2017"
# Revisions
PROJECT_REVISION = "mz80k"
PROJECT_REVISION = "mz80k_mist"

171
Sharp - MZ-80K_MiST/mz80k.qsf → Sharp - MZ-80K_MiST/mz80k_mist.qsf
View File

@@ -18,14 +18,14 @@
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 20:08:26 November 23, 2017
# Date created = 18:40:37 November 24, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# mz80k_assignment_defaults.qdf
# ace_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
@@ -34,8 +34,21 @@
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_location_assignment PIN_7 -to LED
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:59:05 MARCH 16, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY Output
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
@@ -63,61 +76,143 @@ set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_90 -to SPI_SS4
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PIN_31 -to UART_RX
set_location_assignment PIN_46 -to UART_TX
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name TOP_LEVEL_ENTITY mz80k
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:08:26 NOVEMBER 23, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name TOP_LEVEL_ENTITY mz80k_mist
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
# Assembler Assignments
# =====================
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/mz80k.sv
set_global_assignment -name VERILOG_FILE rtl/mycom.v
set_global_assignment -name QIP_FILE rtl/vram.qip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
# start EDA_TOOL_SETTINGS(eda_simulation)
# ---------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------
# ----------------------
# start ENTITY(ace_mist)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(ace_mist)
# --------------------
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SYSTEMVERILOG_FILE rtl/mz80k_mist.sv
set_global_assignment -name VERILOG_FILE rtl/mz80k_top.v
set_global_assignment -name VERILOG_FILE rtl/vga.v
set_global_assignment -name VERILOG_FILE rtl/sound.v
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name VERILOG_FILE rtl/ps2.v
set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name QIP_FILE rtl/monrom.qip
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name VERILOG_FILE rtl/keyboard.v
set_global_assignment -name VERILOG_FILE rtl/i8253.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name VERILOG_FILE rtl/ps2.v
set_global_assignment -name VERILOG_FILE rtl/fz80.v
set_global_assignment -name VHDL_FILE rtl/dac.vhd
set_global_assignment -name QIP_FILE rtl/cgrom.qip
set_global_assignment -name VERILOG_FILE rtl/sound.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VERILOG_FILE rtl/sigma_delta_dac.v
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name VERILOG_FILE rtl/cg_rom.v
set_global_assignment -name VERILOG_FILE rtl/ram2.v
set_global_assignment -name VERILOG_FILE rtl/monrom.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

2
Sharp - MZ-80K_MiST/mz80k_mist.srf Normal file
View File

@@ -0,0 +1,2 @@
{ "" "" "" "*" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}

4
Sharp - MZ-80K_MiST/rtl/build_id.v
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@@ -1,2 +1,2 @@
`define BUILD_DATE "171123"
`define BUILD_TIME "223444"
`define BUILD_DATE "180624"
`define BUILD_TIME "132954"

58
Sharp - MZ-80K_MiST/rtl/cgrom.v → Sharp - MZ-80K_MiST/rtl/cg_rom.v
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@@ -4,7 +4,7 @@
// MODULE: altsyncram
// ============================================================
// File Name: cgrom.v
// File Name: cg_rom.v
// Megafunction Name(s):
// altsyncram
//
@@ -14,11 +14,11 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
@@ -36,21 +36,21 @@
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cgrom (
module cg_rom (
address,
clken,
clock,
rden,
q);
input [10:0] address;
input clken;
input clock;
input rden;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
@@ -61,7 +61,7 @@ module cgrom (
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.rden_a (rden),
.clocken0 (clken),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
@@ -71,7 +71,6 @@ module cgrom (
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
@@ -79,17 +78,18 @@ module cgrom (
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "NORMAL",
`ifdef NO_PLI
altsyncram_component.init_file = "../rtl/80KCG.rif"
altsyncram_component.init_file = "./roms/cg.rif"
`else
altsyncram_component.init_file = "../rtl/80KCG.hex"
altsyncram_component.init_file = "./roms/cg.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone III",
@@ -116,9 +116,9 @@ endmodule
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
@@ -126,7 +126,7 @@ endmodule
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../rtl/80KCG.hex"
// Retrieval info: PRIVATE: MIFfilename STRING "./roms/cg.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
@@ -136,12 +136,12 @@ endmodule
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../rtl/80KCG.hex"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: INIT_FILE STRING "./roms/cg.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
@@ -153,17 +153,17 @@ endmodule
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cgrom_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cg_rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cg_rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cg_rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cg_rom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cg_rom_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cg_rom_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

3
Sharp - MZ-80K_MiST/rtl/cgrom.qip
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@@ -1,3 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "cgrom.v"]

48
Sharp - MZ-80K_MiST/rtl/dac.vhd
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@@ -1,48 +0,0 @@
-------------------------------------------------------------------------------
--
-- Delta-Sigma DAC
--
-- Refer to Xilinx Application Note XAPP154.
--
-- This DAC requires an external RC low-pass filter:
--
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dac is
generic (
C_bits : integer := 8
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(C_bits-1 downto 0);
dac_o : out std_logic
);
end dac;
architecture rtl of dac is
signal sig_in: unsigned(C_bits downto 0);
begin
seq: process(clk_i, res_n_i)
begin
if res_n_i = '0' then
sig_in <= to_unsigned(2**C_bits, sig_in'length);
dac_o <= '0';
elsif rising_edge(clk_i) then
-- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
dac_o <= sig_in(C_bits);
end if;
end process seq;
end rtl;

4
Sharp - MZ-80K_MiST/rtl/fz80.v
View File

@@ -367,7 +367,9 @@ mreq, iorq, rd, wr, data_out, busack_out, intack_out, mr,
//
wire mr = g_mr1 | g_mr2; // for debug
wire intack_out = (g_if | g_iack) & intack;
`ifdef M1
wire nmiack_out = g_iack & nmiack;
`endif
// load
wire tmp0 = s_if & (i_rs_r | i_setres_r);
wire tmp1 = s_if & (i_ldrr | incdec8) | s_imm1 & i_ldrn | s_mr1 & i_ldrhl | s_in & i_inrc;
@@ -661,6 +663,8 @@ mreq, iorq, rd, wr, data_out, busack_out, intack_out, mr,
sel_rld | sel_rrd,
sel_fr | sel_rrd
};
wire iff2;
wire co_pc;
//initial $monitor($stime,, self);
// sequencer
seq seq(.data_in(data), .busreq(busreq), .waitreq(waitreq1), .intreq(intreq), .nmireq(nmireq), .reset_in(reset_in), .clk(clk),

459
Sharp - MZ-80K_MiST/rtl/fz80c.v Normal file
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@@ -0,0 +1,459 @@
//
// Z80 Compatible Bus wrapper for fz80 ver.0.52
//
// Version 0.52a
//
// Copyright (c) 2004 Tatsuyuki Sato
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/*
note:
It should be necessary to set "`define M1" inf fz80.
---------------------------------------------------
-----------------------------
non-compatible spesification.
-----------------------------
1.no internal cycle
A internal cycle without bus cycle doesn't exist.
So some instruction is faster than Z80.
2.ealy tristate after reset
The "at" and "dt" assert after 1cycle from reset.
The Z80 is after 2cycles from reset.
3.busreq/busack timming are not checked yet.
4.halt always output 1(no supported).
-------------
state changes
-------------
+------+---+---+---+---+---+---+
|state |t1w|t1 |t2w|t2 |t3 |t4 |
+------+---+---+---+---+---+---+
| M1 | - | O | - | O*| O | O |
| MEM | - | O | - | O*| x | O |
| IO | - | O | - | O*| x | O |
| SpM1 | O | O | O | O | O | O |
+------+---+---+---+---+---+---+
*:sense wait (wait cycle)
histry:
2004. 9.16 ver.0.52a
bugfix power on reset error.
halt_n output always 1 (do not supported yet)
change `MREQ_INSIDE_RD logic.
2004. 9.10 ver.0.52
added power on reset
bugfix mreq inside rd mode
2004. 9. 9 ver.0.51
1st test version
*/
//`define FZ80C_NGC_LINK // xilinx XST link synthesized fz80c.v
//`define DEBUG_OUTPUT
// ----- design option -----
`define MREQ_INSIDE_RD // for wr = (rfsh & ~mreq_n & rd_n);
//`define FZ80C_POWER_ON_RESET // power on self reset
//`define DISABLE_BUSREQ_SYNC // bypass busreq/busack syncronize.
//`define DISABLE_REFRESH_CYCLE // no rfsh cycle & inst code fetch t4 raise
//`define NMI_SYNC_SENSE // nmi fall sense with clk
//`define DO_VAL_IF_DT 8'h00 // "do" set fixed value when output disable
module fz80c (/*AUTOARG*/
// Inputs
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di,
// Outputs
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n,
`ifdef DEBUG_OUTPUT
ts,
wait_window,
`endif
A, At,
do,dt
);
input reset_n,clk;
input wait_n , busrq_n;
input int_n,nmi_n;
input [7:0] di;
output m1_n;
output mreq_n;
output iorq_n;
output rd_n;
output wr_n;
output rfsh_n;
output halt_n;
output busak_n; // (enable controll : mreq_n,iorq_n,rd_n,wr_n,rfsh_n)
output [15:0] A; // Address Bus
output [7:0] do; // Data Bus
output dt; // tristate controll : do
output At; // tristate controll : A
`ifdef DEBUG_OUTPUT
output [3:0] ts;
output wait_window;
`endif
`ifndef FZ80C_NGC_LINK
// internal register
reg [15:0] A;
reg [7:0] dinst_r;
reg [7:0] do_r;
reg [3:0] ts;
reg reset_s;
reg m1_r;
`ifndef DISABLE_REFRESH_CYCLE
reg rfsh_r;
`endif
reg mreq_r;
reg iorq_r;
reg wr_r;
reg rd_r;
reg wait_r;
reg dt_r,dt_t4;
`ifndef DISABLE_BUSREQ_SYNC
reg at_r;
reg busack_r;
reg busreq_r;
`endif
//reg halt_r;
`ifdef NMI_SYNC_SENSE
reg nmi_r1,nmi_r2;
`endif
// auto wait
reg tw1,tw2;
// gate signal base
reg t3l;
reg t04l;
`ifdef FZ80C_POWER_ON_RESET
reg por_n = 0;
reg por2_n = 0;
`endif
//////////////////////////////////////////////////////////////
// FZ80
//////////////////////////////////////////////////////////////
wire start;
wire mreq;
wire iorq;
wire rd;
wire wr;
wire busack;
wire waitreq;
reg intreq;
reg nmireq;
wire busreq;
wire m1;
//wire [7:0] data_in = m1 ? dinst_r : di;
wire [7:0] data_in = ~rfsh_n ? dinst_r : di;
wire [7:0] data_out;
wire [15:0] adr ,radr;
wire nmiack;
//wire halt;
// mreq,iorq inside in rd_wr
//wire req_mask =
fz80 fz80(
.data_in(data_in),
.reset_in(reset_s),
.clk(~clk),
.adr(adr),
.intreq(intreq),
.nmireq(nmireq),
.busreq(busreq),
.start(start),
.mreq(mreq),
.iorq(iorq),
.rd(rd),
.wr(wr),
.data_out(data_out),
.busack_out(busack),
.intack_out(),
.mr(),
.m1(m1),
// .halt(halt),
.radr(radr),
.nmiack_out(nmiack),
.waitreq(waitreq)
);
///////////////////////////////////////////////////////
// wires
///////////////////////////////////////////////////////
// state value
wire t0 = ts[3:0]==0; // t0 : reset cycle
wire t1 = ts[0]; // t1 : spM1 = t1&t2
wire t2 = ts[1]; // t2 : spM1 = tw(1,2)
wire t3 = ts[2]; // M1.t3
wire t4 = ts[3]; // M1.t4 or MEM/IO.t3
wire t04 = ~t1 & ~t2 & ~t3; // T0 or T4
`ifdef DEBUG_OUTPUT
// wait input window
assign wait_window = t2 & ~wait_r;
`endif
// RFSH assert timming
`ifdef DISABLE_REFRESH_CYCLE
wire nxt_rfsh = 1'b0;
`else
wire nxt_rfsh = (m1&t2&wait_r)|t3; // T3 and T4
`endif
///////////////////////////////////////////////////////
// NMI eddge sense
///////////////////////////////////////////////////////
`ifndef NMI_SYNC_SENSE
wire nmi_clr = nmiack | reset_s;
always @(negedge nmi_n or posedge nmi_clr)
begin
if(nmi_clr) nmireq <= #1 1'b0;
else nmireq <= #1 1'b1;
end
`endif
///////////////////////////////////////////////////////
// Timming state controll
///////////////////////////////////////////////////////
`ifdef FZ80C_POWER_ON_RESET
always @(negedge clk)
begin
por_n <= #1 por2_n;
por2_n <= #1 1'b1;
end
// with por
always @(negedge clk or negedge por_n)
if(~por_n) reset_s <= #1 1'b1;
else reset_s <= #1 ~reset_n;
`else
// without por
always @(negedge clk) reset_s <= #1 ~reset_n;
`endif
always @(posedge clk)
begin
if (reset_s)
begin
dinst_r <= #1 8'h00;
ts <= #1 4'b0000; // reset cycle;
A <= #1 16'h0000;
m1_r <= #1 1'b1;
`ifndef DISABLE_REFRESH_CYCLE
rfsh_r <= #1 1'b1;
`endif
intreq <= #1 1'b0;
`ifdef NMI_SYNC_SENSE
nmireq <= #1 1'b0;
nmi_r2 <= #1 1'b0;
nmi_r1 <= #1 1'b0;
`endif
tw1 <= #1 1'b0;
tw2 <= #1 1'b0;
dt_t4 <= #1 1'b1;
`ifndef DISABLE_BUSREQ_SYNC
busreq_r <= #1 1'b1;
busack_r <= #1 1'b1;
at_r <= #1 1'b1;
`endif
iorq_r <= #1 1'b1;
rd_r <= #1 1'b1;
mreq_r <= #1 1'b1;
// halt_r <= #1 1'b1;
end else begin
// T1 T2 on , T3 T4 off
m1_r <= #1 ~m1 | nxt_rfsh;
`ifndef DISABLE_REFRESH_CYCLE
// T3 T4 on , T1 T2 off
rfsh_r <= #1 ~nxt_rfsh;
`endif
// T1(M1),T2,T4(IO) on , T1(IO),T3,T4(M1) off
iorq_r <= #1 ~iorq | t04 | tw1 | nxt_rfsh;
// T1(MEM),T2,T4(MEM) on,T1(IO),T3,T4(M1) off
rd_r <= #1 ~rd | (iorq&t04) | nxt_rfsh;
// T1,T2,T4(MEM) on T3,T4(M1) off
mreq_r <= #1 ~mreq | nxt_rfsh;
// timming state controll
ts[0] <= #1 (t1&tw1) | t04; // t1
ts[1] <= #1 (t2& ~wait_r) | (t1&~tw1); // t2
ts[2] <= #1 (t2& wait_r& m1); // t3
ts[3] <= #1 (t2& wait_r&~m1) | t3; // t4
// auto wait state
tw1 <= #1 ~t1 & (m1&iorq); // TW for SpecialM1
tw2 <= #1 t1 & iorq; // TW for IO and SpecialM1
// address / refresh address
A <= #1 nxt_rfsh ? radr : adr;
// IRQ (T4 raise)
intreq <= #1 ~int_n;
// NMI eddge sense
`ifdef NMI_SYNC_SENSE
nmi_r2 <= #1 nmi_r1;
nmi_r1 <= #1 ~nmi_n;
if(nmiack) nmireq <= #1 1'b0;
else if(~nmi_r2 & nmi_r1) nmireq <= #1 1'b1;
`endif
// Opcode Latch = T3 raise
if(t2) dinst_r <= #1 di;
// data outpot tristate , HOLD half clock in T4
dt_t4 <= #1 dt_r;
// busreq / busack & Address tristate
`ifndef DISABLE_BUSREQ_SYNC
busreq_r <= #1 ~busrq_n;
busack_r <= #1 ~busack;
at_r <= #1 ~busack;
`endif
// halt fetch
// if(m1&t4) halt_r <= #1 ~halt;
end
end
// clk fall event
always @(negedge clk)
begin
if (reset_s)
begin
t3l <= #1 1'b0;
t04l <= #1 1'b1;
wait_r <= #1 1'b1;
wr_r <= #1 1'b1;
dt_r <= #1 1'b1;
do_r <= #1 8'h00;
end else begin
// gate controll
t3l <= #1 t3;
// t4l-t0l | specialM1.t1l
t04l <= #1 t04 | (t1&m1&iorq);
// DataOutput
do_r <= #1 data_out;
// wait sense (T2 raise)
wait_r <= #1 (wait_n | (m1&iorq)) & ~tw2;
// data bus enable , T1,T2 on , T4 off
dt_r <= #1 ~wr | t04;
// T1(IO),T2 on , T1(MEM),T4 off
wr_r <= #1 ~wr | t4 | (mreq&t1);
end
end
/////////////////////////////////////////////////////////////////////////////
// fz80 input
/////////////////////////////////////////////////////////////////////////////
assign waitreq = ~t4;
`ifdef DISABLE_BUSREQ_SYNC
assign busreq = ~busrq_n;
`else
assign busreq = busreq_r;
`endif
/////////////////////////////////////////////////////////////////////////////
// output signal
/////////////////////////////////////////////////////////////////////////////
// MREQ glidge mask
`ifdef MREQ_INSIDE_RD
reg mreq_dly;
always @(posedge clk or negedge rd_n)
begin
if(~rd_n) mreq_dly <= #1 1'b0;
else if(t04) mreq_dly <= #1 rd;
end
reg rd_hold_n;
always @(posedge clk or posedge mreq_n)
begin
if(mreq_n) rd_hold_n <= #1 1'b1;
else rd_hold_n <= #1 mreq_n | rd_n;
end
`else
wire mreq_dly = 0;
wire rd_hold_n = 1;
`endif
assign m1_n = m1_r;
`ifndef DISABLE_REFRESH_CYCLE
assign rfsh_n = rfsh_r;
`else
assign rfsh_n = 1'b1;
`endif
assign mreq_n = (mreq_r| t04l | mreq_dly) & (~t3l | rfsh_n);
assign iorq_n = iorq_r | t04l;
assign rd_n = (rd_r | t04l) & rd_hold_n;
assign wr_n = wr_r | t1;
assign dt = dt_r & dt_t4;
`ifndef DISABLE_BUSREQ_SYNC
assign At = at_r;
assign busak_n = busack_r;
`else
assign At = busack | reset_s;
assign busak_n = busack;
`endif
`ifdef DO_VAL_IF_DT
assign do = dt ? `DO_VAL_IF_DT : do_r;
`else
assign do = do_r;
`endif
//assign halt_n = halt_r;
assign halt_n = 1'b1;
`endif // FZ80C_USER_NGC_LINK
endmodule

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CLOCK_ENABLE_INPUT_A=NORMAL
CLOCK_ENABLE_OUTPUT_A=NORMAL
INIT_FILE=./roms/Mon.hex
INTENDED_DEVICE_FAMILY="Cyclone III"
NUMWORDS_A=32768
OPERATION_MODE=SINGLE_PORT
OUTDATA_ACLR_A=NONE
OUTDATA_REG_A=CLOCK0
POWER_UP_UNINITIALIZED=FALSE
READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
WIDTHAD_A=15
WIDTH_A=8
WIDTH_BYTEENA_A=1
DEVICE_FAMILY="Cyclone III"
address_a
clock0
clocken0
q_a

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`timescale 1ns / 1ps
// ============================================================================
// i8255.v
// - PIO
//
// (C) 2012 Robert Finch, Stratford
// robfinch<remove>@opencores.org
//
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// ============================================================================
//
module i8255(ack_o, rst_i, clk_i, rd_i, we_i, cs_i, adr_i, dat_i, dat_o, a, b, c);
output ack_o;
input rst_i;
input clk_i;
input rd_i;
input we_i;
input cs_i;
input [1:0] adr_i;
input [7:0] dat_i;
output [7:0] dat_o;
reg [7:0] dat_o;
inout [7:0] a;
tri [7:0] a;
inout [7:0] b;
tri [7:0] b;
inout [7:0] c;
tri [7:0] c;
reg [7:0] ao,bo,co; // output registers
reg [7:0] aL,bL; // input latches
reg [1:0] modeA;
reg modeB;
reg [7:0] cio;
reg aio;
reg bio;
wire INTEai = co[4];
wire INTEao = co[6];
wire INTEb = co[2];
wire ackA_n = c[6];
wire stbA_n = c[4];
wire ackB_n = c[2];
wire stbB_n = c[2];
reg ostbA_n,ostbB_n; // old strobe
reg oackA_n,oackB_n; // old acknowledge
reg ack1;
//wire cs = cyc_i && stb_i && (adr_i[15:2]==pIOAddress[15:2]);
always @(posedge clk_i)
ack1 <= cs_i;
assign ack_o = cs_i ? (we_i ? 1'b1 : ack1) : 1'b0;
wire wr = cs_i & we_i;
reg owr; // old write
reg [1:0] oad; // old address
// Input port latches
always @(stbA_n)
if (stbA_n==1'b0)
aL <= a;
always @(stbB_n)
if (stbB_n==1'b0)
bL <= b;
always @(posedge clk_i)
if (rst_i) begin
modeA <= 2'd0;
modeB <= 1'b0;
cio <= 8'hFF;
aio <= 1'b1;
bio <= 1'b1;
ao <= 8'h00;
bo <= 8'h00;
co <= 8'h00;
end
else begin
owr <= wr;
oad <= adr_i[1:0];
ostbA_n <= stbA_n;
ostbB_n <= stbB_n;
oackA_n <= ackA_n;
oackB_n <= ackB_n;
// Ports in Input mode: Negative edge on strobe actives IBF signal
if (stbA_n==1'b0 && ostbA_n==1'b1 && ((modeA==2'd1 && aio) || modeA==2'd2))
co[5] <= 1'b1;
if (stbB_n==1'b0 && ostbB_n==1'b1 && modeB==1'b1 && bio)
co[1] <= 1'b1;
// Ports in input mode: rising edge on strobe sets interrupt output if INTE is set.
if (stbA_n==1'b1 && ostbA_n==1'b0 && ((modeA==2'd1 && aio) || modeA==2'd2))
if (INTEai)
co[3] <= 1'b1;
if (stbB_n==1'b1 && ostbB_n==1'b0 && modeB==1'b1 && bio)
if (INTEb)
co[0] <= 1'b1;
// Ports in output mode: Rising edge on ACK sets interrupt output if INTE is set.
if (!oackA_n & ackA_n && ((modeA==2'd1 && !aio) || modeA==2'd2))
if (INTEao)
co[3] <= 1'b1;
if (!oackB_n & ackB_n && (modeB==1'd1 && !bio))
if (INTEb)
co[0] <= 1'b1;
// Deactivation of write causes OBF_n to be activated
// Output: write causes INTR to be reset
if (!wr & owr) begin
case(oad)
2'd0: begin
if ((modeA==2'd1 && !aio) || modeA==2'd2)
co[7] <= 1'b0;
if ((modeA==2'd1 && !aio) || modeA==2'd2)
if (INTEao)
co[3] <= 1'b0;
end
2'd1: begin
if (modeB==1'b1 && !bio)
co[1] <= 1'b0;
if (modeB==1'b1 && !bio)
if (INTEb)
co[0] <= 1'b0;
end
endcase
end
// falling edge of ACK causes OBF_n to be deactivated
if (oackA_n & !ackA_n && ((modeA==2'b01 && !aio) || modeA==2'd2))
co[7] <= 1'b1;
if (oackB_n & !ackB_n && (modeB==1'b1 && !bio))
co[1] <= 1'b1;
if (cs_i & we_i) begin
case(adr_i[1:0])
2'd0: ao <= dat_i;
2'd1: bo <= dat_i;
2'd2: co <= dat_i;
2'd3:
begin
if (dat_i[7]) begin
modeB <= dat_i[2];
if (dat_i[2]) begin
// Port C pin directions are the same for
// both input and output under mode 1
cio[2] <= 1'b1;
cio[1] <= 1'b0;
cio[0] <= 1'b0;
end
else begin
cio[3] <= dat_i[0]; // This pin control will be overridden by Port A settings.
cio[2] <= dat_i[0];
cio[1] <= dat_i[0];
cio[0] <= dat_i[0];
end
modeA <= dat_i[6:5];
case(dat_i[6:5])
2'b00: begin
cio[7] <= dat_i[3];
cio[6] <= dat_i[3];
cio[5] <= dat_i[3];
cio[4] <= dat_i[3];
end
2'b01: begin
// Mode 1 - Input
if (dat_i[4]) begin
cio[4] <= 1'b1;
cio[5] <= 1'b0;
cio[3] <= 1'b0;
end
// Mode 1 - Output
else begin
cio[7] <= 1'b0;
cio[6] <= 1'b1;
cio[3] <= 1'b0;
end
end
2'b1x: begin
cio[7] <= 1'b0;
cio[6] <= 1'b1;
cio[4] <= 1'b1;
cio[5] <= 1'b0;
cio[3] <= 1'b0;
end
endcase
aio <= dat_i[4];
bio <= dat_i[1];
// Mode change causes port A and C outputs to be
// reset to zero.
if (dat_i[6:5]!=modeA) begin
ao <= 8'h00;
co <= 8'h00;
end
end
else begin
case(dat_i[3:1])
3'd0: co[0] <= dat_i[0];
3'd1: co[1] <= dat_i[0];
3'd2: co[2] <= dat_i[0];
3'd3: co[3] <= dat_i[0];
3'd4: co[4] <= dat_i[0];
3'd5: co[5] <= dat_i[0];
3'd6: co[6] <= dat_i[0];
3'd7: co[7] <= dat_i[0];
endcase
end
end
endcase
end
// Reads
if (cs_i) begin
case(adr_i[1:0])
2'd0: begin
if (modeA==2'b00) // Simple I/O
dat_o <= aio ? a : ao;
else begin // Handshake I/O
// Reading port clears IBF
if (aio==1'b1) begin
dat_o <= aL;
co[5] <= 1'b0;
if (INTEai) // Reading the port resets the interrupt
co[3] <= 1'b0;
end
else
dat_o <= ao;
end
end
2'd1: begin
if (modeB==1'b0)
dat_o <= bio ? b : bo;
else begin
// Reading port clears IBF
if (bio==1'b1) begin
dat_o <= bL;
co[1] <= 1'b0;
if (INTEb) // Reading the port resets the interrupt
co[0] <= 1'b0;
end
else
dat_o <= bo;
end
end
2'd2: dat_o <= {
cio[0] ? c[0] : co[0],
cio[1] ? c[1] : co[1],
cio[2] ? c[2] : co[2],
cio[3] ? c[3] : co[3],
cio[4] ? c[4] : co[4],
cio[5] ? c[5] : co[5],
cio[6] ? c[6] : co[6],
cio[7] ? c[7] : co[7],
};
2'd3: dat_o <= 8'h00; // no read of control word
endcase
end
else
dat_o <= 8'h00;
end
// In mode 2 the I/O is defined as output when ACK is active, otherwise input; the aio setting is a don't care.
assign a =
(modeA==2'd2) ? (ackA_n==1'b0 ? ao : 8'bz) :
aio ? 8'bz : ao;
assign b = bio ? 8'bz : bo;
assign c[0] = cio[0] ? 1'bz : co[0];
assign c[1] = cio[1] ? 1'bz : co[1];
assign c[2] = cio[2] ? 1'bz : co[2];
assign c[3] = cio[3] ? 1'bz : co[3];
assign c[4] = cio[4] ? 1'bz : co[4];
assign c[5] = cio[5] ? 1'bz : co[5];
assign c[6] = cio[6] ? 1'bz : co[6];
assign c[7] = cio[7] ? 1'bz : co[7];
endmodule

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--
-- i8255.vhd
--
-- Intel 8255 (PPI:Programmable Peripheral Interface) partiality compatible module
-- for MZ-700 on FPGA
--
-- Port A : Output, mode 0 only
-- Port B : Input, mode 0 only
-- Port C : Input(7-4)&Output(3-0), mode 0 only, bit set/reset support
--
-- Nibbles Lab. 2005
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity i8255 is
Port ( RST : in std_logic;
A : in std_logic_vector(1 downto 0);
CS : in std_logic;
WR : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
LDDAT : out std_logic_vector(7 downto 0);
-- LDDAT2 : out std_logic;
-- LDSNS : out std_logic;
CLKIN : in std_logic;
KCLK : in std_logic;
-- FCLK : in std_logic;
VBLNK : in std_logic;
INTMSK : out std_logic;
RBIT : in std_logic;
SENSE : in std_logic;
MOTOR : out std_logic;
PS2CK : in std_logic;
PS2DT : in std_logic);
end i8255;
architecture Behavioral of i8255 is
--
-- Port Register
--
signal PA : std_logic_vector(7 downto 0);
signal PB : std_logic_vector(7 downto 0);
signal PC : std_logic_vector(7 downto 0);
--
-- Port Selecter
--
signal SELPA : std_logic;
signal SELPB : std_logic;
signal SELPC : std_logic;
signal SELCT : std_logic;
--
-- CURSOR blink
--
signal TBLNK : std_logic;
signal CCOUNT : std_logic_vector(3 downto 0);
--
-- Remote
--
signal SNS : std_logic;
signal MTR : std_logic;
signal M_ON : std_logic;
signal SENSE0 : std_logic;
signal SWIN : std_logic_vector(3 downto 0);
--
-- Components
--
component keymatrix
Port ( RST : in std_logic;
PA : in std_logic_vector(3 downto 0);
PB : out std_logic_vector(7 downto 0);
KCLK : in std_logic;
LDDAT : out std_logic_vector(7 downto 0);
PS2CK : in std_logic;
PS2DT : in std_logic);
end component;
begin
--
-- Instantiation
--
keys : keymatrix port map (
RST => RST,
PA => PA(3 downto 0),
PB => PB,
KCLK => KCLK,
LDDAT => LDDAT,
PS2CK => PS2CK,
PS2DT => PS2DT);
--
-- Port select for Output
--
SELPA<='1' when A="00" else '0';
SELPB<='1' when A="01" else '0';
SELPC<='1' when A="10" else '0';
SELCT<='1' when A="11" else '0';
--
-- Output
--
process( RST, WR, CS ) begin
if( RST='0' ) then
PA<=(others=>'0');
-- PB<=(others=>'0');
PC<=(others=>'0');
elsif( WR'event and WR='1' and CS='0' ) then
if( SELPA='1' ) then
PA<=DI;
end if;
-- if( SELPB='1' ) then
-- PB<=DI;
-- end if;
if( SELPC='1' ) then
PC(3 downto 0)<=DI(3 downto 0);
end if;
if( SELCT='1' and DI(7)='0' ) then
case DI(3 downto 0) is
when "0000" => PC(0)<='0';
when "0001" => PC(0)<='1';
when "0010" => PC(1)<='0';
when "0011" => PC(1)<='1';
when "0100" => PC(2)<='0';
when "0101" => PC(2)<='1';
when "0110" => PC(3)<='0';
when "0111" => PC(3)<='1';
-- when "1000" => PC(4)<='0';
-- when "1001" => PC(4)<='1';
-- when "1010" => PC(5)<='0';
-- when "1011" => PC(5)<='1';
-- when "1100" => PC(6)<='0';
-- when "1101" => PC(6)<='1';
-- when "1110" => PC(7)<='0';
-- when "1111" => PC(7)<='1';
when others => PC<="XXXXXXXX";
end case;
end if;
end if;
end process;
--
-- CURSOR blink Clock
--
process( CLKIN, PA(7) ) begin
if( PA(7)='0' ) then
CCOUNT<=(others=>'0');
elsif( CLKIN'event and CLKIN='1' ) then
CCOUNT<=CCOUNT+'1';
if( CCOUNT=13 ) then
CCOUNT<=(others=>'0');
TBLNK<=not TBLNK;
end if;
end if;
end process;
--
-- Input select
--
DO<=PB when SELPB='1' else
VBLNK&TBLNK&RBIT&MTR&PC(3 downto 0) when SELPC='1' else (others=>'1');
--
-- Remote
--
MOTOR<=MTR;
process( KCLK ) begin
if( KCLK'event and KCLK='1' ) then
M_ON<=PC(3);
SNS<=SENSE0;
if( SENSE0='1' ) then
MTR<='0';
elsif( SNS='1' and SENSE0='0' ) then
MTR<='1';
elsif( M_ON='0' and PC(3)='1' ) then
MTR<=not MTR;
end if;
SWIN<=SWIN(2 downto 0)&(not SENSE);
if( SWIN="1111" and SENSE='0' ) then
SENSE0<='0';
elsif( SWIN="0000" and SENSE='1' ) then
SENSE0<='1';
end if;
end if;
end process;
--
-- Others
--
INTMSK<=PC(2);
end Behavioral;

18
Sharp - MZ-80K_MiST/rtl/keyboard.v → Sharp - MZ-80K_MiST/rtl/keyboard.sv
View File

@@ -29,18 +29,14 @@ always @(negedge clk) begin
if(input_strobe) begin
case(code)
'h16: joystick[1] <= ~release_btn; // 1
'h1E: joystick[2] <= ~release_btn; // 2
'h75: joystick[4] <= ~release_btn; // arrow up
'h75: joystick[7] <= ~release_btn; // arrow up
'h74: joystick[6] <= ~release_btn; // arrow right
'h72: joystick[5] <= ~release_btn; // arrow down
'h6B: joystick[6] <= ~release_btn; // arrow left
'h74: joystick[7] <= ~release_btn; // arrow right
'h29: joystick[0] <= ~release_btn; // Space
// 'h11: joystick[1] <= ~release_btn; // Left Alt
// 'h0d: joystick[2] <= ~release_btn; // Tab
'h76: joystick[3] <= ~release_btn; // Escape
'h6B: joystick[4] <= ~release_btn; // arrow left
'h16: joystick[3] <= ~release_btn; // 1
'h1E: joystick[2] <= ~release_btn; // 2
'h26: joystick[1] <= ~release_btn; // 3
'h25: joystick[0] <= ~release_btn; // 4
endcase
end
end

73
Sharp - MZ-80K_MiST/rtl/mist_io.v
View File

@@ -82,12 +82,13 @@ module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
output reg ps2_kbd_data,
output ps2_mouse_clk,
output reg ps2_mouse_data,
input ps2_caps_led,
// ARM -> FPGA download
input ioctl_force_erase,
output reg ioctl_download = 0, // signal indicating an active download
output reg ioctl_erasing = 0, // signal indicating an active erase
output reg [7:0] ioctl_index, // menu index used to upload the file
output ioctl_wr,
output reg ioctl_wr = 0,
output reg [24:0] ioctl_addr,
output reg [7:0] ioctl_dout
);
@@ -96,7 +97,7 @@ reg [7:0] b_data;
reg [6:0] sbuf;
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [9:0] byte_cnt; // counts bytes
reg [7:0] byte_cnt; // counts bytes
reg [7:0] but_sw;
reg [2:0] stick_idx;
@@ -119,8 +120,6 @@ wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
reg spi_do;
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1};
// drive MISO only when transmitting core id
always@(negedge SPI_SCK) begin
if(!CONF_DATA0) begin
@@ -149,10 +148,6 @@ always@(negedge SPI_SCK) begin
8'h18:
spi_do <= b_data[~bit_cnt];
// reading keyboard LED status
8'h1f:
spi_do <= kbd_led[~bit_cnt];
default:
spi_do <= 0;
endcase
@@ -451,7 +446,14 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(SPI_DI) begin
addr <= 0;
case(ioctl_index)
0: addr <= 'h080000; // BOOT ROM
'h01: addr <= 'h000100; // ROM file
'h41: addr <= 'h000100; // COM file
'h81: addr <= 'h000000; // C00 file
'hC1: addr <= 'h010000; // EDD file
default: addr <= 'h100000; // FDD file
endcase
ioctl_download <= 1;
end else begin
addr_w <= addr;
@@ -471,21 +473,60 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin
end
end
assign ioctl_wr = |ioctl_wrd;
reg [1:0] ioctl_wrd;
reg [24:0] erase_mask;
wire [24:0] next_erase = (ioctl_addr + 1'd1) & erase_mask;
always@(negedge clk_sys) begin
always@(posedge clk_sys) begin
reg rclkD, rclkD2;
reg old_force = 0;
reg [5:0] erase_clk_div;
reg [24:0] end_addr;
reg erase_trigger = 0;
rclkD <= rclk;
rclkD2 <= rclkD;
ioctl_wrd<= {ioctl_wrd[0],1'b0};
ioctl_wr <= 0;
if(rclkD & ~rclkD2) begin
ioctl_dout <= data_w;
ioctl_addr <= addr_w;
ioctl_wrd <= 2'b11;
ioctl_wr <= 1;
end
if(ioctl_download) begin
old_force <= 0;
ioctl_erasing <= 0;
erase_trigger <= (ioctl_index == 1);
end else begin
old_force <= ioctl_force_erase;
// start erasing
if(erase_trigger) begin
erase_trigger <= 0;
erase_mask <= 'hFFFF;
end_addr <= 'h0100;
erase_clk_div <= 1;
ioctl_erasing <= 1;
end else if((ioctl_force_erase & ~old_force)) begin
erase_trigger <= 0;
ioctl_addr <= 'h1FFFFFF;
erase_mask <= 'h1FFFFFF;
end_addr <= 'h0050000;
erase_clk_div <= 1;
ioctl_erasing <= 1;
end else if(ioctl_erasing) begin
erase_clk_div <= erase_clk_div + 1'd1;
if(!erase_clk_div) begin
if(next_erase == end_addr) ioctl_erasing <= 0;
else begin
ioctl_addr <= next_erase;
ioctl_dout <= 0;
ioctl_wr <= 1;
end
end
end
end
end
endmodule
endmodule

3
Sharp - MZ-80K_MiST/rtl/monrom.qip
View File

@@ -1,3 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "monrom.v"]

42
Sharp - MZ-80K_MiST/rtl/monrom.v
View File

@@ -14,11 +14,11 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
@@ -38,23 +38,23 @@
// synopsys translate_on
module monrom (
address,
clken,
clock,
data,
rden,
wren,
q);
input [14:0] address;
input clken;
input clock;
input [7:0] data;
input rden;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
@@ -67,7 +67,7 @@ module monrom (
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.rden_a (rden),
.clocken0 (clken),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
@@ -77,22 +77,22 @@ module monrom (
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "NORMAL",
`ifdef NO_PLI
altsyncram_component.init_file = "80ktc.rif"
altsyncram_component.init_file = "./roms/Mon.rif"
`else
altsyncram_component.init_file = "80ktc.hex"
altsyncram_component.init_file = "./roms/Mon.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone III",
@@ -122,9 +122,9 @@ endmodule
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
@@ -133,7 +133,7 @@ endmodule
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "80ktc.hex"
// Retrieval info: PRIVATE: MIFfilename STRING "./roms/Mon.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
@@ -146,11 +146,11 @@ endmodule
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "80ktc.hex"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: INIT_FILE STRING "./roms/Mon.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
@@ -164,15 +164,15 @@ endmodule
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL monrom.v TRUE

139
Sharp - MZ-80K_MiST/rtl/mycom.v
View File

@@ -1,139 +0,0 @@
module mycom(CLK_50MHZ, BTN_NORTH,BTN_EAST,BTN_SOUTH, BTN_WEST,
VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC, Pix_ce,
PS2_CLK, PS2_DATA, Turbo,
SW,LED,TP1);
input CLK_50MHZ;
input BTN_NORTH,BTN_EAST,BTN_SOUTH,BTN_WEST;
input PS2_CLK, PS2_DATA;
input Turbo;
output VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC;
output Pix_ce;
input [3:0] SW;
output [7:0] LED;
output TP1;
// <EFBFBD>N<EFBFBD><EFBFBD><EFBFBD>b<EFBFBD>N<EFBFBD>̐<EFBFBD><EFBFBD><EFBFBD>
wire CLK_CPU;
reg CLK_2M = 0, CLK_31250 = 0;
reg [4:0] count_2M = 0;
reg [10:0] count_31250 = 0;
reg [32:0] clk_count = 0;
always @(posedge CLK_50MHZ) begin
clk_count <= clk_count + 1;
end
always @(posedge CLK_50MHZ) begin
count_2M <= count_2M >= 13 ? 0 : count_2M + 1;
count_31250 <= count_31250 >= 800 ? 0 : count_31250 + 1;
CLK_2M <= count_2M == 0 ? ~CLK_2M : CLK_2M;
CLK_31250 <= count_31250 == 0 ? ~CLK_31250 : CLK_31250;
end
assign CLK_CPU = Turbo ? clk_count[2] : clk_count[3];
// assign CLK_CPU = clk_count[2]; // 6MHZ
// assign CLK_CPU = clk_count[3]; // 3MHZ
// reset<EFBFBD><EFBFBD><EFBFBD>H
wire reset;
reg reset1 = 1, reset2 = 1;
always @( posedge CLK_CPU ) begin
reset1 <= BTN_EAST;
reset2 <= reset1;
end
assign reset = reset1 | reset2;
// Z80<EFBFBD><EFBFBD>WIRE<EFBFBD><EFBFBD><EFBFBD>`
wire [15:0] cpu_addr;
wire [7:0] cpu_data_in, cpu_data_out;
wire mreq, iorq, rd, wr, busreq, busack, intack;
wire start, waitreq;
// I/O<EFBFBD>̎<EFBFBD><EFBFBD>
wire [15:0]io_led,io_e000,io_e001,io_e002,io_8253,io_e008;
assign io_led = (cpu_addr[15:0] == 16'he300) & mreq;
assign io_e000 = (cpu_addr[15:0] == 16'he000) & mreq;
assign io_e001 = (cpu_addr[15:0] == 16'he001) & mreq;
assign io_e002 = (cpu_addr[15:0] == 16'he002) & mreq;
assign io_8253 = (cpu_addr[15:2] == 14'b11100000000001) & mreq;
assign io_e008 = (cpu_addr[15:0] == 16'he008) & mreq;
wire [7:0] io_switch = {BTN_NORTH,BTN_EAST,BTN_SOUTH,
BTN_WEST,SW[3:0]};
reg [7:0] led_buf;
reg [7:0] sound_buf;
reg [3:0] key_no;
reg speaker_enable;
always @(posedge CLK_CPU or posedge reset) begin
if (reset) begin
led_buf <= 0;
sound_buf <= 0;
key_no <= 0;
speaker_enable <= 0;
end else begin
if ( io_led & wr ) begin
led_buf <= cpu_data_out;
end else if (io_e000 & wr ) begin
key_no <= cpu_data_out[3:0];
end else if (io_e008 & wr ) begin
speaker_enable <= cpu_data_out[0];
end
end
end
assign LED = led_buf;
// Z80<EFBFBD>̎<EFBFBD><EFBFBD>
assign waitreq = start;
wire out0, out1, out2;
fz80 z80(.data_in(cpu_data_in), .data_out(cpu_data_out),
.reset_in(reset), .clk(CLK_CPU),
.mreq(mreq), .iorq(iorq), .rd(rd), .wr(wr),
.adr(cpu_addr), .waitreq(waitreq),
.nmireq(0), .intreq(out2 & 0), .busreq(busreq), .busack_out(busack),
.start(start));
// 8253<EFBFBD>̎<EFBFBD><EFBFBD> (CLK0=2M CLK1=31.25K CLK2=OUT1)
wire [7:0] i8253_data_out;
i8253 i8253_1(.reset(reset), .clk(CLK_CPU), .addr(cpu_addr[1:0]), .data_out(i8253_data_out), .data_in(cpu_data_out),
.cs(io_8253 & ~start), .rd(rd), .wr(wr),
.clk0(CLK_2M), .clk1(CLK_31250), .clk2(out1),
.out0(out0), .out1(out1), .out2(out2) );
// KEYBOARD<EFBFBD>̎<EFBFBD><EFBFBD>
wire [7:0] ps2_data;
ps2 ps2_1(.clk(CLK_50MHZ), .reset(reset), .ps2_clk(PS2_CLK), .ps2_data(PS2_DATA), .cs(io_e001 & rd), .rd(rd), .addr(key_no), .data(ps2_data));
// MAIN RAM<EFBFBD>̎<EFBFBD><EFBFBD>
wire ram_select = (( cpu_addr[15:15] == 1'b0 || cpu_addr[15:12] == 4'b1000) & mreq) & ~busack;
wire ram_en, ram_we;
wire [7:0] ram_data_out, ram_data_in;
monrom monrom(.address(cpu_addr),.clock(CLK_50MHZ),.data(ram_data_in),
.q(ram_data_out),.rden(ram_en),.wren(ram_we));
assign ram_en = ram_select;
assign ram_we = wr;
assign ram_data_in = cpu_data_out;
// VRAM<EFBFBD>̎<EFBFBD><EFBFBD>
wire vram_select = ((cpu_addr[15:11] == 5'b11010) & mreq) | busack;
wire [11:0] vram_addr;
wire vram_rd, vram_wr;
wire [7:0] vram_data, vram_data_in;
vram vram(.address(vram_addr),.clock(CLK_50MHZ),
.data(vram_data_in),.q(vram_data),.rden(vram_select),.wren(vram_wr));
assign vram_data_in = (vram_select & wr) ? cpu_data_out : 8'hzz;
// VGA<EFBFBD>̎<EFBFBD><EFBFBD>
wire [11:0] vga_addr;
vga vga1(.CLK_50MHZ(CLK_50MHZ), .VGA_RED(VGA_RED), .VGA_GREEN(VGA_GREEN), .VGA_BLUE(VGA_BLUE),
.VGA_HSYNC(VGA_HSYNC), .VGA_VSYNC(VGA_VSYNC), .Pix_ce(Pix_ce),
.VGA_ADDR(vga_addr), .VGA_DATA(vram_data), .BUS_REQ(busreq), .BUS_ACK(busack));
assign vram_addr[11:0] = busack ? vga_addr[11:0] : cpu_addr[11:0];
assign vram_rd = busack | rd;
assign vram_wr = busack ? 1'b0 : wr;
// Memory<EFBFBD>A<EFBFBD>N<EFBFBD>Z<EFBFBD>X
assign cpu_data_in = ( io_led & rd ) ? io_switch :
( io_e001 & rd ) ? ps2_data :
( io_e002 & rd ) ? {VGA_VSYNC, clk_count[24], 6'b0000000} :
( io_8253 & rd ) ? i8253_data_out :
( io_e008 & rd ) ? {7'b0000000, clk_count[19]} : // MUSIC<EFBFBD><EFBFBD><EFBFBD>Ȃǂ<EFBFBD>WAIT<EFBFBD>ŏd<EFBFBD>v
(vram_select & rd) ? vram_data :
(ram_select & rd) ? ram_data_out: 8'hzz;
assign TP1 = speaker_enable & out0;
endmodule

136
Sharp - MZ-80K_MiST/rtl/mz80k.sv
View File

@@ -1,136 +0,0 @@
module mz80k
(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"MZ80K;;",
"O2,CPU CLOCK ,6MHZ,3MHZ;",
"O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
"T6,Reset;",
"V,v1.00.",`BUILD_DATE
};
wire clk_sys;
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] kbjoy;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoubler_disable;
wire ypbpr;
wire ps2_kbd_clk, ps2_kbd_data;
wire [7:0] audio;
//assign LED = 1;
wire hblank, vblank;
wire ce_vid;
wire hs, vs;
wire r,g,b;
pll pll
(
.inclk0(CLOCK_27),
.c0(clk_sys)
);
video_mixer #(.LINE_LENGTH(640), .HALF_DEPTH(1)) video_mixer
(
.clk_sys(clk_sys),
.ce_pix(ce_vid),
.ce_pix_actual(ce_vid),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R({r,r,r}),
.G({g,g,g}),
.B({b,b,b}),
.HSync(hs),
.VSync(vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.scandoubler_disable(1),//scandoubler_disable),
.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
.hq2x(status[4:3]==1),
.ypbpr_full(1),
.line_start(0),
.mono(0)
);
mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_SCK (SPI_SCK ),
.CONF_DATA0 (CONF_DATA0 ),
.SPI_SS2 (SPI_SS2 ),
.SPI_DO (SPI_DO ),
.SPI_DI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable(scandoubler_disable),
.ypbpr (ypbpr ),
.ps2_kbd_clk (ps2_kbd_clk ),
.ps2_kbd_data (ps2_kbd_data ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
mycom mycom
(
.CLK_50MHZ(clk_sys),
.BTN_NORTH(),
.BTN_EAST((status[0] | status[6] | buttons[1])),//reset
.BTN_SOUTH(),
.BTN_WEST(),
.VGA_RED(r),
.VGA_GREEN(g),
.VGA_BLUE(b),
.VGA_HSYNC(hs),
.VGA_VSYNC(vs),
.Turbo(status[2]),
.Pix_ce(ce_vid),
.PS2_CLK(ps2_kbd_clk),
.PS2_DATA(ps2_kbd_data),
.SW(),
.LED(LED),
.TP1(audio)
);
dac dac
(
.clk_i(clk_sys),
.res_n_i(1),
.dac_i(audio),
.dac_o(AUDIO_L)
);
assign AUDIO_R = AUDIO_L;
endmodule

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module mz80k_mist(
input CLOCK_27,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output LED,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input SPI_SS4,
input CONF_DATA0/*,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE*/
);
`include "rtl\build_id.v"
assign LED = 1;
localparam CONF_STR = {
"Sharp MZ80K;MZF;",
// "O34,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
"O2,CPU Clock, 3Mhz, 6Mhz;",
"T5,Reset;",
"V,v0.2.",`BUILD_DATE
};
wire clk_sys;
wire clk_12p5;
wire locked;
wire scandoubler_disable;
wire ypbpr;
wire ps2_kbd_clk, ps2_kbd_data;
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire audio;
wire r, g, b;
wire hs, vs;
wire [7:0] kb_ext;
pll pll(
.areset(),
.inclk0(CLOCK_27),
.c0(clk_sys),//50.0Mhz
.c1(clk_12p5),//12.5Mhz
.locked(locked)
);
reg [7:0] reset_cnt;
always @(posedge clk_sys) begin
if(!locked || buttons[1] || status[0] || status[5])
reset_cnt <= 8'h0;
else if(reset_cnt != 8'd255)
reset_cnt <= reset_cnt + 8'd1;
end
wire reset = (reset_cnt != 8'd255);
mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
(
.conf_str(CONF_STR),
.clk_sys(clk_sys),
.SPI_SCK(SPI_SCK),
.CONF_DATA0(CONF_DATA0),
.SPI_SS2(SPI_SS2),
.SPI_DO(SPI_DO),
.SPI_DI(SPI_DI),
.buttons(buttons),
.switches(switches),
.scandoubler_disable(scandoubler_disable),
.ypbpr(ypbpr),
.status(status),
.ps2_kbd_clk(ps2_kbd_clk),
.ps2_kbd_data(ps2_kbd_data)
);
video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer
(
.clk_sys(clk_sys),
.ce_pix(clk_12p5),
.ce_pix_actual(clk_12p5),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 3, status[4:3] == 2}),
.scandoubler_disable(1),//scandoubler_disable),
.hq2x(status[4:3]==1),
.ypbpr(ypbpr),
.ypbpr_full(1),
.R({r,r,r}),
.G({g,g,g}),
.B({b,b,b}),
.mono(0),
.HSync(hs),
.VSync(vs),
.line_start(0),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS)
);
sigma_delta_dac #(.MSBI(2)) sigma_delta_dac
(
.DACout(AUDIO_L),
.DACin({audio,audio,audio}),
.CLK(clk_sys),
.RESET(0)
);
assign AUDIO_R = AUDIO_L;
mz80k_top mz80k_top(
.CLK_50MHZ(clk_sys),
.RESET(reset),
.PS2_CLK(ps2_kbd_clk),
.PS2_DATA(ps2_kbd_data),
.VGA_RED(r),
.VGA_GREEN(g),
.VGA_BLUE(b),
.VGA_HSYNC(hs),
.VGA_VSYNC(vs),
.TURBO(status[2]),
.TP1(audio)
);
keyboard keyboard(
.clk(clk_sys),
.reset(0),
.ps2_kbd_clk(ps2_kbd_clk),
.ps2_kbd_data(ps2_kbd_data),
.joystick(kb_ext)
);
endmodule

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module mz80k_top(
input CLK_50MHZ,
input RESET,
input PS2_CLK,
input PS2_DATA,
output VGA_RED,
output VGA_GREEN,
output VGA_BLUE,
output VGA_HSYNC,
output VGA_VSYNC,
input [7:0] SW,
input TURBO,
input SCREEN,
output TP1
);
wire CLK_CPU;
reg CLK_2M = 0, CLK_31250 = 0;
reg [4:0] count_2M = 0;
reg [10:0] count_31250 = 0;
reg [32:0] clk_count = 0;
always @(posedge CLK_50MHZ) begin
clk_count <= clk_count + 1;
end
always @(posedge CLK_50MHZ) begin
count_2M <= count_2M >= 13 ? 0 : count_2M + 1;
count_31250 <= count_31250 >= 800 ? 0 : count_31250 + 1;
CLK_2M <= count_2M == 0 ? ~CLK_2M : CLK_2M;
CLK_31250 <= count_31250 == 0 ? ~CLK_31250 : CLK_31250;
end
assign CLK_CPU = TURBO ? clk_count[2] : clk_count[3]; // 3MHZ
// Z80
wire [15:0] cpu_addr;
wire [7:0] cpu_data_in, cpu_data_out;
wire mreq, iorq, rd, wr, busreq, busack, intack;
wire start, waitreq;
// I/O
wire io_e000 = (cpu_addr[15:0] == 16'he000) & mreq;
wire io_e001 = (cpu_addr[15:0] == 16'he001) & mreq;
wire io_e002 = (cpu_addr[15:0] == 16'he002) & mreq;
wire io_8253 = (cpu_addr[15:2] == 14'b11100000000001) & mreq;
wire io_e008 = (cpu_addr[15:0] == 16'he008) & mreq;
reg [3:0] key_no;
reg speaker_enable;
always @(posedge CLK_CPU or posedge RESET) begin
if (RESET) begin
key_no <= 0;
speaker_enable <= 0;
end else begin
if (io_e000 & wr ) begin
key_no <= cpu_data_out[3:0];
end else if (io_e008 & wr ) begin
speaker_enable <= cpu_data_out[0];
end
end
end
// Z80
assign waitreq = start;
wire out0, out1, out2;
fz80 z80(
.data_in(cpu_data_in),
.data_out(cpu_data_out),
.reset_in(RESET),
.clk(CLK_CPU),
.mreq(mreq),
.iorq(iorq),
.rd(rd),
.wr(wr),
.adr(cpu_addr),
.waitreq(waitreq),
.nmireq(0),
.intreq(out2 & 0),
.busreq(busreq),
.busack_out(busack),
.start(start)
);
// 8253(CLK0=2M CLK1=31.25K CLK2=OUT1)
wire [7:0] i8253_data_out;
i8253 i8253_1(
.reset(RESET),
.clk(CLK_CPU),
.addr(cpu_addr[1:0]),
.data_out(i8253_data_out),
.data_in(cpu_data_out),
.cs(io_8253 & ~start),
.rd(rd),
.wr(wr),
.clk0(CLK_2M),
.clk1(CLK_31250),
.clk2(out1),
.out0(out0),
.out1(out1),
.out2(out2)
);
// KEYBOARD
wire [7:0] ps2_dat;
ps2 ps2_1(
.clk(CLK_50MHZ),
.reset(RESET),
.ps2_clk(PS2_CLK),
.ps2_data(PS2_DATA),
.cs(io_e001 & rd),
.rd(rd),
.addr(key_no),
.data(ps2_dat)
);
// VGA
wire [11:0] vga_addr;
vga vga1(
.CLK_50MHZ(CLK_50MHZ),
.VGA_RED(VGA_RED),
.VGA_GREEN(VGA_GREEN),
.VGA_BLUE(VGA_BLUE),
.VGA_HSYNC(VGA_HSYNC),
.VGA_VSYNC(VGA_VSYNC),
.VGA_ADDR(vga_addr),
.VGA_DATA(vram_data),
.BUS_REQ(busreq),
.BUS_ACK(busack)
);
// MAIN RAM
wire ram_select = (( cpu_addr[15:15] == 1'b0 || cpu_addr[15:12] == 4'b1000) & mreq) & ~busack;
wire ram_en, ram_we;
wire [7:0] ram_data_out, ram_data_in;
monrom mon_rom(
.address(cpu_addr),
.clock(CLK_50MHZ),
.data(ram_data_in),
.q(ram_data_out),
.clken(ram_en),
.wren(ram_we)
);
assign ram_en = ram_select;
assign ram_we = wr;
assign ram_data_in = cpu_data_out;
// VRAM
wire vram_select = ((cpu_addr[15:11] == 5'b11010) & mreq) | busack;
wire [11:0] vram_addr;
wire vram_rd, vram_wr;
wire [7:0] vram_data, vram_data_in;
ram2 ram2_2(
.address(vram_addr),
.clock(CLK_50MHZ),
.data(vram_data_in),
.q(vram_data),
.clken(vram_select),
.rden(vram_rd),
.wren(vram_wr)
);
assign vram_data_in = (vram_select & wr) ? cpu_data_out : 8'hzz;
assign vram_addr[11:0] = busack ? vga_addr[11:0] : cpu_addr[11:0];
assign vram_rd = busack | rd;
assign vram_wr = busack ? 1'b0 : wr;
// Memory
assign cpu_data_in =
( io_e001 & rd ) ? ps2_dat :
( io_e002 & rd ) ? {VGA_VSYNC, clk_count[24], 6'b0000000} :
( io_8253 & rd ) ? i8253_data_out :
( io_e008 & rd ) ? {7'b0000000, clk_count[19]} : // MUSIC<EFBFBD><EFBFBD><EFBFBD>Ȃǂ<EFBFBD>WAIT<EFBFBD>ŏd<EFBFBD>v
(vram_select & rd) ? vram_data :
(ram_select & rd) ? ram_data_out: 8'hzz;
assign TP1 = speaker_enable & out0;
endmodule

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/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file monrom.v when simulating
// the core, monrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module monrom(
addr,
clk,
din,
dout,
en,
we);
input [15 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input we;
// synthesis translate_off
BLKMEMSP_V6_2 #(
.c_addr_width(16),
.c_default_data("0"),
.c_depth(36864),
.c_enable_rlocs(0),
.c_has_default_data(0),
.c_has_din(1),
.c_has_en(1),
.c_has_limit_data_pitch(0),
.c_has_nd(0),
.c_has_rdy(0),
.c_has_rfd(0),
.c_has_sinit(0),
.c_has_we(1),
.c_limit_data_pitch(18),
.c_mem_init_file("monrom.mif"),
.c_pipe_stages(0),
.c_reg_inputs(0),
.c_sinit_value("0"),
.c_width(8),
.c_write_mode(0),
.c_ybottom_addr("0"),
.c_yclk_is_rising(1),
.c_yen_is_high(1),
.c_yhierarchy("hierarchy1"),
.c_ymake_bmm(0),
.c_yprimitive_type("16kx1"),
.c_ysinit_is_high(1),
.c_ytop_addr("1024"),
.c_yuse_single_primitive(0),
.c_ywe_is_high(1),
.c_yydisable_warnings(1))
inst (
.ADDR(addr),
.CLK(clk),
.DIN(din),
.DOUT(dout),
.EN(en),
.WE(we),
.ND(),
.RFD(),
.RDY(),
.SINIT());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of monrom is "black_box"
endmodule

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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file monrom.vhd when simulating
-- the core, monrom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY monrom IS
port (
addr: IN std_logic_VECTOR(15 downto 0);
clk: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
dout: OUT std_logic_VECTOR(7 downto 0);
en: IN std_logic;
we: IN std_logic);
END monrom;
ARCHITECTURE monrom_a OF monrom IS
-- synthesis translate_off
component wrapped_monrom
port (
addr: IN std_logic_VECTOR(15 downto 0);
clk: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
dout: OUT std_logic_VECTOR(7 downto 0);
en: IN std_logic;
we: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_monrom use entity XilinxCoreLib.blkmemsp_v6_2(behavioral)
generic map(
c_sinit_value => "0",
c_has_en => 1,
c_reg_inputs => 0,
c_yclk_is_rising => 1,
c_ysinit_is_high => 1,
c_ywe_is_high => 1,
c_yprimitive_type => "16kx1",
c_ytop_addr => "1024",
c_yhierarchy => "hierarchy1",
c_has_limit_data_pitch => 0,
c_has_rdy => 0,
c_write_mode => 0,
c_width => 8,
c_yuse_single_primitive => 0,
c_has_nd => 0,
c_has_we => 1,
c_enable_rlocs => 0,
c_has_rfd => 0,
c_has_din => 1,
c_ybottom_addr => "0",
c_pipe_stages => 0,
c_yen_is_high => 1,
c_depth => 36864,
c_has_default_data => 0,
c_limit_data_pitch => 18,
c_has_sinit => 0,
c_mem_init_file => "monrom.mif",
c_yydisable_warnings => 1,
c_default_data => "0",
c_ymake_bmm => 0,
c_addr_width => 16);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_monrom
port map (
addr => addr,
clk => clk,
din => din,
dout => dout,
en => en,
we => we);
-- synthesis translate_on
END monrom_a;

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##############################################################
#
# Xilinx Core Generator version J.40
# Date: Mon Feb 25 18:49:53 2008
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fg320
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET active_clock_edge=Rising_Edge_Triggered
CSET additional_output_pipe_stages=0
CSET coefficient_file=C:\FPGA\mycom\mz-sp5030.coe
CSET component_name=monrom
CSET depth=36864
CSET disable_warning_messages=true
CSET enable_pin=true
CSET enable_pin_polarity=Active_High
CSET global_init_value=0
CSET handshaking_pins=false
CSET has_limit_data_pitch=false
CSET init_pin=false
CSET init_value=0
CSET initialization_pin_polarity=Active_High
CSET limit_data_pitch=18
CSET load_init_file=true
CSET port_configuration=Read_And_Write
CSET primitive_selection=Optimize_For_Area
CSET register_inputs=false
CSET select_primitive=16kx1
CSET width=8
CSET write_enable_polarity=Active_High
CSET write_mode=Read_After_Write
# END Parameters
GENERATE
# CRC: 71eb081a

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`timescale 1ns/1ns
module mycom_bench;
reg CLK_50MHZ;
reg BTN_NORTH,BTN_EAST,BTN_SOUTH,BTN_WEST;
reg [3:0] SW;
wire [7:0] LED;
wire VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC;
reg PS2_CLK, PS2_DATA;
wire TP1;
mycom mycom_1(CLK_50MHZ, BTN_NORTH,BTN_EAST,BTN_SOUTH,BTN_WEST,
VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC,
PS2_CLK, PS2_DATA,
SW, LED, TP1);
initial begin
CLK_50MHZ <= 0;
BTN_NORTH <= 1;
BTN_EAST <= 0;
BTN_SOUTH <= 0;
BTN_WEST <= 0;
PS2_CLK <= 0;
PS2_DATA <= 0;
SW <= 5;
#400000
$finish;
end
always #1 begin
CLK_50MHZ <= ~CLK_50MHZ;
end
endmodule

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/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file ram2.v when simulating
// the core, ram2. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module ram2(
addr,
clk,
din,
dout,
en,
we);
input [10 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input we;
// synthesis translate_off
BLKMEMSP_V6_2 #(
.c_addr_width(11),
.c_default_data("0"),
.c_depth(2048),
.c_enable_rlocs(0),
.c_has_default_data(1),
.c_has_din(1),
.c_has_en(1),
.c_has_limit_data_pitch(0),
.c_has_nd(0),
.c_has_rdy(0),
.c_has_rfd(0),
.c_has_sinit(0),
.c_has_we(1),
.c_limit_data_pitch(18),
.c_mem_init_file("mif_file_16_1"),
.c_pipe_stages(0),
.c_reg_inputs(0),
.c_sinit_value("0"),
.c_width(8),
.c_write_mode(0),
.c_ybottom_addr("0"),
.c_yclk_is_rising(1),
.c_yen_is_high(1),
.c_yhierarchy("hierarchy1"),
.c_ymake_bmm(0),
.c_yprimitive_type("16kx1"),
.c_ysinit_is_high(1),
.c_ytop_addr("1024"),
.c_yuse_single_primitive(0),
.c_ywe_is_high(1),
.c_yydisable_warnings(1))
inst (
.ADDR(addr),
.CLK(clk),
.DIN(din),
.DOUT(dout),
.EN(en),
.WE(we),
.ND(),
.RFD(),
.RDY(),
.SINIT());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of ram2 is "black_box"
endmodule

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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file ram2.vhd when simulating
-- the core, ram2. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY ram2 IS
port (
addr: IN std_logic_VECTOR(10 downto 0);
clk: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
dout: OUT std_logic_VECTOR(7 downto 0);
en: IN std_logic;
we: IN std_logic);
END ram2;
ARCHITECTURE ram2_a OF ram2 IS
-- synthesis translate_off
component wrapped_ram2
port (
addr: IN std_logic_VECTOR(10 downto 0);
clk: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
dout: OUT std_logic_VECTOR(7 downto 0);
en: IN std_logic;
we: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_ram2 use entity XilinxCoreLib.blkmemsp_v6_2(behavioral)
generic map(
c_sinit_value => "0",
c_has_en => 1,
c_reg_inputs => 0,
c_yclk_is_rising => 1,
c_ysinit_is_high => 1,
c_ywe_is_high => 1,
c_yprimitive_type => "16kx1",
c_ytop_addr => "1024",
c_yhierarchy => "hierarchy1",
c_has_limit_data_pitch => 0,
c_has_rdy => 0,
c_write_mode => 0,
c_width => 8,
c_yuse_single_primitive => 0,
c_has_nd => 0,
c_has_we => 1,
c_enable_rlocs => 0,
c_has_rfd => 0,
c_has_din => 1,
c_ybottom_addr => "0",
c_pipe_stages => 0,
c_yen_is_high => 1,
c_depth => 2048,
c_has_default_data => 1,
c_limit_data_pitch => 18,
c_has_sinit => 0,
c_yydisable_warnings => 1,
c_mem_init_file => "mif_file_16_1",
c_default_data => "0",
c_ymake_bmm => 0,
c_addr_width => 11);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_ram2
port map (
addr => addr,
clk => clk,
din => din,
dout => dout,
en => en,
we => we);
-- synthesis translate_on
END ram2_a;

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##############################################################
#
# Xilinx Core Generator version J.40
# Date: Sun Feb 24 16:19:11 2008
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fg320
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET active_clock_edge=Rising_Edge_Triggered
CSET additional_output_pipe_stages=0
CSET component_name=ram2
CSET depth=2048
CSET disable_warning_messages=true
CSET enable_pin=true
CSET enable_pin_polarity=Active_High
CSET global_init_value=0
CSET handshaking_pins=false
CSET has_limit_data_pitch=false
CSET init_pin=false
CSET init_value=0
CSET initialization_pin_polarity=Active_High
CSET limit_data_pitch=18
CSET load_init_file=false
CSET port_configuration=Read_And_Write
CSET primitive_selection=Optimize_For_Area
CSET register_inputs=false
CSET select_primitive=16kx1
CSET width=8
CSET write_enable_polarity=Active_High
CSET write_mode=Read_After_Write
# END Parameters
GENERATE
# CRC: 2b8d682f

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module rom(clk, addr, data);
input clk;
input [10:0] addr;
output [7:0] data;
reg [7:0] data;
always @(posedge clk) begin
case (addr)
11'h000: data = 8'h21;
11'h001: data = 8'h00;
11'h002: data = 8'hd0;
11'h003: data = 8'h3e;
11'h004: data = 8'h00;
11'h005: data = 8'h77;
11'h006: data = 8'h23;
11'h007: data = 8'h3c;
11'h008: data = 8'h18;
11'h009: data = 8'hfb;
default: data = 8'hXX;
endcase
end
endmodule

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/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file rom_2k.v when simulating
// the core, rom_2k. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module rom_2k(
addr,
clk,
dout,
en);
input [10 : 0] addr;
input clk;
output [7 : 0] dout;
input en;
// synthesis translate_off
BLKMEMSP_V6_2 #(
.c_addr_width(11),
.c_default_data("0"),
.c_depth(2048),
.c_enable_rlocs(0),
.c_has_default_data(0),
.c_has_din(0),
.c_has_en(1),
.c_has_limit_data_pitch(0),
.c_has_nd(0),
.c_has_rdy(0),
.c_has_rfd(0),
.c_has_sinit(0),
.c_has_we(0),
.c_limit_data_pitch(18),
.c_mem_init_file("rom_2k.mif"),
.c_pipe_stages(0),
.c_reg_inputs(0),
.c_sinit_value("0"),
.c_width(8),
.c_write_mode(0),
.c_ybottom_addr("0"),
.c_yclk_is_rising(1),
.c_yen_is_high(1),
.c_yhierarchy("hierarchy1"),
.c_ymake_bmm(0),
.c_yprimitive_type("16kx1"),
.c_ysinit_is_high(1),
.c_ytop_addr("1024"),
.c_yuse_single_primitive(0),
.c_ywe_is_high(1),
.c_yydisable_warnings(1))
inst (
.ADDR(addr),
.CLK(clk),
.DOUT(dout),
.EN(en),
.DIN(),
.ND(),
.RFD(),
.RDY(),
.SINIT(),
.WE());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of rom_2k is "black_box"
endmodule

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--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file rom_2k.vhd when simulating
-- the core, rom_2k. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY rom_2k IS
port (
addr: IN std_logic_VECTOR(10 downto 0);
clk: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
en: IN std_logic);
END rom_2k;
ARCHITECTURE rom_2k_a OF rom_2k IS
-- synthesis translate_off
component wrapped_rom_2k
port (
addr: IN std_logic_VECTOR(10 downto 0);
clk: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
en: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_rom_2k use entity XilinxCoreLib.blkmemsp_v6_2(behavioral)
generic map(
c_sinit_value => "0",
c_has_en => 1,
c_reg_inputs => 0,
c_yclk_is_rising => 1,
c_ysinit_is_high => 1,
c_ywe_is_high => 1,
c_yprimitive_type => "16kx1",
c_ytop_addr => "1024",
c_yhierarchy => "hierarchy1",
c_has_limit_data_pitch => 0,
c_has_rdy => 0,
c_write_mode => 0,
c_width => 8,
c_yuse_single_primitive => 0,
c_has_nd => 0,
c_has_we => 0,
c_enable_rlocs => 0,
c_has_rfd => 0,
c_has_din => 0,
c_ybottom_addr => "0",
c_pipe_stages => 0,
c_yen_is_high => 1,
c_depth => 2048,
c_has_default_data => 0,
c_limit_data_pitch => 18,
c_has_sinit => 0,
c_mem_init_file => "rom_2k.mif",
c_yydisable_warnings => 1,
c_default_data => "0",
c_ymake_bmm => 0,
c_addr_width => 11);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rom_2k
port map (
addr => addr,
clk => clk,
dout => dout,
en => en);
-- synthesis translate_on
END rom_2k_a;

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##############################################################
#
# Xilinx Core Generator version J.40
# Date: Fri Feb 22 02:27:21 2008
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fg320
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET active_clock_edge=Rising_Edge_Triggered
CSET additional_output_pipe_stages=0
CSET coefficient_file=C:\FPGA\mycom\cg_rom.coe
CSET component_name=rom_2k
CSET depth=2048
CSET disable_warning_messages=true
CSET enable_pin=true
CSET enable_pin_polarity=Active_High
CSET global_init_value=0
CSET handshaking_pins=false
CSET has_limit_data_pitch=false
CSET init_pin=false
CSET init_value=0
CSET initialization_pin_polarity=Active_High
CSET limit_data_pitch=18
CSET load_init_file=true
CSET port_configuration=Read_Only
CSET primitive_selection=Optimize_For_Area
CSET register_inputs=false
CSET select_primitive=16kx1
CSET width=8
CSET write_enable_polarity=Active_High
CSET write_mode=Read_After_Write
# END Parameters
GENERATE
# CRC: e5516405

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#####################################################
### SPARTAN-3E STARTER KIT BOARD CONSTRAINTS FILE
#####################################################
# ==== Analog-to-Digital Converter (ADC) ====
# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
# ==== Programmable Gain Amplifier (AMP) ====
# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
# ==== Pushbuttons (BTN) ====
NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
# ==== Clock inputs (CLK) ====
NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
#NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
# ==== Digital-to-Analog Converter (DAC) ====
# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
# ==== 1-Wire Secure EEPROM (DS)
NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
# ==== Ethernet PHY (E) ====
NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33 ;
NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33 ;
NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ;
NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<4>" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 ;
NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<4>" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
# ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ====
NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
NET "FPGA_HSWAP" LOC = "B3" | IOSTANDARD = LVCMOS33 ;
# ==== FX2 Connector (FX2) ====
NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ;
NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# These four connections are shared with the J1 6-pin accessory header
NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# These four connections are shared with the J2 6-pin accessory header
NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# These four connections are shared with the J4 6-pin accessory header
NET "TP1" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# The discrete LEDs are shared with the following 8 FX2 connections
#NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IP<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IP<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IP<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IP<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# ==== 6-pin header J1 ====
# These are shared connections with the FX2 connector
#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
# ==== 6-pin header J2 ====
# These are shared connections with the FX2 connector
#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
# ==== 6-pin header J4 ====
# These are shared connections with the FX2 connector
#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
# ==== Character LCD (LCD) ====
NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
# LCD data connections are shared with StrataFlash connections SF_D<11:8>
#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
# ==== Discrete LEDs (LED) ====
# These are shared connections with the FX2 connector
NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
# ==== PS/2 Mouse/Keyboard Port (PS2) ====
NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
# ==== Rotary Pushbutton Switch (ROT) ====
NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;
NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
# ==== RS-232 Serial Ports (RS232) ====
NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ;
NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
# ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)
NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ;
NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ;
NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ;
NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ;
NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ;
NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ;
NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ;
NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ;
NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ;
NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ;
NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ;
NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ;
NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ;
NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I ;
NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ;
NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I ;
NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ;
NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ;
NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I ;
NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I ;
# Path to allow connection to top DCM connection
NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
# Prohibit VREF pins
CONFIG PROHIBIT = D2;
CONFIG PROHIBIT = G4;
CONFIG PROHIBIT = J6;
CONFIG PROHIBIT = L5;
CONFIG PROHIBIT = R4;
# ==== Intel StrataFlash Parallel NOR Flash (SF) ====
NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ;
NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
# ==== STMicro SPI serial Flash (SPI) ====
# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
# ==== Slide Switches (SW) ====
NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
# ==== VGA Port (VGA) ====
NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
# ==== Xilinx CPLD (XC) ====
NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL ;
NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ;
NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;

4
Sharp - MZ-80K_MiST/rtl/pll.qip
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@@ -1,4 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

348
Sharp - MZ-80K_MiST/rtl/pll.v Normal file
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@@ -0,0 +1,348 @@
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 27,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 50,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 54,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 25,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "54"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.500000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "50"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.50000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "54"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

350
Sharp - MZ-80K_MiST/rtl/pll.vhd
View File

@@ -1,350 +0,0 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 27,
clk0_duty_cycle => 50,
clk0_multiply_by => 50,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "50"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

4
Sharp - MZ-80K_MiST/rtl/ps2.v
View File

@@ -61,7 +61,7 @@ module ps2(clk, reset,
end
//
// PS/2<EFBFBD><EFBFBD><EFBFBD>͏<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
// PS/2“ü—͏ˆ—ŽÀ‘•
//
wire dten;
wire [7:0] kdata;
@@ -215,7 +215,7 @@ module ps2(clk, reset,
8'h4A: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // ?
8'h51: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // _
8'h11: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // GRPH
8'h13: begin key_tbl6[5] <= key_f0; key_f0 <= 1'b0; end // <EFBFBD>J<EFBFBD>i
8'h13: begin key_tbl6[5] <= key_f0; key_f0 <= 1'b0; end // ƒJƒi
8'h12: begin key_tbl8[0] <= ( key_f0 | key_e0 ) & (key_tbl8[0] | ~key_e0 ); key_f0 <= 1'b0; key_e0 <= 1'b0; end // SHIFT
8'h59: begin key_tbl8[5] <= ( key_f0 | key_e0 ) & (key_tbl8[5] | ~key_e0 ); key_f0 <= 1'b0; key_e0 <= 1'b0; end // SHIFT
8'h14: begin key_tble[0] <= key_f0; key_f0 <= 1'b0; end // CTRL

116
Sharp - MZ-80K_MiST/rtl/ps2_recieve.v Normal file
View File

@@ -0,0 +1,116 @@
module ps2_recieve(
input clk,
input reset,
input ps2_clk,
input ps2_data,
output dten,
output [7:0] kdata);
reg [10:0] key_data;
reg [3:0] clk_data;
always @(posedge clk or posedge reset) begin
if( reset ) begin
key_data <= 11'b11111111111;
dten <= 1'b0;
end else begin
clk_data <= {clk_data[2:0], ps2_clk};
if ( clk_data == 4'b0011 )
key_data <= {ps2_data, key_data[10:1]};
if ( !key_data[0] & key_data[10] ) begin
dten <= 1'b1;
kdata <= key_data[8:1];
key_data <= 11'b11111111111;
end else
dten <= 1'b0;
end
end
endmodule
module keyboard (
input clock,
input ps2_data,
input ps2_clk,
output reg [7:0] led_g
);
parameter idle = 2'b01;
parameter receive = 2'b10;
parameter ready = 2'b11;
reg [1:0] state=idle;
reg [15:0] rxtimeout=16'b0000000000000000;
reg [10:0] rxregister=11'b11111111111;
reg [1:0] datasr=2'b11;
reg [1:0] clksr=2'b11;
reg [7:0] rxdata;
reg datafetched;
reg rxactive;
reg dataready;
always @(posedge clock )
begin
if(datafetched==1)
led_g <=rxdata;
end
always @(posedge clock )
begin
rxtimeout<=rxtimeout+1;
datasr <= {datasr[0],ps2_data};
clksr <= {clksr[0],ps2_clk};
if(clksr==2'b10)
rxregister<= {datasr[1],rxregister[10:1]};
case (state)
idle:
begin
rxregister <=11'b11111111111;
rxactive <=0;
dataready <=0;
rxtimeout <=16'b0000000000000000;
if(datasr[1]==0 && clksr[1]==1)
begin
state<=receive;
rxactive<=1;
end
end
receive:
begin
if(rxtimeout==50000)
state<=idle;
else if(rxregister[0]==0)
begin
dataready<=1;
rxdata<=rxregister[8:1];
state<=ready;
datafetched<=1;
end
end
ready:
begin
if(datafetched==1)
begin
state <=idle;
dataready <=0;
rxactive <=0;
end
end
endcase
end
endmodule

93
Sharp - MZ-80K_MiST/rtl/ps2n.sv Normal file
View File

@@ -0,0 +1,93 @@
module ps2n(
input clk,
input reset,
input ps2_clk,
input ps2_data,
input cs,
input rd,
input [7:0] addr,
output [7:0] data);
reg [7:0]key_tbl0 = 8'b11111111,
key_tbl1 = 8'b11111111,
key_tbl2 = 8'b11111111,
key_tbl3 = 8'b11111111,
key_tbl4 = 8'b11111111,
key_tbl5 = 8'b11111111,
key_tbl6 = 8'b11111111,
key_tbl7 = 8'b11111111,
key_tbl8 = 8'b11111111,
key_tbl9 = 8'b11111111,
key_tbla = 8'b11111111,
key_tblb = 8'b11111111,
key_tblc = 8'b11111111,
key_tbld = 8'b11111111,
key_tble = 8'b11111111;
always @(posedge clk ) begin
if ( cs & rd ) begin
begin
case (addr[3:0])
4'h0: data <= key_tbl0;
4'h1: data <= key_tbl1;
4'h2: data <= key_tbl2;
4'h3: data <= key_tbl3;
4'h4: data <= key_tbl4;
4'h5: data <= key_tbl5;
4'h6: data <= key_tbl6;
4'h7: data <= key_tbl7;
4'h8: data <= key_tbl8;
4'h9: data <= key_tbl9;
4'ha: data <= key_tbla;
4'hb: data <= key_tblb;
4'hc: data <= key_tblc;
4'hd: data <= key_tbld;
4'he: data <= key_tble;
default: data <= 8'hzz;
endcase
end
end
end
always @(posedge clk ) begin
key_tbl0 <= 8'b11111111;
key_tbl1 <= 8'b11111111;
key_tbl2 <= 8'b11111111;
key_tbl3 <= 8'b11111111;
key_tbl4 <= 8'b11111111;
key_tbl5 <= 8'b11111111;
key_tbl6 <= 8'b11111111;
key_tbl7 <= 8'b11111111;
key_tbl8 <= 8'b11111111;
key_tbl9 <= 8'b11111111;
case ( kdata )
8'h1C: begin key_tbl4[0] = 1'b0; end//A
8'h32: begin key_tbl6[2] = 1'b0; end//B
default: begin end
endcase
end
wire dten;
wire [7:0] kdata;
ps2_recieve ps2_recieve1(
.clk(clk),
.reset(reset),
.ps2_clk(ps2_clk),
.ps2_data(ps2_data),
.dten(dten),
.kdata(kdata)
);
endmodule

59
Sharp - MZ-80K_MiST/rtl/vram.v → Sharp - MZ-80K_MiST/rtl/ram2.v
View File

@@ -4,7 +4,7 @@
// MODULE: altsyncram
// ============================================================
// File Name: vram.v
// File Name: ram2.v
// Megafunction Name(s):
// altsyncram
//
@@ -14,11 +14,11 @@
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
@@ -36,15 +36,17 @@
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module vram (
module ram2 (
address,
clken,
clock,
data,
rden,
wren,
q);
input [11:0] address;
input [10:0] address;
input clken;
input clock;
input [7:0] data;
input rden;
@@ -53,6 +55,7 @@ module vram (
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
@@ -67,6 +70,7 @@ module vram (
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.clocken0 (clken),
.rden_a (rden),
.q_a (sub_wire0),
.aclr0 (1'b0),
@@ -77,7 +81,6 @@ module vram (
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
@@ -87,18 +90,18 @@ module vram (
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "NORMAL",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
@@ -116,9 +119,9 @@ endmodule
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
@@ -128,7 +131,7 @@ endmodule
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
@@ -138,40 +141,42 @@ endmodule
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL vram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL vram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vram_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram2_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

BIN
Sharp - MZ-80K_MiST/rtl/rom/80ktc.rom
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Sharp - MZ-80K_MiST/rtl/roms/80ktc.zip Normal file
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0
Sharp - MZ-80K_MiST/rtl/rom/80KCG.ROM → Sharp - MZ-80K_MiST/rtl/roms/CG.ROM
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BIN
Sharp - MZ-80K_MiST/rtl/roms/MZ80K2E Jap CG Normal file
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Sharp - MZ-80K_MiST/rtl/roms/MZ80K2E Jap CG.zip Normal file
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Sharp - MZ-80K_MiST/rtl/roms/MZ80K2E ROM Normal file
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Sharp - MZ-80K_MiST/rtl/roms/MZ80K2E ROM.zip Normal file
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257
Sharp - MZ-80K_MiST/rtl/roms/Mon.hex Normal file
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@@ -0,0 +1,257 @@
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0
Sharp - MZ-80K_MiST/rtl/80KCG.hex → Sharp - MZ-80K_MiST/rtl/roms/cg.hex
View File

66
Sharp - MZ-80K_MiST/rtl/roms/cg_jp.HEX Normal file
View File

@@ -0,0 +1,66 @@
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32
Sharp - MZ-80K_MiST/rtl/roms/cgrom.v Normal file
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:56:03 02/22/2008
// Design Name:
// Module Name: cgrom
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cgrom( addr, dout, en);
input [10:0] addr;
output [7:0] dout;
input en;
reg [7:0] mem [0:2047];
assign dout = en ? mem[addr] : 8'hzz;
initial $readmemh( "roms/cg_jp_hex.hex", mem );
endmodule

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256
Sharp - MZ-80K_MiST/rtl/roms/mon_rom_jp.hex.hex Normal file
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@@ -0,0 +1,256 @@
C3 4A 00 C3 E6 07 C3 0E 09 C3 18 09 C3 20 09 C3
26 09 C3 35 09 C3 81 09 C3 99 09 C3 BD 08 C3 32
0A C3 36 04 C3 75 04 C3 D8 04 C3 F8 04 C3 88 05
C3 C7 01 C3 08 03 00 00 C3 38 10 C3 58 03 C3 E5
02 C3 FA 02 C3 AB 02 C3 BE 02 31 F0 10 ED 56 CD
C9 0F 3E 16 CD 12 00 06 3C 21 70 11 CD D8 0F 21
92 03 3E C3 32 38 10 22 39 10 3E 04 32 9E 11 3C
32 9F 11 CD BE 02 CD 09 00 11 41 01 CD 15 00 C3
6B 01 CD 09 00 3E 2A CD 12 00 11 A3 11 CD 03 00
1A FE 1B CA 82 00 FE 2A 20 01 13 21 96 01 06 04
CD 80 01 CA CF 00 21 9A 01 CD 80 01 CA 59 01 21
9E 01 06 02 CD 80 01 CA 6B 01 21 A0 01 CD 80 01
CA 73 01 21 A2 01 CD 80 01 CA 77 01 C3 82 00 13
13 13 13 1A FE 0D C2 04 01 CD D8 04 DA A4 01 CD
09 00 11 38 01 CD 15 00 11 F1 10 21 10 00 19 36
0D CD 15 00 CD F8 04 DA A4 01 2A 06 11 7C FE 12
DA 82 00 E9 D5 CD D8 04 DA A4 01 CD 09 00 11 31
01 CD 15 00 11 F1 10 21 10 00 19 36 0D CD 15 00
D1 D5 21 F1 10 06 10 CD 80 01 C2 05 01 D1 C3 DF
00 46 4F 55 4E 44 20 0D 4C 4F 41 44 49 4E 47 20
0D 2A 2A 20 20 4D 4F 4E 49 54 4F 52 20 53 50 2D
31 30 30 32 20 20 2A 2A 0D 13 13 13 13 1A FE 24
C2 82 00 13 CD 10 04 DA 82 00 E9 3E FF 32 9D 11
C3 82 00 AF C3 6D 01 21 00 F0 7E B7 C2 82 00 E9
C5 D5 E5 1A BE 20 0B 05 28 08 FE 0D 28 04 13 23
18 F1 E1 D1 C1 C9 4C 4F 41 44 47 4F 54 4F 53 53
53 47 46 44 FE 02 CA 82 00 CD 09 00 11 B5 01 CD
15 00 C3 82 00 22 43 48 45 43 4B 20 53 55 4D 20
45 52 52 4F 52 22 0D C5 D5 E5 3E 02 32 A0 11 06
01 1A FE 0D 28 02 FE C8 CA 10 02 FE CF CA 03 02
FE D7 CA 0C 02 FE 23 21 71 02 20 04 21 89 02 13
CD 1C 02 DA D1 01 CD C8 02 DA 13 02 CD AB 02 41
C3 D1 01 3E 03 32 A0 11 13 C3 D1 01 3E 01 18 F5
CD C8 02 F5 CD BE 02 F1 E1 D1 C1 C9 C5 06 08 1A
BE 28 09 23 23 23 10 F8 37 13 C1 C9 23 D5 5E 23
56 EB 7C B7 28 09 3A A0 11 3D 28 03 29 18 FA 22
A1 11 3E 02 32 A0 11 D1 13 1A 47 E6 F0 FE 30 28
05 3A 9F 11 18 07 13 78 E6 0F 32 9F 11 4F 06 00
21 A1 02 09 4E 3A 9E 11 47 AF 81 10 FD C1 4F AF
C9 43 77 07 44 A7 06 45 ED 05 46 98 05 47 FC 04
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98 05 46 48 05 47 B4 04 41 31 04 42 BB 03 52 00
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28 0C D5 EB 21 04 E0 73 72 3E 01 D1 18 06 3E 34
32 07 E0 AF 32 08 E0 C9 21 00 E0 36 F9 23 7E E6
08 20 02 37 C9 3A 08 E0 0F 38 FA 3A 08 E0 0F 30
FA 10 F2 AF C9 C5 E5 21 71 04 CD AE 02 06 32 AF
CD 5B 07 10 FA E1 C1 C3 BE 02 F5 C5 E6 0F 47 3E
08 90 32 9E 11 C1 F1 C9 F3 C5 D5 E5 32 9B 11 3E
F0 32 9C 11 21 C0 A8 AF ED 52 E5 23 EB 3E 74 32
07 E0 3E B0 32 07 E0 21 06 E0 73 72 2B 36 0A 36
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2B 00 00 00 36 12 36 7A 23 D1 4E 7E BA 20 FB 79
BB 20 F7 E1 D1 C1 FB C9 E5 3E 80 32 07 E0 21 06
E0 F3 5E 56 FB 7B B2 CA 79 03 AF 21 C0 A8 ED 52
DA 83 03 EB 3A 9B 11 E1 C9 11 C0 A8 3A 9B 11 EE
01 E1 C9 F3 21 06 E0 7E 2F 5F 7E 2F 57 FB 13 C3
7C 03 F5 C5 D5 E5 3A 9B 11 EE 01 32 9B 11 3E 80
32 07 E0 21 06 E0 5E 56 21 C0 A8 19 2B 2B EB 21
06 E0 73 72 E1 D1 C1 F1 FB C9 7C CD C3 03 7D CD
C3 03 C9 F5 E6 F0 0F 0F 0F 0F CD DA 03 CD 12 00
F1 E6 0F CD DA 03 CD 12 00 C9 D5 E5 21 E9 03 E6
0F 5F 16 00 19 7E E1 D1 C9 30 31 32 33 34 35 36
37 38 39 41 42 43 44 45 46 C5 E5 01 00 10 21 E9
03 BE 20 03 79 18 06 23 0C 05 20 F5 37 E1 C1 C9
D5 CD 1F 04 38 07 67 CD 1F 04 38 01 6F D1 C9 C5
1A 13 CD F9 03 38 0D 07 07 07 07 4F 1A 13 CD F9
03 38 01 B1 C1 C9 F3 D5 C5 E5 16 D7 1E CC 21 F0
10 01 80 00 CD 33 07 CD B2 06 DA 63 05 7B FE CC
20 11 CD 09 00 D5 11 6C 04 CD 15 00 11 F1 10 CD
15 00 D1 CD B8 07 CD 8D 04 C3 63 05 57 52 49 54
49 4E 47 20 0D F3 D5 C5 E5 16 D7 1E 53 2A 02 11
E5 C1 2A 04 11 78 B1 CA D4 04 C3 44 04 D5 C5 E5
16 02 3E F9 32 00 E0 7E CD A5 07 3A 01 E0 E6 08
C2 A7 04 37 C3 D4 04 23 0B 78 B1 C2 97 04 2A 97
11 7C CD A5 07 7D CD A5 07 CD 80 07 15 C2 C4 04
B7 C3 D4 04 06 00 CD 67 07 05 C2 C6 04 E1 C1 C5
E5 C3 97 04 E1 C1 D1 C9 F3 D5 C5 E5 16 D2 1E CC
01 80 00 21 F0 10 CD B2 06 DA 82 05 CD 5E 06 DA
82 05 CD 10 05 C3 63 05 F3 D5 C5 E5 16 D2 1E 53
2A 02 11 E5 C1 2A 04 11 78 B1 CA 63 05 C3 E6 04
D5 C5 E5 26 02 01 01 E0 11 02 E0 CD 01 06 DA 82
05 CD 60 07 CD 60 07 CD 60 07 1A E6 20 CA 1B 05
54 21 00 00 22 97 11 E1 C1 C5 E5 CD 24 06 DA 82
05 77 23 0B 78 B1 C2 3B 05 2A 97 11 CD 24 06 DA
82 05 5F CD 24 06 DA 82 05 BD C2 74 05 7B BC C2
74 05 AF E1 C1 D1 CD 00 07 F5 3A 9C 11 FE F0 20
01 FB F1 C9 15 CA 7C 05 62 C3 15 05 3E 01 37 C3
63 05 3E 02 37 C3 63 05 F3 D5 C5 E5 2A 02 11 E5
C1 2A 04 11 16 D2 1E 53 78 B1 CA 63 05 CD 33 07
CD B2 06 DA 82 05 CD 5E 06 DA 82 05 CD B2 05 C3
63 05 D5 C5 E5 26 02 01 01 E0 11 02 E0 CD 01 06
DA 82 05 CD 60 07 CD 60 07 CD 60 07 1A E6 20 CA
BD 05 54 E1 C1 C5 E5 CD 24 06 DA 82 05 BE C2 7C
05 23 0B 78 B1 C2 D7 05 2A 99 11 CD 24 06 BC C2
7C 05 CD 24 06 BD C2 7C 05 15 CA 62 05 62 C3 B7
05 3E F9 32 00 E0 00 0A E6 08 C2 0F 06 37 C9 1A
E6 20 C2 07 06 0A E6 08 C2 1D 06 37 C9 1A E6 20
CA 15 06 C9 C5 D5 E5 21 00 08 01 01 E0 11 02 E0
CD 01 06 DA 5A 06 CD 60 07 CD 60 07 CD 60 07 1A
E6 20 CA 4F 06 E5 2A 97 11 23 22 97 11 E1 37 7D
17 6F 25 C2 30 06 CD 01 06 7D E1 D1 C1 C9 C5 D5
E5 21 28 28 7B FE CC CA 6D 06 21 14 14 22 95 11
01 01 E0 11 02 E0 2A 95 11 CD 01 06 DA AE 06 CD
60 07 CD 60 07 CD 60 07 1A E6 20 CA 76 06 25 C2
79 06 CD 01 06 DA AE 06 CD 60 07 CD 60 07 CD 60
07 1A E6 20 C2 76 06 2D C2 92 06 CD 01 06 E1 D1
C1 C9 C5 D5 E5 0E 0A 3A 02 E0 E6 10 CA C4 06 AF
E1 D1 C1 C9 3E 06 32 03 E0 3E 07 32 03 E0 0D C2
B7 06 CD 09 00 7A FE D7 28 08 11 22 07 CD 18 00
18 0C 11 29 07 CD 18 00 11 24 07 CD 18 00 3A 02
E0 E6 10 C2 BF 06 CD 44 0A C2 EE 06 37 C3 C0 06
F5 C5 D5 06 0A 3A 02 E0 E6 10 20 04 D1 C1 F1 C9
3E 06 32 03 E0 3E 07 32 03 E0 05 C2 05 07 D1 C1
F1 C9 7F 20 50 4C 41 59 0D 7F 20 52 45 43 4F 52
44 2E 0D C5 D5 E5 11 00 00 78 B1 20 0B EB 22 97
11 22 99 11 E1 D1 C1 C9 7E E5 26 08 07 30 01 13
25 20 F9 E1 23 0B C3 39 07 3E 0E 3D C2 5B 07 C9
3E 0D 3D C2 62 07 C9 F5 3E 03 32 03 E0 CD 59 07
CD 59 07 3E 02 32 03 E0 CD 59 07 CD 59 07 F1 C9
F5 3E 03 32 03 E0 CD 59 07 CD 59 07 CD 59 07 CD
59 07 3E 02 32 03 E0 CD 59 07 CD 59 07 CD 59 07
CD 60 07 F1 C9 C5 06 08 CD 80 07 07 DC 80 07 D4
67 07 05 C2 AB 07 C1 C9 C5 D5 7B 01 F0 55 11 28
28 FE CC CA CC 07 01 F8 2A 11 14 14 CD 67 07 0B
78 B1 20 F8 CD 80 07 15 20 FA CD 67 07 1D 20 FA
CD 80 07 D1 C1 C9 F5 C5 E5 D5 AF 32 93 11 CD B3
09 47 3A 9D 11 B7 CC E5 02 78 E6 F0 FE C0 C2 A6
08 78 FE CD CA 5B 08 FE C9 CA 2B 08 FE CA CA 2B
08 FE CB CA B3 08 FE C8 CA 38 08 FE C7 CA 2B 08
3A 93 11 B7 FA 42 08 C2 31 08 78 CD DC 0D C3 EE
07 3D 32 93 11 C3 42 08 3A 93 11 3C 32 93 11 C3
2A 08 78 CD A6 0D CD B5 0D FE 62 C2 EE 07 3A 93
11 E6 80 EE 80 32 93 11 C3 EE 07 2A 71 11 5C 16
00 21 73 11 19 EB 1A B7 01 28 00 2A 71 11 C2 7A
08 13 1A B7 CA 7D 08 C3 7B 08 25 0E 50 2E 00 CD
B4 0F D1 D5 C5 CD A6 0D ED B0 C1 E1 E5 41 7E CD
CE 0B 77 23 10 F8 36 0D 2B 7E FE 20 28 F8 CD 06
00 D1 E1 C1 F1 C9 3A 93 11 B7 FA 42 08 CA 42 08
C3 31 08 E1 E5 36 1B 23 36 0D C3 9E 08 CD CA 08
FE F0 20 02 AF C9 CD CE 0B C9 C5 D5 E5 CD 50 0A
78 07 38 06 3E F0 E1 D1 C1 C9 07 D2 EC 08 06 00
21 08 00 09 11 C9 0A 19 7E C3 D6 08 3A 70 11 B7
C2 FD 08 06 00 21 C9 0A 09 7E C3 D6 08 79 E6 F0
0F 47 79 E6 0F 80 C6 A0 6F 26 00 C3 E4 08 AF 32
94 11 3E CD CD DC 0D C9 3A 94 11 B7 C8 C3 06 00
3E 20 CD 35 09 C9 CD 0C 00 3A 94 11 B7 C8 D6 0A
38 F4 20 FA C9 FE 0D CA 0E 09 C5 4F 47 CD A6 0D
CD 46 09 78 C1 C9 79 CD B9 0B 4F E6 F0 FE F0 C8
FE C0 79 C2 70 09 FE C7 D2 70 09 CD DC 0D FE C3
CA 73 09 FE C5 CA 6B 09 FE C6 C0 AF 32 94 11 C9
CD B5 0D 3A 94 11 3C FE 50 38 02 D6 50 32 94 11
C9 F5 C5 D5 06 05 CD A6 0D 1A FE 0D CA DF 0F 4F
CD 46 09 13 10 F3 C3 84 09 F5 C5 D5 06 05 CD A6
0D 1A FE 0D CA DF 0F CD B9 0B CD 70 09 13 10 F1
C3 9C 09 C5 D5 E5 CD B1 0F CD A6 0D 7E 32 8E 11
22 8F 11 21 92 11 36 EF AF 32 00 E0 32 91 11 2F
32 00 E0 16 14 CD FF 09 CD 50 0A 78 07 DA D3 09
15 C2 D5 09 CD FF 09 CD CA 08 FE F0 CA E4 09 F5
CD A6 0D 3A 8E 11 2A 8F 11 77 F1 E1 D1 C1 C9 F5
E5 3A 02 E0 07 07 DA 25 0A 3A 91 11 0F DA 22 0A
3A 92 11 2A 8F 11 CD A6 0D 77 3A 91 11 EE 01 32
91 11 E1 F1 C9 3A 91 11 0F D2 22 0A 3A 8E 11 C3
13 0A 3E F8 32 00 E0 00 3A 01 E0 2F E6 21 C2 44
0A C6 01 C9 3E F9 32 00 E0 00 3A 01 E0 E6 08 C9
D5 E5 06 FA 16 00 05 78 32 00 E0 FE EF C2 64 0A
42 D1 E1 C9 FE F8 CA B2 0A 3A 01 E0 2F B7 CA 56
0A 5F 7A F6 80 57 21 AD 0A 78 E6 0F 07 07 07 07
4F 7B 07 30 03 3E 07 E9 07 30 03 3E 06 E9 07 30
03 3E 05 E9 07 30 03 3E 04 E9 07 30 03 3E 03 E9
07 30 03 3E 02 E9 07 30 03 3E 01 E9 AF 81 4F C3
56 0A 3A 01 E0 2F 5F E6 21 CA C0 0A 7A F6 40 57
7B E6 DE CA 56 0A C3 71 0A 21 23 25 27 29 2A 1D
1F 61 63 65 67 69 6A 5D 5F 22 24 26 28 20 1C 1E
D1 62 64 66 68 60 5C 5E D0 11 05 14 15 0F 2B 31
33 51 45 54 55 4F 6B 71 73 17 12 19 09 10 30 32
D3 57 52 59 49 50 70 72 D2 01 04 07 0A 0C 1B 35
37 41 44 47 4A 4C 5B 75 77 13 06 08 0B 2C 34 36
D5 53 46 48 4B 6C 74 76 D4 1A 03 02 0D 2E C9 39
3B 5A 43 42 4D 6E CA 79 7B 18 16 0E 2F 2D 38 3A
D7 58 56 4E 6F 6D 78 7A D6 F0 C7 F0 C3 CD F0 3D
3F F0 C8 F0 C4 CD F0 7D 7F C5 00 C1 F0 F0 3C 3E
DC C6 00 C2 CB F0 7C 7E D8 A1 A3 A5 A7 A9 AA 9D
9F A2 A4 A6 A8 A0 9C 9E DD 91 85 94 95 8F AB B1
B3 97 92 99 89 90 B0 B2 DE 81 84 87 8A 8C 9B B5
B7 93 86 88 8B AC B4 B6 D9 9A 83 82 8D AE C9 B9
BB 98 96 8E AF AD B8 BA DA F0 C7 F0 C3 CD F0 BD
BF C5 00 C1 F0 F0 BC BE DB D6 10 D2 C1 0B 3E F0
C9 C5 E5 21 D6 0B 4F 06 00 09 7E E1 C1 C9 C5 E5
21 C6 0C C3 C6 0B F0 C1 C2 C3 C4 C5 C6 F0 F0 F0
F0 F0 F0 F0 F0 F0 00 61 62 63 64 65 66 67 68 69
6B 6A 2F 2A 2E 2D 20 21 22 23 24 25 26 27 28 29
4F 2C 51 2B 57 49 55 01 02 03 04 05 06 07 08 09
0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19
1A 52 59 54 50 45 C7 C8 C9 CA CB CC CD CE CF DF
E7 E8 E9 EA EC ED D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
DA DB DC DD DE C0 00 BD 9D B1 B5 B9 B4 9E B2 B6
BA BE 9F B3 B7 BB BF A3 85 A4 A5 A6 94 87 88 9C
82 98 84 92 90 83 91 81 9A 97 93 95 89 A1 AF 8B
86 96 A2 AB AA 8A 8E B0 AD 8D A7 A8 A9 8F 8C AE
AC 9B A0 99 BC B8 00 3B 3A 70 3C 71 5A 3D 43 56
3F 1E 4A 1C 5D 3E 5C 1F 5F 5E 37 7B 7F 36 7A 7E
33 4B 4C 1D 6C 5B 78 41 35 34 74 30 38 75 39 4D
6F 6E 32 77 76 72 73 47 7C 53 31 4E 6D 48 46 7D
44 1B 58 79 42 60 20 41 42 43 44 45 46 47 48 49
4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59
5A FB CD DD CB D1 30 31 32 33 34 35 36 37 38 39
2D 3D 3B 2F 2E 2C E5 F4 EC DA E3 E2 D7 D4 E6 E8
C2 C1 C4 C7 CF CA 20 E1 FE C8 FA 5F F8 F1 F7 3F
CC DB DC E9 F5 3A 5E 3C 5B F3 5D 40 C9 3E FC 5C
C6 DF D0 CE D3 D2 FF 21 22 23 24 25 26 27 28 29
2B 2A DE F6 EB EA C3 C5 EF F0 E4 E7 EE ED E0 FD
D8 D5 F2 F9 D9 D6 20 A1 9A 9F 9C 92 AA 97 98 A6
AF A9 B8 B3 B0 B7 9E A0 9D A4 96 A5 AB A3 9B BD
A2 BB 99 82 87 8C BC A7 AC 91 93 94 95 B4 B5 B6
AE AD BA B2 B9 A8 B1 83 88 8D 86 84 89 8E BF 85
8A 8F BE 81 8B 90 7F 11 12 13 14 15 16 60 61 62
63 64 65 66 67 68 70 71 72 73 74 75 76 77 78 79
7A 7B 7C 7D 7E 69 F5 3A 02 E0 07 30 FA 3A 02 E0
07 38 FA F1 C9 F5 C5 D5 E5 47 CD B1 0F 70 2A 71
11 7D FE 27 C2 90 0E 5C 16 00 21 73 11 19 7E B7
C2 90 0E 23 36 01 23 36 00 C3 90 0E F5 C5 D5 E5
47 E6 F0 FE C0 C2 DE 0F A8 07 07 4F 06 00 21 F3
0D 09 E9 C3 32 0E 00 C3 74 0E 00 C3 84 0E 00 C3
90 0E 00 C3 AE 0E 00 C3 BF 0E 00 C3 C5 0E 00 C3
F8 0E 00 C3 49 0F 00 C3 E1 0E 00 C3 EE 0E 00 C3
DE 0F 00 C3 DE 0F 00 C3 8B 0F 00 C3 DE 0F 00 C3
DE 0F CD A6 0D AF 32 03 E0 01 C0 03 11 00 D0 21
28 D0 ED B0 EB 06 28 CD D8 0F 01 1A 00 11 73 11
21 73 11 23 ED B0 36 00 3A 73 11 B7 C2 6A 0E CD
A6 0D 3E 01 32 03 E0 C3 DE 0F 2A 71 11 25 22 71
11 C3 39 0E 2A 71 11 7C FE 18 CA 32 0E 24 22 71
11 C3 DE 0F 2A 71 11 7C B7 CA DE 0F 25 C3 7E 0E
2A 71 11 7D FE 27 D2 9D 0E 2C C3 7E 0E 2E 00 24
7C FE 19 DA 7E 0E 26 18 22 71 11 C3 32 0E 2A 71
11 7D B7 28 04 2D C3 7E 0E 2E 27 25 F2 7E 0E 21
00 00 C3 7E 0E CD A6 0D 0E 19 21 00 D0 06 28 CD
D8 0F 0D C2 CD 0E 21 73 11 06 1B CD D8 0F C3 BF
0E 3E 05 32 03 E0 3E 00 32 70 11 C3 DE 0F 3E 04
32 03 E0 3E 01 C3 E8 0E 2A 71 11 7C B5 CA DE 0F
7D B7 C2 1D 0F 5C 16 00 21 73 11 19 7E B7 C2 1D
0F CD B1 0F CD A6 0D 2B 36 00 C3 AE 0E 2A 71 11
5C 1C 16 00 21 73 11 19 7E 47 B7 3E 28 28 02 3E
50 2A 71 11 95 4F 06 00 CD B1 0F E5 D1 1B CD A6
0D ED B0 2B 36 00 C3 AE 0E 2A 71 11 5C 1C 16 00
21 73 11 19 7E B7 0E 00 2A 71 11 2E 27 28 02 24
0C CD B4 0F 7E B7 C2 DE 0F E5 2A 71 11 3E 27 95
47 79 B7 28 04 3E 28 80 47 D1 D5 E1 2B CD A6 0D
7E 12 36 00 2B 1B 10 F8 C3 DE 0F 2A 71 11 5C 1C
16 00 21 73 11 19 7E B7 2A 71 11 CA 9D 0E 2E 00
7C FE 17 28 05 24 24 C3 7E 0E 24 22 71 11 C3 32
0E 2A 71 11 C5 D5 E5 C1 11 28 00 21 D8 CF 19 05
F2 BE 0F 06 00 09 D1 C1 C9 21 03 E0 36 8A 36 07
36 05 3E 01 32 03 E0 C9 AF 77 23 10 FC C9 E1 D1
C1 F1 C9 AE CD EE FF AE FE AC DE 4E FF AE DF AE
DF 2F FF 26 7D FE FD EE FD AC DF 7E DF AE DF FF

42
Sharp - MZ-80K_MiST/rtl/roms/mram.v Normal file
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@@ -0,0 +1,42 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:04:18 02/22/2008
// Design Name:
// Module Name: mram
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mram(addr,din,dout,en,we);
input [14:0] addr;
input [7:0] din;
output [7:0] dout;
input en, we;
reg [7:0] mem [0:32767];
wire WRITE, READ;
always @( WRITE or din ) begin
if ( WRITE )
mem[ addr ] <= din;
end
assign READ = ~we & en;
assign WRITE = we & en;
assign dout = READ ? mem[ addr ] : 8'hzz;
initial $readmemh( "roms/mon_rom_jp.hex.hex", mem );
endmodule

0
Sharp - MZ-80K_MiST/rtl/80ktc.hex → Sharp - MZ-80K_MiST/rtl/roms/newMon.hex
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18
Sharp - MZ-80K_MiST/rtl/roms/ram.v Normal file
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@@ -0,0 +1,18 @@
module ram( addr, data, ce, we, oe );
input [9:0] addr;
inout [7:0] data;
input ce, we, oe;
reg [7:0] mem [0:1023];
wire WRITE, READ;
always @( WRITE or data ) begin
if ( WRITE )
mem[addr] <= data;
end
assign READ = oe & ce;
assign WRITE = we & ce;
assign data = READ ? mem[addr]: 8'hzz;
endmodule

12
Sharp - MZ-80K_MiST/rtl/scandoubler.v
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@@ -19,6 +19,18 @@
// TODO: Delay vsync one line
`define BITS_TO_FIT(N) ( \
N <= 2 ? 0 : \
N <= 4 ? 1 : \
N <= 8 ? 2 : \
N <= 16 ? 3 : \
N <= 32 ? 4 : \
N <= 64 ? 5 : \
N <= 128 ? 6 : \
N <= 256 ? 7 : \
N <= 512 ? 8 : \
N <=1024 ? 9 : 10 )
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
(
// system interface

33
Sharp - MZ-80K_MiST/rtl/sigma_delta_dac.v Normal file
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@@ -0,0 +1,33 @@
//
// PWM DAC
//
// MSBI is the highest bit number. NOT amount of bits!
//
module sigma_delta_dac #(parameter MSBI=0)
(
output reg DACout, //Average Output feeding analog lowpass
input [MSBI:0] DACin, //DAC input (excess 2**MSBI)
input CLK,
input RESET
);
reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
reg [MSBI+2:0] DeltaB; //B input of Delta Adder
always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
always @(*) DeltaAdder = DACin + DeltaB;
always @(*) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge CLK or posedge RESET) begin
if(RESET) begin
SigmaLatch <= 1'b1 << (MSBI+1);
DACout <= 1;
end else begin
SigmaLatch <= SigmaAdder;
DACout <= ~SigmaLatch[MSBI+2];
end
end
endmodule

2
Sharp - MZ-80K_MiST/rtl/sound.v
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@@ -20,7 +20,7 @@
//////////////////////////////////////////////////////////////////////////////////
module sound(CLK_50MHZ, SW, TP1);
input CLK_50MHZ;
input [7:0] SW;
input SW;
output TP1;
reg [14:0] count = 0;
reg [14:0] count2 = 1;

47
Sharp - MZ-80K_MiST/rtl/vga.v
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@@ -18,26 +18,30 @@
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga(CLK_50MHZ, VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC, Pix_ce,
VGA_ADDR, VGA_DATA, BUS_REQ, BUS_ACK);
input CLK_50MHZ;
output VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC;
output Pix_ce;
output [11:0] VGA_ADDR;
input [7:0] VGA_DATA;
output BUS_REQ;
input BUS_ACK;
module vga(
input CLK_50MHZ,
output VGA_RED,
output VGA_GREEN,
output VGA_BLUE,
output VGA_HSYNC,
output VGA_VSYNC,
output VGA_VBLANK,
output [11:0] VGA_ADDR,
input [7:0] VGA_DATA,
output BUS_REQ,
input BUS_ACK
);
reg [9:0] x = 0;
reg [9:0] y = 0;
reg [1:0] counter = 0;
wire display;
wire [9:0] gx, gy; // <EFBFBD>O<EFBFBD><EFBFBD><EFBFBD>t<EFBFBD>B<EFBFBD>b<EFBFBD>N<EFBFBD><EFBFBD>W(0,0)-(639,399)
wire [9:0] gx, gy; //(0,0)-(639,399)
always @(posedge CLK_50MHZ) begin
counter <= counter + 1;
end
assign Pix_ce = counter[0];
assign gx = x - 144; // (96+48)
assign gx = x - 144; // (96+48) sync pulse + back porch
assign gy = y - 71; // (2+29+40)
always @(posedge counter[0]) begin
if ( x < 800 )
@@ -51,13 +55,21 @@ module vga(CLK_50MHZ, VGA_RED, VGA_GREEN, VGA_BLUE, VGA_HSYNC, VGA_VSYNC, Pix_ce
y <= 0;
end
end
// CGROM<EFBFBD>̎<EFBFBD><EFBFBD>
// CGROM
wire [7:0] cgrom_data;
wire [11:0] cgrom_addr;
cgrom cgrom(.address(cgrom_addr), .clock(CLK_50MHZ), .q(cgrom_data), .rden(1'b1));
wire [5:0] cx, cy; // <EFBFBD>L<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>N<EFBFBD>^<EFBFBD>[<EFBFBD><EFBFBD>W<EFBFBD>֕ϊ<EFBFBD>(0,0)-(79,24)
assign cx = gx >> 4; // <EFBFBD>P<EFBFBD>U<EFBFBD>Ŋ<EFBFBD><EFBFBD><EFBFBD>
assign cy = gy >> 4; // <EFBFBD>P<EFBFBD>U<EFBFBD>Ŋ<EFBFBD><EFBFBD><EFBFBD>
cg_rom cg_rom(
.address(cgrom_addr),
.clock(CLK_50MHZ),
.q(cgrom_data),
.clken(1'b1)
);
wire [5:0] cx, cy; //(0,0)-(79,24)
assign cx = gx >> 4;
assign cy = gy >> 4;
assign VGA_ADDR = (cy * 40) + cx;
assign cgrom_addr = {VGA_DATA, gy[3:1]};
@@ -69,4 +81,5 @@ cgrom cgrom(.address(cgrom_addr), .clock(CLK_50MHZ), .q(cgrom_data), .rden(1'b1)
assign VGA_BLUE = 0; //display ? (cgrom_data[7-((gx>>1) & 7)]) : 0;
assign VGA_HSYNC = x < 96 ? 0 : 1;
assign VGA_VSYNC = y < 2 ? 0 : 1;
assign VGA_VBLANK = (x == 639 & y == 499) ? 1 : 0;
endmodule

2
Sharp - MZ-80K_MiST/rtl/video_mixer.sv
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@@ -23,7 +23,7 @@ module video_mixer
parameter LINE_LENGTH = 768,
parameter HALF_DEPTH = 0,
parameter OSD_COLOR = 3'd4,
parameter OSD_COLOR = 3'd7,
parameter OSD_X_OFFSET = 10'd0,
parameter OSD_Y_OFFSET = 10'd0
)

3
Sharp - MZ-80K_MiST/rtl/vram.qip
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@@ -1,3 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "vram.v"]

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Sharp - MZ-80K_MiST/snapshot/mz80k_mist.rbf
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