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113 lines
3.1 KiB
VHDL
113 lines
3.1 KiB
VHDL
--
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-- iodecode.vhd
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--
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-- Manage access for I/O, Ram and Rom
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--
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-- Copyright (C)2001 - 2005 SEILEBOST
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-- All rights reserved.
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--
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-- $Id: iodecode.vhd, v0.10 2009/06/25 00:00:00 SEILEBOST $
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--
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-- TODO :
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-- Remark :
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-- 08/03/09 : Retour en arrière
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Library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_STD.all;
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--use IEEE.std_logic_unsigned.all;
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entity iodecode is
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port ( RESETn : in std_logic;
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CLK_1 : in std_logic;
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ADDR : in std_logic_vector(15 downto 0);
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ADDR_LE : in std_logic;
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MAPn : in std_logic;
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CSROMn : out std_logic;
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CSRAMn : out std_logic;
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CSIOn : out std_logic
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);
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end entity iodecode;
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architecture iodecode_arch of iodecode is
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signal lCSROMn : std_logic;
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signal lCSRAMn : std_logic;
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signal lCSIOn : std_logic;
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signal lADDR : std_logic_vector(15 downto 0);
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begin
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-- Latch BAP
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u_laddr: PROCESS ( ADDR_LE, resetn )
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begin
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if (resetn = '0') then
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lADDR<= (OTHERS => '0');
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elsif rising_edge(ADDR_LE) then
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lAddr<= Addr;
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end if;
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end process;
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-- PAGE I/O : 0x300-0x3FF
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-- lCSIOn <= '0' WHEN (lADDR(7 downto 0) = "00000011") AND (CLK_1 = '1') ELSE '1';
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lCSIOn <= '0' WHEN (ADDR(15 downto 8) = "00000011") AND (ADDR_LE = '1') ELSE '1';
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--p_CSION : process(CLK_1)
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--begin
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-- lCSIOn <= '1';
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-- if (rising_edge(CLK_1)) then
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-- if (lADDR(7 downto 0) = "00000011") then
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-- lCSION <= '0';
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-- end if;
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-- end if;
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--end process;
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-- PAGE ROM : 0xC000-0xFFFF
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-- lCSROMn <= '0' WHEN (lADDR(7 downto 6) = "11" AND MAPn = '1' AND CLK_1 = '1') ELSE '1'; p_CSION : process(CLK_1)
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lCSROMn <= '0' WHEN (ADDR(15 downto 14) = "11" AND MAPn = '1' AND ADDR_LE = '1') ELSE '1';
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--p_CSROMN : process(CLK_1)
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--begin
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-- lCSROMn <= '1';
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-- if (rising_edge(CLK_1)) then
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-- if (lADDR(7 downto 6) = "11" AND MAPn = '1') then
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-- lCSROMn <= '0';
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-- end if;
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-- end if;
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-- end process;
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-- PAGR RAM : le reste ...
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-- lCSRAMn <= '0' WHEN -- Partie Ram shadow
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-- (lADDR(7 downto 6) = "11" AND MAPn = '0' AND CLK_1 = '1')
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-- OR
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-- -- Partie Ram normale
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-- ( (lADDR(7 downto 0) /= "00000011" and lADDR(7 downto 6) /= "11")
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-- AND MAPn = '1' AND CLK_1 = '1')
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-- ELSE '1';
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lCSRAMn <= '0' WHEN -- Partie Ram shadow
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(ADDR(15 downto 14) = "11" AND MAPn = '0' AND ADDR_LE = '1')
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OR
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-- Partie Ram normale
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(((ADDR(15 downto 8) /= "00000011") AND (ADDR(15 downto 14) /= "11")) AND MAPn = '1' AND ADDR_LE = '1')
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ELSE '1';
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--p_CSRAMN : process(CLK_1)
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--begin
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-- lCSRAMn <= '1';
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-- if (rising_edge(CLK_1)) then
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-- if ((lADDR(7 downto 6) = "11" AND MAPn = '0')
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-- OR ((lADDR(7 downto 0) /= "00000011" and lADDR(7 downto 6) /= "11")
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-- AND MAPn = '1')) then
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-- lCSRAMn <= '0';
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-- end if;
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-- end if;
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--end process;
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-- Assign output signal
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CSROMn <= lCSROMn;
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CSRAMn <= lCSRAMn;
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CSIOn <= lCSIOn;
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end architecture iodecode_arch;
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