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23 lines
377 B
Systemverilog
23 lines
377 B
Systemverilog
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module ram88 (
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input clk,
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input [12:0] addr,
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input [12:0] addrb,
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input [7:0] din,
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input we,
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input cs,
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output reg [7:0] dout,
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output reg [7:0] doutb
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);
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reg [7:0] memory[8191:0] /*verilator public_flat_rd*/;
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always @(posedge clk) begin
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if (~cs) begin
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if (~we) memory[addr] <= din;
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dout <= memory[addr];
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end
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doutb <= memory[addrb];
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end
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endmodule
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