mirror of
https://github.com/Gehstock/Mist_FPGA.git
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112 lines
3.0 KiB
Systemverilog
112 lines
3.0 KiB
Systemverilog
//============================================================================
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// Copyright (C) 2023 Martin Donlon
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module ga23_layer(
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input clk,
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input ce_pix,
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input NL,
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input large_tileset,
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// io registers
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input [9:0] x_ofs,
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input [9:0] y_ofs,
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input [7:0] control,
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// position
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input [9:0] x_base,
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input [9:0] y,
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input [9:0] rowscroll,
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// vram address for current tile
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output [14:0] vram_addr,
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//
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input load,
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input [15:0] attrib,
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input [15:0] index,
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output prio_out,
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output [10:0] color_out,
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input [31:0] sdr_data,
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output reg [21:0] sdr_addr,
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output reg sdr_req,
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input sdr_ack,
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input dbg_enabled
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);
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wire [14:0] vram_base = { control[1:0], 13'd0 };
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wire wide = control[2];
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wire enabled = ~control[4] & dbg_enabled;
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wire en_rowscroll = control[6];
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wire [9:0] x = x_base + ( en_rowscroll ? rowscroll : x_ofs );
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wire [6:0] tile_x = NL ? ( x[9:3] - ( wide ? 7'd32 : 7'd0) ) : ( x[9:3] + ( wide ? 7'd32 : 7'd0) );
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wire [5:0] tile_y = y[8:3];
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assign vram_addr = wide ? {vram_base[14], tile_y, tile_x[6:0], 1'b0} : {vram_base[14:13], tile_y, tile_x[5:0], 1'b0};
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reg [3:0] cnt;
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reg [1:0] prio;
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reg [6:0] palette;
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reg flip_x;
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wire flip_y = attrib[10];
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reg [2:0] offset;
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always_ff @(posedge clk) begin
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if (ce_pix) begin
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cnt <= cnt + 4'd1;
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if (load & dbg_enabled) begin
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cnt <= 4'd0;
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sdr_addr <= { (large_tileset ? attrib[15] : 1'b0), index, flip_y ? ~y[2:0] : y[2:0], 2'b00 };
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sdr_req <= ~sdr_req;
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palette <= attrib[6:0];
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prio <= attrib[8:7];
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flip_x <= attrib[9] ^ NL;
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offset <= x[2:0] ^ {3{NL}};
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end
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end
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end
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wire [1:0] shift_prio_out;
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wire [10:0] shift_color_out;
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ga23_shifter shifter(
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.clk(clk),
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.ce_pix(ce_pix),
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.offset(offset),
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.load(load),
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.reverse(flip_x),
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.row(sdr_data),
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.palette(palette),
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.prio(prio),
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.color_out(shift_color_out),
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.prio_out(shift_prio_out)
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);
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assign color_out = enabled ? shift_color_out : 11'd0;
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assign prio_out = enabled ? ( ( shift_prio_out[0] & shift_color_out[3] ) | ( shift_prio_out[1] & |shift_color_out[3:0] ) ) : 1'b0;
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endmodule |