mirror of
https://github.com/Gehstock/Mist_FPGA.git
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729 lines
18 KiB
Systemverilog
729 lines
18 KiB
Systemverilog
//============================================================================
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// Irem M92 for MiSTer FPGA - Main module
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//
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// Copyright (C) 2023 Martin Donlon
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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import m92_pkg::*;
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module m92 (
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input clk_sys,
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input reset_n,
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output reg ce_pix,
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output flipped,
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input board_cfg_t board_cfg,
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output [7:0] R,
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output [7:0] G,
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output [7:0] B,
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output HSync,
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output VSync,
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output HBlank,
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output VBlank,
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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input [3:0] coin,
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input [3:0] start_buttons,
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input [9:0] p1_input,
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input [9:0] p2_input,
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input [9:0] p3_input,
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input [9:0] p4_input,
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input [23:0] dip_sw,
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input pause_rq,
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output cpu_paused,
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output [24:0] sdr_vram_addr,
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input [31:0] sdr_vram_data,
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output sdr_vram_req,
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output [24:0] sdr_sprite_addr,
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input [63:0] sdr_sprite_dout,
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output sdr_sprite_req,
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input sdr_sprite_ack,
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output sdr_sprite_refresh,
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output [24:0] sdr_bg_addr_a,
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input [31:0] sdr_bg_data_a,
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output sdr_bg_req_a,
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input sdr_bg_ack_a,
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output [24:0] sdr_bg_addr_b,
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input [31:0] sdr_bg_data_b,
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output sdr_bg_req_b,
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input sdr_bg_ack_b,
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output [24:0] sdr_bg_addr_c,
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input [31:0] sdr_bg_data_c,
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output sdr_bg_req_c,
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input sdr_bg_ack_c,
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output reg [24:0] sdr_cpu_addr,
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input [15:0] sdr_cpu_dout,
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output reg [15:0] sdr_cpu_din,
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output reg sdr_cpu_req,
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input sdr_cpu_ack,
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output reg [1:0] sdr_cpu_wr_sel,
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output reg [24:0] sdr_audio_cpu_addr,
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input [15:0] sdr_audio_cpu_dout,
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output reg [15:0] sdr_audio_cpu_din,
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output reg sdr_audio_cpu_req,
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input sdr_audio_cpu_ack,
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output reg [1:0] sdr_audio_cpu_wr_sel,
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output [24:0] sdr_audio_addr,
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input [63:0] sdr_audio_dout,
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output sdr_audio_req,
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input sdr_audio_ack,
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input clk_bram,
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input bram_wr,
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input [7:0] bram_data,
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input [19:0] bram_addr,
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input [4:0] bram_cs,
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input ioctl_download,
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input ioctl_wr,
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input [26:0] ioctl_addr,
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input [7:0] ioctl_dout,
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input ioctl_upload,
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output [7:0] ioctl_upload_index,
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output [7:0] ioctl_din,
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input ioctl_rd,
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output ioctl_upload_req,
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input [2:0] dbg_en_layers,
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input dbg_solid_sprites,
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input en_audio_filters,
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input dbg_fm_en,
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input sprite_freeze,
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input dbg_io_write,
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input [7:0] dbg_io_data,
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output reg dbg_io_wait
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);
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assign ioctl_upload_index = 8'd1;
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assign flipped = NL;
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wire [15:0] rgb_color;
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assign R = { rgb_color[4:0], rgb_color[4:2] };
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assign G = { rgb_color[9:5], rgb_color[9:7] };
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assign B = { rgb_color[14:10], rgb_color[14:12] };
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reg paused = 0;
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assign cpu_paused = paused;
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always @(posedge clk_sys) begin
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if (pause_rq & ~paused) begin
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if (~cpu_mem_read & ~cpu_mem_write & ~mem_rq_active & vpulse) begin
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paused <= 1;
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end
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end else if (~pause_rq & paused) begin
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paused <= ~vpulse;
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end
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end
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wire ce_13m;
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jtframe_frac_cen #(2) pixel_cen
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(
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.clk(clk_sys),
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.cen_in(1),
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.n(10'd1),
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.m(10'd3),
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.cen({ce_pix, ce_13m})
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);
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wire ce_9m, ce_18m;
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jtframe_frac_cen #(2) cpu_cen
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(
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.clk(clk_sys),
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.cen_in(1),
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.n(10'd9),
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.m(10'd20),
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.cen({ce_9m, ce_18m})
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);
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wire dma_busy;
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wire [15:0] cpu_mem_out;
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wire [19:0] cpu_mem_addr;
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wire [1:0] cpu_mem_sel;
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// v30 bus read/write signals are only asserted for a single clock cycle, so latch them for an additional one
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reg cpu_mem_read_lat, cpu_mem_write_lat;
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wire cpu_mem_read_w, cpu_mem_write_w;
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wire cpu_mem_read = cpu_mem_read_w | cpu_mem_read_lat;
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wire cpu_mem_write = cpu_mem_write_w | cpu_mem_write_lat;
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wire cpu_io_read, cpu_io_write;
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wire [7:0] cpu_io_in;
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wire [7:0] cpu_io_out;
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wire [7:0] cpu_io_addr;
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wire [15:0] cpu_mem_in;
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/* Global signals from schematics */
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wire IOWR = cpu_io_write; // IO Write
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wire IORD = cpu_io_read; // IO Read
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wire MWR = cpu_mem_write; // Mem Write
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wire MRD = cpu_mem_read; // Mem Read
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wire [15:0] cpu_word_out = cpu_mem_addr[0] ? { cpu_mem_out[7:0], 8'h00 } : cpu_mem_out;
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wire [1:0] cpu_word_byte_sel = cpu_mem_addr[0] ? { cpu_mem_sel[0], 1'b0 } : cpu_mem_sel;
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reg [15:0] cpu_ram_rom_data;
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wire [24:0] cpu_region_addr;
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wire cpu_region_writable;
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wire ram_rom_memrq;
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wire buffer_memrq;
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wire sprite_control_memrq;
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wire video_control_memrq;
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wire eeprom_memrq;
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wire banked_memrq;
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wire [7:0] snd_latch_dout;
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wire snd_latch_rdy;
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reg [1:0] ce_counter_cpu;
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reg ce_cpu, ce_4x_cpu;
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reg mem_rq_active = 0;
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always @(posedge clk_sys, negedge reset_n) begin
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if (!reset_n) begin
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ce_cpu <= 0;
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ce_4x_cpu <= 0;
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ce_counter_cpu <= 0;
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end else begin
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ce_cpu <= 0;
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ce_4x_cpu <= 0;
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if (~paused) begin
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if (~((ram_rom_memrq) & (cpu_mem_read | cpu_mem_write)) & ~mem_rq_active) begin // stall main cpu while fetching from sdram
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ce_counter_cpu <= ce_counter_cpu + 2'd1;
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ce_4x_cpu <= 1;
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ce_cpu <= &ce_counter_cpu;
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end
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end
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end
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end
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function [15:0] word_shuffle(input [19:0] addr, input [15:0] data);
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begin
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word_shuffle = addr[0] ? { 8'h00, data[15:8] } : data;
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end
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endfunction
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always_ff @(posedge clk_sys or negedge reset_n) begin
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if (!reset_n) begin
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mem_rq_active <= 0;
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end else begin
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cpu_mem_read_lat <= cpu_mem_read_w;
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cpu_mem_write_lat <= cpu_mem_write_w;
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if (!mem_rq_active) begin
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if (ram_rom_memrq & ((cpu_mem_read_w & ~cpu_mem_read_lat) | (cpu_mem_write_w & ~cpu_mem_write_lat))) begin // sdram request
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sdr_cpu_wr_sel <= 2'b00;
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sdr_cpu_addr <= cpu_region_addr;
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if (cpu_mem_write & cpu_region_writable ) begin
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sdr_cpu_wr_sel <= cpu_word_byte_sel;
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sdr_cpu_din <= cpu_word_out;
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end
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sdr_cpu_req <= ~sdr_cpu_req;
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mem_rq_active <= 1;
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end
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end else if (sdr_cpu_req == sdr_cpu_ack) begin
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mem_rq_active <= 0;
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cpu_ram_rom_data <= sdr_cpu_dout;
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end
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end
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end
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wire rom0_ce, rom1_ce, ram_cs2;
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reg [7:0] dbg_io_latch;
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reg [3:0] bank_select = 4'd0;
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wire [7:0] switches_p1 = board_cfg.kick_harness ? { p1_input[4], p1_input[5], p1_input[6], 1'b0, p1_input[3], p1_input[2], p1_input[1], p1_input[0] }
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: { p1_input[4], p1_input[5], 1'b0, 1'b0, p1_input[3], p1_input[2], p1_input[1], p1_input[0] };
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wire [7:0] switches_p2 = board_cfg.kick_harness ? { p2_input[4], p2_input[5], p2_input[6], 1'b0, p2_input[3], p2_input[2], p2_input[1], p2_input[0] }
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: { p2_input[4], p2_input[5], 1'b0, 1'b0, p2_input[3], p2_input[2], p2_input[1], p2_input[0] };
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wire [7:0] switches_p3 = board_cfg.kick_harness ? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 }
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: { p3_input[4], p3_input[5], coin[2], start_buttons[2], p3_input[3], p3_input[2], p3_input[1], p3_input[0] };
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wire [7:0] switches_p4 = board_cfg.kick_harness ? { p2_input[9], p2_input[8], p2_input[7], 1'b0, p1_input[9], p1_input[8], p1_input[7], 1'b0 }
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: { p4_input[4], p4_input[5], coin[3], start_buttons[3], p4_input[3], p4_input[2], p4_input[1], p4_input[0] };
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wire [15:0] switches_p1_p2 = { ~switches_p2, ~switches_p1 };
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`ifdef M92_DEBUG_IO
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wire [15:0] switches_p3_p4 = { dbg_io_latch, dbg_io_latch };
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`else
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wire [15:0] switches_p3_p4 = { ~switches_p4, ~switches_p3 };
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`endif
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wire [15:0] flags = { ~dip_sw[23:16], ~dma_busy, 1'b1, 1'b1 /*TEST*/, 1'b1 /*R*/, ~coin[1:0], ~start_buttons[1:0] };
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reg [7:0] sys_flags = 0;
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wire COIN0 = sys_flags[0];
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wire COIN1 = sys_flags[1];
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wire SOFT_NL = ~sys_flags[2];
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wire CBLK = sys_flags[3];
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wire BRQ = ~sys_flags[4];
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wire BANK = sys_flags[5];
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wire NL = SOFT_NL ^ ~dip_sw[8];
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// TODO BANK, CBLK, NL
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always @(posedge clk_sys) begin
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if (IOWR && cpu_io_addr == 8'h02) sys_flags <= cpu_io_out[7:0];
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if (IOWR && cpu_io_addr == 8'h20) bank_select <= cpu_io_out[3:0];
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end
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reg [15:0] vid_ctrl;
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always @(posedge clk_sys or negedge reset_n) begin
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if (~reset_n) begin
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vid_ctrl <= 0;
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end else if (video_control_memrq & MWR) begin
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vid_ctrl <= cpu_word_out;
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end
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end
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`ifdef M92_DEBUG_IO
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always @(posedge clk_sys or negedge reset_n) begin
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if (~reset_n) begin
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dbg_io_wait <= 0;
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dbg_io_latch <= 8'hff;
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end else begin
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if (IORD && cpu_io_addr == 8'h06) begin
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dbg_io_wait <= 0;
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end
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if (dbg_io_write) begin
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dbg_io_wait <= 1;
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dbg_io_latch <= dbg_io_data;
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end
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end
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end
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`endif
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wire [15:0] ga21_dout;
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wire [7:0] eeprom_dout;
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// mux io and memory reads
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always_comb begin
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bit [15:0] d16;
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bit [15:0] io16;
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if (buffer_memrq) d16 = ga21_dout;
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else if(eeprom_memrq) d16 = { eeprom_dout, eeprom_dout };
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else d16 = cpu_ram_rom_data;
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cpu_mem_in = word_shuffle(cpu_mem_addr, d16);
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case ({cpu_io_addr[7:1], 1'b0})
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8'h00: io16 = switches_p1_p2;
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8'h02: io16 = flags;
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8'h04: io16 = ~dip_sw[15:0];
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8'h06: io16 = switches_p3_p4;
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8'h08: io16 = { snd_latch_dout, snd_latch_dout };
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default: io16 = 16'hffff;
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endcase
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cpu_io_in = cpu_io_addr[0] ? io16[15:8] : io16[7:0];
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end
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wire int_req, int_ack;
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wire [8:0] int_vector;
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v30 #(.INTACK_DELAY(0)) v30(
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.clk(clk_sys),
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.ce(ce_cpu),
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.ce_4x(ce_4x_cpu),
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.reset(~reset_n),
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.turbo(1),
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.SLOWTIMING(0),
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.cpu_idle(),
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.cpu_halt(),
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.cpu_irqrequest(),
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.cpu_prefix(),
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.bus_read(cpu_mem_read_w),
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.bus_write(cpu_mem_write_w),
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.bus_be(cpu_mem_sel),
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.bus_addr(cpu_mem_addr),
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.bus_datawrite(cpu_mem_out),
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.bus_dataread(cpu_mem_in),
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.irqrequest_in(int_req),
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.irqvector_in(int_vector),
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.irqrequest_ack(int_ack),
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// TODO
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.cpu_done(),
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.RegBus_Din(cpu_io_out),
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.RegBus_Adr(cpu_io_addr),
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.RegBus_wren(cpu_io_write),
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.RegBus_rden(cpu_io_read),
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.RegBus_Dout(cpu_io_in)
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);
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address_translator address_translator(
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.A(cpu_mem_addr),
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.board_cfg(board_cfg),
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.ram_rom_memrq(ram_rom_memrq),
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.sdr_addr(cpu_region_addr),
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.writable(cpu_region_writable),
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.buffer_memrq(buffer_memrq),
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.sprite_control_memrq(sprite_control_memrq),
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.video_control_memrq(video_control_memrq),
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.eeprom_memrq(eeprom_memrq),
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.bank_select(bank_select)
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);
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wire vblank, hblank, vsync, hsync, vpulse, hpulse, hint;
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m92_pic m92_pic(
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.clk(clk_sys),
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.ce(ce_cpu),
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.reset(~reset_n),
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.cs((IORD | IOWR) & ~cpu_io_addr[7] & cpu_io_addr[6] & ~cpu_io_addr[0]), // 0x40-0x43
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.wr(IOWR),
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.rd(0),
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.a0(cpu_io_addr[1]),
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.din(cpu_io_out),
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.int_req(int_req),
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.int_vector(int_vector),
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.int_ack(int_ack),
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.intp({4'd0, snd_latch_rdy, hint, ~dma_busy, vblank})
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);
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assign HSync = hsync;
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assign HBlank = hblank;
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assign VSync = vsync;
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assign VBlank = vblank;
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wire objram_we;
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wire [15:0] objram_data, objram_q;
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wire [63:0] objram_q64;
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wire [10:0] objram_addr;
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wire [11:0] ga22_color, ga23_color;
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wire ga23_prio;
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objram objram(
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.clk(clk_sys),
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.addr(objram_addr),
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.we(objram_we),
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.data(objram_data),
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.q(objram_q),
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.q64(objram_q64)
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);
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wire bufram_we;
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wire [15:0] bufram_data;
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wire [15:0] bufram_q00, bufram_q01, bufram_q10, bufram_q11;
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wire [10:0] bufram_addr;
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wire [1:0] bufram_cs = ( ~bufram_addr[10] & ~dma_busy ) ? { 1'b0, vid_ctrl[0] } :
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( bufram_addr[10] & ~dma_busy ) ? { vid_ctrl[2], vid_ctrl[1] } :
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( ~bufram_addr[10] & dma_busy ) ? { 1'b0, vid_ctrl[3] } :
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( bufram_addr[10] & dma_busy ) ? { vid_ctrl[5], vid_ctrl[4] } : 2'b00;
|
|
|
|
wire [15:0] bufram_q;
|
|
|
|
wire [12:0] ga21_palram_addr;
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|
wire ga21_palram_we, ga21_palram_cs;
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|
wire [15:0] ga21_palram_dout;
|
|
wire [15:0] palram_q;
|
|
wire [10:0] ga22_count;
|
|
|
|
|
|
|
|
singleport_unreg_ram #(.widthad(13), .width(16), .name("BUFRAM")) bufram(
|
|
.clock(clk_sys),
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|
.address({bufram_cs, bufram_addr}),
|
|
.q(bufram_q),
|
|
.wren(bufram_we),
|
|
.data(bufram_data)
|
|
);
|
|
|
|
palram palram(
|
|
.clk(clk_sys),
|
|
|
|
.ce_pix(ce_pix),
|
|
|
|
.vid_ctrl(vid_ctrl),
|
|
.dma_busy(dma_busy),
|
|
|
|
.cpu_addr(cpu_mem_addr[10:1]),
|
|
|
|
.ga21_addr(ga21_palram_addr),
|
|
.ga21_we(ga21_palram_we),
|
|
.ga21_req(ga21_palram_cs),
|
|
|
|
.obj_color(ga22_color[10:0]),
|
|
.obj_prio(ga22_color[11]),
|
|
.obj_active(|ga22_color[3:0]),
|
|
|
|
.pf_color(ga23_color),
|
|
.pf_prio(~ga23_prio),
|
|
|
|
.din(ga21_palram_dout),
|
|
.dout(palram_q),
|
|
|
|
.rgb_out(rgb_color)
|
|
);
|
|
|
|
GA21 ga21(
|
|
.clk(clk_sys),
|
|
.ce(ce_9m),
|
|
|
|
.reset(),
|
|
|
|
.din(cpu_word_out),
|
|
.dout(ga21_dout),
|
|
|
|
.addr(cpu_mem_addr[11:1]),
|
|
|
|
.reg_cs(sprite_control_memrq),
|
|
.buf_cs(buffer_memrq),
|
|
.wr(MWR),
|
|
|
|
.busy(dma_busy),
|
|
|
|
.obj_dout(objram_data),
|
|
.obj_din(objram_q),
|
|
.obj_addr(objram_addr),
|
|
.obj_we(objram_we),
|
|
|
|
.buffer_dout(bufram_data),
|
|
.buffer_din(bufram_q),
|
|
.buffer_addr(bufram_addr),
|
|
.buffer_we(bufram_we),
|
|
|
|
.count(ga22_count),
|
|
|
|
.pal_addr(ga21_palram_addr),
|
|
.pal_dout(ga21_palram_dout),
|
|
.pal_din(palram_q),
|
|
.pal_we(ga21_palram_we),
|
|
.pal_cs(ga21_palram_cs)
|
|
);
|
|
|
|
GA22 ga22(
|
|
.clk(clk_sys),
|
|
|
|
.ce(ce_13m), // 13.33Mhz
|
|
|
|
.ce_pix(ce_pix), // 6.66Mhz
|
|
|
|
.reset(~reset_n),
|
|
|
|
.color(ga22_color),
|
|
|
|
.NL(NL),
|
|
.hpulse(hpulse),
|
|
.vpulse(vpulse),
|
|
|
|
.count(ga22_count),
|
|
|
|
.obj_in(objram_q64),
|
|
|
|
.sdr_data(sdr_sprite_dout),
|
|
.sdr_addr(sdr_sprite_addr),
|
|
.sdr_req(sdr_sprite_req),
|
|
.sdr_ack(sdr_sprite_ack),
|
|
.sdr_refresh(sdr_sprite_refresh),
|
|
|
|
.dbg_solid_sprites(dbg_solid_sprites)
|
|
);
|
|
|
|
wire [14:0] vram_addr;
|
|
assign sdr_vram_addr = {REGION_VRAM.base_addr[24:16], vram_addr, 1'b0};
|
|
|
|
GA23 ga23(
|
|
.clk(clk_sys),
|
|
|
|
.ce(ce_pix),
|
|
|
|
.reset(~reset_n),
|
|
|
|
.paused(paused),
|
|
|
|
.io_wr(IOWR),
|
|
.addr(IOWR ? {8'd0, cpu_io_addr} : cpu_mem_addr),
|
|
.cpu_din(IOWR ? {8'd0, cpu_io_out} : cpu_mem_out),
|
|
|
|
.vram_addr(vram_addr),
|
|
.vram_din(sdr_vram_data),
|
|
.vram_req(sdr_vram_req),
|
|
|
|
.NL(NL),
|
|
.large_tileset(board_cfg.large_tileset),
|
|
|
|
.sdr_data_a(sdr_bg_data_a),
|
|
.sdr_addr_a(sdr_bg_addr_a),
|
|
.sdr_req_a(sdr_bg_req_a),
|
|
.sdr_ack_a(sdr_bg_ack_a),
|
|
|
|
.sdr_data_b(sdr_bg_data_b),
|
|
.sdr_addr_b(sdr_bg_addr_b),
|
|
.sdr_req_b(sdr_bg_req_b),
|
|
.sdr_ack_b(sdr_bg_ack_b),
|
|
|
|
.sdr_data_c(sdr_bg_data_c),
|
|
.sdr_addr_c(sdr_bg_addr_c),
|
|
.sdr_req_c(sdr_bg_req_c),
|
|
.sdr_ack_c(sdr_bg_ack_c),
|
|
|
|
.vblank(vblank),
|
|
.hblank(hblank),
|
|
.vsync(vsync),
|
|
.hsync(hsync),
|
|
.hpulse(hpulse),
|
|
.vpulse(vpulse),
|
|
|
|
.hint(hint),
|
|
|
|
.color_out(ga23_color),
|
|
.prio_out(ga23_prio),
|
|
|
|
.dbg_en_layers(dbg_en_layers)
|
|
);
|
|
|
|
/*
|
|
// Sound board test (select sound with P1 left/right)
|
|
reg [7:0] snd_id;
|
|
reg snd_wr;
|
|
reg left_last, right_last;
|
|
wire left = p1_input[1];
|
|
wire right = p1_input[0];
|
|
|
|
always @(posedge clk_sys) begin
|
|
if (!reset_n) begin
|
|
snd_wr <= 0;
|
|
snd_id <= 0;
|
|
end else begin
|
|
snd_wr <= 0;
|
|
left_last <= left;
|
|
right_last <= right;
|
|
if (!left_last & left) begin
|
|
snd_id <= snd_id - 1'd1;
|
|
snd_wr <= 1;
|
|
end
|
|
if (!right_last & right) begin
|
|
snd_id <= snd_id + 1'd1;
|
|
snd_wr <= 1;
|
|
end
|
|
end
|
|
|
|
end
|
|
*/
|
|
wire [15:0] sound_sample;
|
|
|
|
sound sound(
|
|
.clk_sys(clk_sys),
|
|
.reset(~reset_n),
|
|
.filter_en(en_audio_filters),
|
|
.dbg_fm_en(dbg_fm_en),
|
|
.paused(paused),
|
|
|
|
.latch_wr(IOWR & cpu_io_addr == 8'h00),
|
|
//.latch_wr(snd_wr),
|
|
.latch_rd(IORD & cpu_io_addr == 8'h08),
|
|
.latch_din(cpu_io_out),
|
|
//.latch_din(snd_id),
|
|
.latch_dout(snd_latch_dout),
|
|
.latch_rdy(snd_latch_rdy),
|
|
|
|
.rom_addr(bram_addr),
|
|
.rom_data(bram_data),
|
|
.rom_wr(bram_wr & bram_cs[1]),
|
|
|
|
.secure_addr(bram_addr[7:0]),
|
|
.secure_data(bram_data),
|
|
.secure_wr(bram_wr & bram_cs[0]),
|
|
|
|
.sample(sound_sample),
|
|
|
|
.sdr_cpu_addr(sdr_audio_cpu_addr),
|
|
.sdr_cpu_dout(sdr_audio_cpu_dout),
|
|
.sdr_cpu_din(sdr_audio_cpu_din),
|
|
.sdr_cpu_req(sdr_audio_cpu_req),
|
|
.sdr_cpu_ack(sdr_audio_cpu_ack),
|
|
.sdr_cpu_wr_sel(sdr_audio_cpu_wr_sel),
|
|
|
|
.sdr_addr(sdr_audio_addr),
|
|
.sdr_data(sdr_audio_dout),
|
|
.sdr_req(sdr_audio_req),
|
|
.sdr_ack(sdr_audio_ack)
|
|
);
|
|
|
|
assign AUDIO_L = sound_sample;
|
|
assign AUDIO_R = sound_sample;
|
|
|
|
`ifndef NO_EEPROM
|
|
eeprom_28C64 eeprom(
|
|
.clk(clk_sys),
|
|
.reset(~reset_n),
|
|
.ce(1),
|
|
|
|
.rd(MRD & eeprom_memrq),
|
|
.wr(MWR & eeprom_memrq),
|
|
|
|
.addr(cpu_mem_addr[13:1]),
|
|
.q(eeprom_dout),
|
|
.data(cpu_mem_out[7:0]),
|
|
|
|
.ready(),
|
|
|
|
.modified(ioctl_upload_req),
|
|
.ioctl_download(ioctl_download | bram_cs[2]),
|
|
.ioctl_wr(bram_cs[2] ? bram_wr : ioctl_wr),
|
|
.ioctl_addr(bram_cs[2] ? bram_addr[12:0] : ioctl_addr[12:0]),
|
|
.ioctl_dout(ioctl_dout),
|
|
|
|
.ioctl_upload(ioctl_upload),
|
|
.ioctl_din(ioctl_din),
|
|
.ioctl_rd(ioctl_rd)
|
|
);
|
|
`endif
|
|
|
|
endmodule
|