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98 lines
2.3 KiB
Verilog
98 lines
2.3 KiB
Verilog
/*============================================================================
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Missile Command for MiSTer FPGA - Sync circuit
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Copyright (C) 2022 - Jim Gregory - https://github.com/JimmyStones/
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>.
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===========================================================================*/
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`timescale 1 ps / 1 ps
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`default_nettype none
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module sync
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(
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input wire clk_10M,
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input wire ce_5M,
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input wire reset,
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input wire flip,
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output reg h_sync,
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output reg v_sync,
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output reg h_blank,
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output reg v_blank/*verilator public_flat*/,
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output wire s_phi_x,
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output wire s_3INH,
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output reg [8:0] hcnt/*verilator public_flat*/,
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output reg [7:0] vcnt/*verilator public_flat*/
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);
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///// CLOCKS
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reg s_A7_1;
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reg s_A7_2_n;
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reg s_B8;
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always @(posedge clk_10M)
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begin
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reg h_sync_last;
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reg ce_5M_last;
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reg s_1h_last;
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///// HORIZONTAL COUNTER AND SYNC
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if(ce_5M == 1'b1)
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begin
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hcnt <= hcnt + 9'b1;
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begin
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case (hcnt)
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256: h_blank <= 1;
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260: h_sync <= 1;
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288: h_sync <= 0;
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319:
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begin
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hcnt <= 0;
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h_blank <=0;
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end
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endcase
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end
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///// VERTICAL COUNTER AND SYNC
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if (h_sync == 1'b1 && h_sync_last == 1'b0) begin
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if(flip)
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vcnt <= vcnt + 8'b1;
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else
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vcnt <= vcnt - 8'b1;
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end
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h_sync_last <= h_sync;
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case (vcnt)
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0: v_blank <= flip;
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25: v_blank <= ~flip;
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4: if(flip) v_sync <= 1;
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8: if(flip) v_sync <= 0;
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20: if(~flip) v_sync <= 1;
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16: if(~flip) v_sync <= 0;
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endcase
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end
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ce_5M_last <= ce_5M;
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if(ce_5M && !ce_5M_last) s_A7_1 <= ~s_3INH;
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s_1h_last <= hcnt[0];
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if(hcnt[0] && !s_1h_last) s_A7_2_n <= (~hcnt[1] & hcnt[2]);
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if(!hcnt[0] && s_1h_last) s_B8 <= s_A7_2_n;
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end
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assign s_3INH = (vcnt[7:5] == 3'b111);
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assign s_phi_x = (~(s_B8 & ~s_A7_1)) & (~(s_A7_1 & hcnt[1]));
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endmodule |