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Gehstock.Mist_FPGA/common/Sound/jtopl/jt26.qip
Gyorgy Szombathelyi b81529cebf Update JT modules
2022-12-21 01:19:11 +01:00

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set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) common.qip]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_mmr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_reg.v]