mirror of
https://github.com/Gehstock/Mist_FPGA.git
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170 lines
4.7 KiB
VHDL
170 lines
4.7 KiB
VHDL
-- VHDL Entity r65c02_tc.fsm_intnmi.symbol
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--
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-- Created:
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-- by - eda.UNKNOWN (ENTW-7HPZ200)
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-- at - 12:35:56 10.09.2018
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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entity fsm_intnmi is
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port(
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clk_clk_i : in std_logic;
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nmi_n_i : in std_logic;
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rst_nmi_i : in std_logic;
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rst_rst_n_i : in std_logic;
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ce : in std_logic;
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nmi_o : out std_logic
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);
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-- Declarations
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end fsm_intnmi ;
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-- (C) 2008 - 2013 Jens Gutschmidt
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-- (email: opencores@vivare-services.com)
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--
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-- Versions:
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-- Revision 1.8 2018/09/01 18:07:00 jens
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-- - NMI = '0' need at least 1 cycles for correct
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-- operation now (2 cycles in the past)
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--
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-- Revision 1.7 2013/07/21 11:11:00 jens
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-- - Changing the title block and internal revision history
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--
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-- Revision 1.6 2009/01/04 10:20:47 eda
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-- Changes for cosmetic issues only
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--
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-- Revision 1.5 2009/01/04 09:23:10 eda
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-- - Delete unused nets and blocks (same as R6502_TC)
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-- - Rename blocks
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--
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-- Revision 1.4 2009/01/03 16:53:02 eda
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-- - Unused nets and blocks deleted
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-- - Renamed blocks
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--
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-- Revision 1.3 2009/01/03 16:42:02 eda
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-- - Unused nets and blocks deleted
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-- - Renamed blocks
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--
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-- Revision 1.2 2008/12/31 19:31:24 eda
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-- Production Release
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--
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--
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--
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-- VHDL Architecture r65c02_tc.fsm_intnmi.fsm
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--
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-- Created:
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-- by - eda.UNKNOWN (ENTW-7HPZ200)
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-- at - 12:35:56 10.09.2018
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
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--
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-- COPYRIGHT (C) 2008 - 2013 by Jens Gutschmidt
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--
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
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--
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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architecture fsm of fsm_intnmi is
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type state_type is (
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idle,
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idle1,
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IMP
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);
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-- State vector declaration
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attribute state_vector : string;
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attribute state_vector of fsm : architecture is "current_state";
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-- Declare current and next state signals
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signal current_state : state_type;
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signal next_state : state_type;
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-- Declare any pre-registered internal signals
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signal nmi_o_cld : std_logic ;
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begin
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-----------------------------------------------------------------
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clocked_proc : process (
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clk_clk_i,
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ce,
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rst_rst_n_i
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)
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-----------------------------------------------------------------
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begin
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if (rst_rst_n_i = '0') then
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current_state <= idle;
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-- Default Reset Values
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nmi_o_cld <= '0';
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elsif (clk_clk_i'event and clk_clk_i = '1' and ce = '1') then
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current_state <= next_state;
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-- Default Assignment To Internals
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nmi_o_cld <= '0';
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-- Combined Actions
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case current_state is
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when idle1 =>
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if (nmi_n_i = '0') then
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nmi_o_cld <= '1';
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end if;
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when IMP =>
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nmi_o_cld <= '1';
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if (rst_nmi_i = '1') then
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nmi_o_cld <= '0';
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end if;
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when others =>
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null;
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end case;
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end if;
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end process clocked_proc;
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-----------------------------------------------------------------
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nextstate_proc : process (
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current_state,
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nmi_n_i,
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rst_nmi_i
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)
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-----------------------------------------------------------------
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begin
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case current_state is
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when idle =>
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if (nmi_n_i = '1') then
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next_state <= idle1;
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else
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next_state <= idle;
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end if;
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when idle1 =>
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if (nmi_n_i = '0') then
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next_state <= IMP;
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else
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next_state <= idle1;
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end if;
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when IMP =>
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if (rst_nmi_i = '1') then
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next_state <= idle;
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else
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next_state <= IMP;
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end if;
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when others =>
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next_state <= idle;
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end case;
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end process nextstate_proc;
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-- Concurrent Statements
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-- Clocked output assignments
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nmi_o <= nmi_o_cld;
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end fsm;
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