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40 lines
946 B
VHDL
40 lines
946 B
VHDL
---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY synchronizer IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RAW : IN STD_LOGIC;
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SYNC : OUT STD_LOGIC
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);
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END synchronizer;
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ARCHITECTURE vhdl OF synchronizer IS
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signal ff_next : std_logic_vector(2 downto 0);
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signal ff_reg : std_logic_vector(2 downto 0);
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begin
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-- register
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process(clk)
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begin
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if (clk'event and clk='1') then
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ff_reg <= ff_next;
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end if;
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end process;
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ff_next <= RAW&ff_reg(2 downto 1);
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SYNC <= ff_reg(0);
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end vhdl;
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