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52 lines
1.4 KiB
Verilog
52 lines
1.4 KiB
Verilog
/*============================================================================
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Generic single-port RAM module
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Copyright (C) 2022 - Jim Gregory - https://github.com/JimmyStones/
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>.
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===========================================================================*/
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`timescale 1 ps / 1 ps
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`default_nettype none
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module spram # (
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parameter address_width = 8,
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parameter data_width = 8
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)
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(
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input clock,
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input [(address_width-1):0] address,
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input [(data_width-1):0] data,
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output reg [(data_width-1):0] q,
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input wren
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);
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localparam ramLength = (2**address_width);
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reg [(data_width-1):0] mem [ramLength-1:0];
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always @(posedge clock)
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begin
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if (wren)
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begin
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mem[address] <= data;
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q <= data;
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end
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else
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begin
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q <= mem[address];
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end
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end
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endmodule
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