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119 lines
2.7 KiB
Verilog
119 lines
2.7 KiB
Verilog
/*============================================================================
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Missile Command for MiSTer FPGA - Microprocessor circuit
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Copyright (C) 2022 - Jim Gregory - https://github.com/JimmyStones/
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 3 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>.
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===========================================================================*/
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`timescale 1 ps / 1 ps
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`default_nettype none
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module micro
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(
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input clk_10M,
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input wire s_phi_x,
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input wire s_phi_extend,
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input wire reset/*verilator public_flat*/,
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input wire pause,
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input wire flip,
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input wire s_INTACK_n,
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input wire [8:0] hcnt,
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input wire [7:0] vcnt,
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input wire [7:0] s_db_in,
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output wire s_phi_0/*verilator public_flat*/,
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output wire s_phi_2,
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output reg s_irq_n,
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output wire s_READWRITE,
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output wire s_WRITE_n,
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output wire s_br_w_n,
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output wire s_16FLIP,
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output wire [15:0] s_addr/*verilator public_flat*/,
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output wire [7:0] s_db_out,
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output wire sync/*verilator public_flat*/
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);
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//// TODO - Watchdog
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// L3 - 74S86 - XOR
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assign s_16FLIP = ~vcnt_adjust[4];
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// C4 - 74S32 - OR
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assign s_phi_0 = (s_phi_x | s_phi_extend);
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reg irq_pending;
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wire [7:0] vcnt_adjust = vcnt - 8'd10;
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always @(posedge clk_10M)
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begin
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reg s_INTACK_n_last;
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reg s_16FLIP_last;
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s_INTACK_n_last <= s_INTACK_n;
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s_16FLIP_last <= s_16FLIP;
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if(reset)
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irq_pending <= 1'b1;
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else if (!s_INTACK_n & s_INTACK_n_last)
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irq_pending <= 1'b1;
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else if(s_16FLIP && !s_16FLIP_last)
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irq_pending <= vcnt_adjust[5];
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end
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wire sync_phi0 = (sync && s_phi_0);
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// F7, E7
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always @(posedge clk_10M)
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begin
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reg sync_phi0_last;
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sync_phi0_last <= sync_phi0;
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if(reset)
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s_irq_n <= 1'b1;
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else
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if(sync_phi0 && !sync_phi0_last) s_irq_n <= irq_pending;
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end
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// D3 - 7414 - NOT
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wire s_D3_1 = ~s_phi_0;
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wire s_D3_3 = s_READWRITE;
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// C3 - 7432 - OR
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wire s_C3 = s_D3_1 | s_D3_3;
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// C4 - 7432 - OR
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wire s_C4 = ~hcnt[0] | s_C3;
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assign s_WRITE_n = s_C4;
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assign s_br_w_n = s_D3_3;
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bc6502 bc6502
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(
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.reset(reset),
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.clk(s_phi_0),
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.nmi(1'b0),
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.irq(~s_irq_n),
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.rdy(~pause),
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.so(1'b0),
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.di(s_db_in),
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.dout(s_db_out),
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.rw(s_READWRITE),
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.ma(s_addr),
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.rw_nxt(),
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.ma_nxt(),
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.sync(sync),
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.state(),
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.flags()
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);
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assign s_phi_2 = ~s_phi_0;
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endmodule
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