mirror of
https://github.com/Gehstock/Mist_FPGA.git
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124 lines
3.3 KiB
Verilog
124 lines
3.3 KiB
Verilog
///----------------------------------------------------------------------------
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//
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// Copyright 2022 Darren Olafson
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//
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// MiSTer Copyright (C) 2017 Sorgelig
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//
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//----------------------------------------------------------------------------
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// simple read-only cache
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// specificly for 68k program rom. todo - parameterize
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module cache
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(
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input reset,
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input clk,
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input cache_req,
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input [22:0] cache_addr,
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output reg cache_valid,
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output [15:0] cache_data,
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input [15:0] rom_data,
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input rom_valid,
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output reg rom_req,
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output reg [22:0] rom_addr
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);
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reg [22:10] tag [1023:0];
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reg [1023:0] valid ;
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reg [1:0] state = 0;
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reg [9:0] idx_r;
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wire [9:0] idx = cache_addr[9:0];
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wire hit;
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// if tag value matches the upper bits of the address
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// and valid then no need to pass request to sdram
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assign hit = ( tag[idx] == cache_addr[22:10] && valid[idx] == 1 && state == 1 );
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assign cache_data = ( hit == 1 ) ? cache_dout : rom_data;
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always @ (posedge clk) begin
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cache_valid <= ( cache_req != 0 ) && ( hit == 1 || rom_valid == 1 );
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if ( reset == 1 ) begin
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state <= 0;
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// reset bits that indicate tag is valid
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valid <= 0;
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end else begin
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// if no read request then do nothing
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if ( cache_req == 0 ) begin
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rom_req <= 0;
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state <= 1;
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end else begin
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// if there is a hit then read from cache and say we are done
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if ( hit == 1 ) begin
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rom_req <= 0;
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end else if ( state == 1 ) begin
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// read from memory
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idx_r <= idx;
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// we need to read from sdram
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rom_req <= 1;
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rom_addr <= cache_addr;
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// next state is wait for rom ready
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state <= 2;
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end else if ( state == 2 && rom_valid == 1 ) begin
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// write updated tag
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tag[idx_r] <= rom_addr[22:10];
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// mark tag valid
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valid[idx_r] <= 1'b1;
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cache_din <= rom_data;
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state <= 3;
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end else if ( state == 3 ) begin
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state <= 0;
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end
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end
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end
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end
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reg [15:0] cache_din;
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wire [15:0] cache_dout;
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dual_port_ram #(.LEN(1024), .DATA_WIDTH(16)) cache_ram (
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.clock_a ( clk ),
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.address_a ( idx_r ),
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.wren_a ( state == 3 ),
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.data_a ( cache_din ),
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.q_a ( ),
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.clock_b ( clk ),
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.address_b ( idx ),
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.wren_b ( 0 ),
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.q_b ( cache_dout )
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);
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endmodule
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