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Marcel
2023-07-11 12:37:55 +02:00
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245
Arcade_MiST/Toaplan v1 Hardware/DemonsWorld.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 16:51:06 July 10, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# DemonsWorld_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SMART_RECOMPILE ON
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name TOP_LEVEL_ENTITY DemonsWorld
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/dect.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# -------------------------
# start ENTITY(DemonsWorld)
# Pin & Location Assignments
# ==========================
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
# Fitter Assignments
# ==================
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(DemonsWorld)
# -----------------------
set_global_assignment -name SYSTEMVERILOG_FILE rtl/rtl_demonsworld/DemonsWorld.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/rtl_demonsworld/DemonsWorld_Top.sv
set_global_assignment -name VERILOG_FILE rtl/rtl_demonsworld/chip_select.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name QIP_FILE rtl/common/common.qip
set_global_assignment -name VERILOG_FILE rtl/pll_mist.v
set_global_assignment -name QIP_FILE rtl/TMS320C1X/TMS320C1X.qip
set_global_assignment -name QIP_FILE ../../common/Sound/jtopl/jt26.qip
set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../common/CPU/68000/FX68k/fx68k.qip
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

30
Arcade_MiST/Toaplan v1 Hardware/RallyBike.qpf
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@@ -1,30 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 16:01:18 November 25, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "16:01:18 November 25, 2020"
# Revisions
PROJECT_REVISION = "RallyBike"

244
Arcade_MiST/Toaplan v1 Hardware/RallyBike.qsf
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@@ -1,244 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 12:43:38 July 08, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# RallyBike_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SMART_RECOMPILE ON
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name TOP_LEVEL_ENTITY RallyBike
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/dect.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# ---------------------
# start ENTITY(TaitoSJ)
# Pin & Location Assignments
# ==========================
# Fitter Assignments
# ==================
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(TaitoSJ)
# -------------------
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
set_global_assignment -name SYSTEMVERILOG_FILE rtl/rtl_rallybike/RallyBike.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/rtl_rallybike/RallyBike_Top.sv
set_global_assignment -name VERILOG_FILE rtl/rtl_rallybike/chip_select.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name QIP_FILE rtl/common/common.qip
set_global_assignment -name VERILOG_FILE rtl/pll_mist.v
set_global_assignment -name QIP_FILE ../../common/Sound/jtopl/jt26.qip
set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../common/CPU/68000/FX68k/fx68k.qip
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

5
Arcade_MiST/Toaplan v1 Hardware/DemonsWorld.qpf → Arcade_MiST/Toaplan v1 Hardware/ToaplanV1.qpf
View File

@@ -18,13 +18,14 @@
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 16:01:18 November 25, 2020
# Date created = 11:52:25 July 11, 2023
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "16:01:18 November 25, 2020"
DATE = "11:52:25 July 11, 2023"
# Revisions
PROJECT_REVISION = "ToaplanV1"
PROJECT_REVISION = "DemonsWorld"

28
Arcade_MiST/Toaplan v1 Hardware/Vimana.qsf → Arcade_MiST/Toaplan v1 Hardware/ToaplanV1.qsf
View File

@@ -18,14 +18,14 @@
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 15:05:30 July 08, 2023
# Date created = 16:51:06 July 10, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Vimana_assignment_defaults.qdf
# DemonsWorld_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
@@ -42,8 +42,9 @@
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SMART_RECOMPILE ON
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
@@ -129,7 +130,7 @@ set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name TOP_LEVEL_ENTITY Vimana
set_global_assignment -name TOP_LEVEL_ENTITY ToaplanV1
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
@@ -176,8 +177,8 @@ set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# ---------------------------
# start ENTITY(RallyBike_Top)
# -------------------------
# start ENTITY(DemonsWorld)
# Pin & Location Assignments
# ==========================
@@ -194,14 +195,12 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(RallyBike_Top)
# -------------------------
set_global_assignment -name SYSTEMVERILOG_FILE rtl/rtl_vimana/Vimana.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/rtl_vimana/Vimana_Top.sv
set_global_assignment -name VERILOG_FILE rtl/rtl_vimana/chip_select.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/pll_mist.v
set_global_assignment -name QIP_FILE rtl/common/common.qip
# end ENTITY(DemonsWorld)
# -----------------------
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ToaplanV1.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ToaplanV1_Top.sv
set_global_assignment -name VERILOG_FILE rtl/chip_select.v
set_global_assignment -name QIP_FILE rtl/TMS320C1X/TMS320C1X.qip
set_global_assignment -name QIP_FILE ../../common/Sound/jtopl/jt26.qip
set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../common/CPU/68000/FX68k/fx68k.qip
@@ -240,4 +239,5 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
set_global_assignment -name QIP_FILE rtl/common.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

30
Arcade_MiST/Toaplan v1 Hardware/Vimana.qpf
View File

@@ -1,30 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 16:01:18 November 25, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "16:01:18 November 25, 2020"
# Revisions
PROJECT_REVISION = "Vimana"

30
Arcade_MiST/Toaplan v1 Hardware/Zerowing.qpf
View File

@@ -1,30 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 16:01:18 November 25, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "16:01:18 November 25, 2020"
# Revisions
PROJECT_REVISION = "Zerowing"

244
Arcade_MiST/Toaplan v1 Hardware/Zerowing.qsf
View File

@@ -1,244 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 15:42:51 July 08, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Zerowing_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name TOP_LEVEL_ENTITY Zerowing
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/dect.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# --------------------------
# start ENTITY(Zerowing_Top)
# Pin & Location Assignments
# ==========================
# Fitter Assignments
# ==================
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(Zerowing_Top)
# ------------------------
set_global_assignment -name SYSTEMVERILOG_FILE rtl/rtl_zerowing/Zerowing.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/rtl_zerowing/Zerowing_Top.sv
set_global_assignment -name VERILOG_FILE rtl/rtl_zerowing/chip_select.v
set_global_assignment -name QIP_FILE rtl/common/common.qip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/pll_mist.v
set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../common/Sound/jtopl/jt26.qip
set_global_assignment -name QIP_FILE ../../common/CPU/68000/FX68k/fx68k.qip
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

4
Arcade_MiST/Toaplan v1 Hardware/meta/Demons World - Horror Story (Set 3).mra
View File

@@ -28,6 +28,10 @@
<buttons names="Shot,Jump,Rapid Shot,Slow Scroll,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start,Select"/>
<rom index="1">
<part>00</part>
</rom>
<rom index="0" zip="demonwld2.zip|demonwld.zip" md5="None">
<!-- maincpu - starts at 0x0 -->
<interleave output="16">

4
Arcade_MiST/Toaplan v1 Hardware/meta/Rally Bike - Dash Yarou.mra
View File

@@ -27,6 +27,10 @@
<buttons names="Accelerator,Brake,-,Slow Scroll,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,L,Start,Select"/>
<rom index="1">
<part>01</part>
</rom>
<rom index="0" zip="rallybik.zip" md5="None">
<!-- maincpu - starts at 0x0 -->
<interleave output="16">

2
Arcade_MiST/Toaplan v1 Hardware/meta/Same! Same! Same! (2P Set).mra
View File

@@ -31,7 +31,7 @@
<buttons names="Shot,Bomb,-,Slow Scroll,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,Start,L"/>
<rom index="1">
<part>01</part>
<part>03</part>
</rom>
<rom index="0" zip="samesame2.zip|fireshrk.zip" md5="None">

2
Arcade_MiST/Toaplan v1 Hardware/meta/Truxton - Tatsujin.mra
View File

@@ -31,7 +31,7 @@
<buttons names="Shot,Bomb,-,-,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,Start"/>
<rom index="1">
<part>04</part>
<part>05</part>
</rom>
<rom index="0" zip="truxton.zip" md5="None">

2
Arcade_MiST/Toaplan v1 Hardware/meta/Vimana (Japan).mra
View File

@@ -30,7 +30,7 @@
<buttons names="Shot/Charging Shot,Bomb,Fast Scroll,Slow Scroll,P1 Start,P2 Start,Coin A,Coin B,Pause" default="A,B,X,Y,R,Start,Select,L"/>
<rom index="1">
<part>00</part>
<part>02</part>
</rom>
<rom index="0" zip="vimanaj.zip|vimana.zip" md5="None">

304
Arcade_MiST/Toaplan v1 Hardware/rtl/ToaplanV1.sv Normal file
View File

@@ -0,0 +1,304 @@
//============================================================================
// Toaplan Hardware v1 HW top-level for MiST
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module ToaplanV1(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
inout SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input SPI_SS4,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
`include "build_id.v"
// CoreMod Game
// 0 Demons World
// 1 Rally Bike
// 2 Vimana
// 3 Same! Same! Same!
// 4 Zerowing
// 5 Truxton
// 6 Out Zone
// 7 Out Zone Conversation
// 8 HellFire
assign LED = ~ioctl_downl;
assign SDRAM_CLK = clk_72;
assign SDRAM_CKE = 1;
localparam CONF_STR = {
"ToaplanV1", ";;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blending,Off,On;",
"O6,Joystick Swap,Off,On;",
"DIP;",
"T0,Reset;",
"V,v1.00.",`BUILD_DATE
};
wire rotate = status[2];
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
wire joyswap = status[6];
wire [7:0] dsw1 = status[23:16];
wire [7:0] dsw2 = status[31:24];
wire [7:0] dsw3 = status[39:32];
wire flipped;
wire key_service;// = m_fire1[4];
wire key_test;// = m_fire1[3];
wire key_tilt;
wire clk_72;
wire pll_locked;
pll_mist pll(
.inclk0(CLOCK_27),
.c0(clk_72),
.locked(pll_locked)
);
// reset generation
reg reset = 1;
reg rom_loaded = 0;
always @(posedge clk_72) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= status[0] | buttons[1] | ~rom_loaded | ioctl_downl;
end
// ARM connection
wire [63:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [31:0] joystick_0;
wire [31:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire no_csync;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
wire [6:0] core_mod;
user_io #(
.STRLEN($size(CONF_STR)>>3),
.ROM_DIRECT_UPLOAD(1))
user_io(
.clk_sys (clk_72 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.no_csync (no_csync ),
.core_mod (core_mod ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
data_io #(.ROM_DIRECT_UPLOAD(1)) data_io(
.clk_sys ( clk_72 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_SS4 ( SPI_SS4 ),
.SPI_DI ( SPI_DI ),
.SPI_DO ( SPI_DO ),
.ioctl_download( ioctl_downl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
wire [15:0] laudio, raudio;
wire hs, vs;
wire blankn = ~(hb | vb);
wire hb, vb;
wire [4:0] r,b,g;
ToaplanV1_Top ToaplanV1_Top(
.pll_locked ( pll_locked ),
.clk_sys ( clk_72 ),
.reset ( reset ),
.core_mod ( core_mod ),
.turbo_68k ( 0 ),//cpu_turbo
.pause_cpu ( 0 ),
// input scrollDBG,
.p1_right ( m_right1 ),
.p1_left ( m_left1 ),
.p1_down ( m_down1 ),
.p1_up ( m_up1 ),
.p1_buttons ( m_fire1[3:0] ),
.p2_right ( m_right2 ),
.p2_left ( m_left2 ),
.p2_down ( m_down2 ),
.p2_up ( m_up2 ),
.p2_buttons ( m_fire2[3:0] ),
.start1 ( m_one_player ),
.start2 ( m_two_players ),
.coin_a ( m_coin1 ),
.coin_b ( m_coin2 ),
.b_pause ( 0 ),
.service ( key_test ),
.key_tilt ( key_tilt ),
.key_service ( key_service ),
.sw0 ( dsw1 ),
.sw1 ( dsw2 ),
.sw2 ( dsw3 ),
.hblank ( hb ),
.vblank ( vb ),
.hsync ( hs ),
.vsync ( vs ),
.r ( r ),
.g ( g ),
.b ( b ),
.hs_offset (0),
.vs_offset (0),
.hs_width (0),
.vs_width (0),
.refresh_mod (0),
.ntsc (0),
.opl2_level (2'b00),
.audio_l ( laudio ),
.audio_r ( raudio ),
.ioctl_download( ioctl_downl),
.ioctl_index (ioctl_index),
.ioctl_addr ( ioctl_addr - 2'd2 ),//check
.ioctl_wr ( ioctl_wr ),
.ioctl_dout ( ioctl_dout ),
.SDRAM_A ( SDRAM_A ),
.SDRAM_BA ( SDRAM_BA ),
.SDRAM_DQ ( SDRAM_DQ ),
.SDRAM_DQML ( SDRAM_DQML ),
.SDRAM_DQMH ( SDRAM_DQMH ),
.SDRAM_nCS ( SDRAM_nCS ),
.SDRAM_nCAS ( SDRAM_nCAS ),
.SDRAM_nRAS ( SDRAM_nRAS ),
.SDRAM_nWE ( SDRAM_nWE )
);
mist_video #(.COLOR_DEPTH(5),.SD_HCNT_WIDTH(10)) mist_video(
.clk_sys(clk_72),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R(blankn ? r : 5'd0),
.G(blankn ? g : 5'd0),
.B(blankn ? b : 5'd0),
.HSync(~hs),
.VSync(~vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.no_csync(no_csync),
.rotate({~flipped,rotate}),
.ce_divider(3'd5), // pix clock = 72/6
.blend(blend),
.scandoubler_disable(scandoublerD),
.scanlines(scanlines),
.ypbpr(ypbpr)
);
dac #(16) dacl(
.clk_i(clk_72),
.res_n_i(1),
.dac_i({~laudio[15], laudio[14:0]}),
.dac_o(AUDIO_L)
);
dac #(16) dacr(
.clk_i(clk_72),
.res_n_i(1),
.dac_i({~raudio[15], raudio[14:0]}),
.dac_o(AUDIO_R)
);
// Common inputs
wire m_up1, m_down1, m_left1, m_right1, m_up1B, m_down1B, m_left1B, m_right1B;
wire m_up2, m_down2, m_left2, m_right2, m_up2B, m_down2B, m_left2B, m_right2B;
wire m_up3, m_down3, m_left3, m_right3, m_up3B, m_down3B, m_left3B, m_right3B;
wire m_up4, m_down4, m_left4, m_right4, m_up4B, m_down4B, m_left4B, m_right4B;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
wire [11:0] m_fire1, m_fire2, m_fire3, m_fire4;
arcade_inputs inputs (
.clk ( clk_72 ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.rotate ( rotate ),
.orientation ( {~flipped, 1'b0} ),
.joyswap ( joyswap ),
.oneplayer ( 1'b0 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_up1B, m_down1B, m_left1B, m_right1B, m_fire1, m_up1, m_down1, m_left1, m_right1} ),
.player2 ( {m_up2B, m_down2B, m_left2B, m_right2B, m_fire2, m_up2, m_down2, m_left2, m_right2} ),
.player3 ( {m_up3B, m_down3B, m_left3B, m_right3B, m_fire3, m_up3, m_down3, m_left3, m_right3} ),
.player4 ( {m_up4B, m_down4B, m_left4B, m_right4B, m_fire4, m_up4, m_down4, m_left4, m_right4} )
);
endmodule

1245
Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_zerowing/zerowing0.sv → Arcade_MiST/Toaplan v1 Hardware/rtl/ToaplanV1_Top.sv
View File

File diff suppressed because it is too large Load Diff

0
Arcade_MiST/Toaplan v1 Hardware/rtl/common/cache.v → Arcade_MiST/Toaplan v1 Hardware/rtl/cache.v
View File

117
Arcade_MiST/Toaplan v1 Hardware/rtl/chip_select.v Normal file
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@@ -0,0 +1,117 @@
//
module chip_select
(
input [23:0] cpu_a,
input cpu_as_n,
input [15:0] z80_addr,
input MREQ_n,
input IORQ_n,
// M68K selects
output prog_rom_cs,
output ram_cs,
output scroll_ofs_x_cs,
output scroll_ofs_y_cs,
output frame_done_cs,
output int_en_cs,
output crtc_cs,
output tile_ofs_cs,
output tile_attr_cs,
output tile_num_cs,
output scroll_cs,
output shared_ram_cs,
output vblank_cs,
output tile_palette_cs,
output bcu_flip_cs,
output sprite_palette_cs,
output sprite_ofs_cs,
output sprite_cs,
output sprite_size_cs,
output sprite_ram_cs,
output fcu_flip_cs,
output reset_z80_cs,
output dsp_ctrl_cs,
output dsp_addr_cs,
output dsp_r_cs,
output dsp_bio_cs,
// Z80 selects
output z80_p1_cs,
output z80_p2_cs,
output z80_dswa_cs,
output z80_dswb_cs,
output z80_system_cs,
output z80_tjump_cs,
output z80_sound0_cs,
output z80_sound1_cs,
// other params
output reg [15:0] scroll_y_offset
);
function m68k_cs;
input [23:0] start_address;
input [23:0] end_address;
begin
m68k_cs = ( cpu_a[23:0] >= start_address && cpu_a[23:0] <= end_address) & !cpu_as_n;
end
endfunction
function z80_cs;
input [7:0] address_lo;
begin
z80_cs = ( IORQ_n == 0 && z80_addr[7:0] == address_lo );
end
endfunction
always @ (*) begin
scroll_y_offset = 16;
prog_rom_cs = m68k_cs( 24'h000000, 24'h03ffff );
ram_cs = m68k_cs( 24'hc00000, 24'hc03fff );
scroll_ofs_x_cs = m68k_cs( 24'he00000, 24'he00001 );
scroll_ofs_y_cs = m68k_cs( 24'he00002, 24'he00003 );
fcu_flip_cs = m68k_cs( 24'he00006, 24'he00007 );
vblank_cs = m68k_cs( 24'h400000, 24'h400001 );
int_en_cs = m68k_cs( 24'h400002, 24'h400003 );
crtc_cs = m68k_cs( 24'h400008, 24'h40000f );
tile_palette_cs = m68k_cs( 24'h404000, 24'h4047ff );
sprite_palette_cs = m68k_cs( 24'h406000, 24'h4067ff );
shared_ram_cs = m68k_cs( 24'h600000, 24'h600fff );
bcu_flip_cs = m68k_cs( 24'h800000, 24'h800001 );
tile_ofs_cs = m68k_cs( 24'h800002, 24'h800003 );
tile_attr_cs = m68k_cs( 24'h800004, 24'h800005 );
tile_num_cs = m68k_cs( 24'h800006, 24'h800006 );
scroll_cs = m68k_cs( 24'h800010, 24'h80001f );
frame_done_cs = m68k_cs( 24'ha00000, 24'ha00001 );
sprite_ofs_cs = m68k_cs( 24'ha00002, 24'ha00003 );
sprite_cs = m68k_cs( 24'ha00004, 24'ha00005 );
sprite_size_cs = m68k_cs( 24'ha00006, 24'ha00007 );
reset_z80_cs = m68k_cs( 24'he00008, 24'he00009 );
//dsp_ctrl_cs = m68k_cs( 24'he0000a, 24'he0000b );
//dsp_addr_cs = m68k_cs( 4'h0 );
//dsp_r_cs = m68k_cs( 4'h1 );
//dsp_bio_cs = m68k_cs( 4'h3 );
z80_p1_cs = z80_cs( 8'h80 );
z80_p2_cs = z80_cs( 8'hc0 );
z80_dswa_cs = z80_cs( 8'he0 );
z80_dswb_cs = z80_cs( 8'ha0 );
z80_system_cs = z80_cs( 8'h60 );
z80_tjump_cs = z80_cs( 8'h20 );
z80_sound0_cs = z80_cs( 8'h00 );
z80_sound1_cs = z80_cs( 8'h01 );
end
endmodule

3
Arcade_MiST/Toaplan v1 Hardware/rtl/common/common.qip → Arcade_MiST/Toaplan v1 Hardware/rtl/common.qip
View File

@@ -12,3 +12,6 @@ set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) true_dual_
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtframe_fir_mono.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtframe_mixer.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) video_timing.v ]
set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) sdram.sv ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_mist.v ]

443
Arcade_MiST/Toaplan v1 Hardware/rtl/common/sdram.vhd
View File

@@ -1,443 +0,0 @@
-- __ __ __ __ __ __
-- /\ "-.\ \ /\ \/\ \ /\ \ /\ \
-- \ \ \-. \ \ \ \_\ \ \ \ \____ \ \ \____
-- \ \_\\"\_\ \ \_____\ \ \_____\ \ \_____\
-- \/_/ \/_/ \/_____/ \/_____/ \/_____/
-- ______ ______ __ ______ ______ ______
-- /\ __ \ /\ == \ /\ \ /\ ___\ /\ ___\ /\__ _\
-- \ \ \/\ \ \ \ __< _\_\ \ \ \ __\ \ \ \____ \/_/\ \/
-- \ \_____\ \ \_____\ /\_____\ \ \_____\ \ \_____\ \ \_\
-- \/_____/ \/_____/ \/_____/ \/_____/ \/_____/ \/_/
--
-- https://joshbassett.info
-- https://twitter.com/nullobject
-- https://github.com/nullobject
--
-- Copyright (c) 2020 Josh Bassett
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--use work.common.all;
use work.math.all;
-- This SDRAM controller provides a symmetric 32-bit synchronous read/write
-- interface for a 16Mx16-bit SDRAM chip (e.g. AS4C16M16SA-6TCN, IS42S16400F,
-- etc.).
entity sdram is
generic (
-- clock frequency (in MHz)
--
-- This value must be provided, as it is used to calculate the number of
-- clock cycles required for the other timing values.
CLK_FREQ : real;
-- 32-bit controller interface
ADDR_WIDTH : natural := 23;
DATA_WIDTH : natural := 32;
-- SDRAM interface
SDRAM_ADDR_WIDTH : natural := 13;
SDRAM_DATA_WIDTH : natural := 16;
SDRAM_COL_WIDTH : natural := 9;
SDRAM_ROW_WIDTH : natural := 13;
SDRAM_BANK_WIDTH : natural := 2;
-- The delay in clock cycles, between the start of a read command and the
-- availability of the output data.
CAS_LATENCY : natural := 2; -- 2=below 133MHz, 3=above 133MHz
-- The number of 16-bit words to be bursted during a read/write.
BURST_LENGTH : natural := 2;
-- timing values (in nanoseconds)
--
-- These values can be adjusted to match the exact timing of your SDRAM
-- chip (refer to the datasheet).
T_DESL : real := 200000.0; -- startup delay
T_MRD : real := 12.0; -- mode register cycle time
T_RC : real := 60.0; -- row cycle time
T_RCD : real := 18.0; -- RAS to CAS delay
T_RP : real := 18.0; -- precharge to activate delay
T_WR : real := 12.0; -- write recovery time
T_REFI : real := 7800.0 -- average refresh interval
);
port (
-- reset
reset : in std_logic := '0';
-- clock
clk : in std_logic;
-- address bus
addr : in unsigned(ADDR_WIDTH-1 downto 0);
-- input data bus
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
-- When the write enable signal is asserted, a write operation will be performed.
we : in std_logic;
-- When the request signal is asserted, an operation will be performed.
req : in std_logic;
-- The acknowledge signal is asserted by the SDRAM controller when
-- a request has been accepted.
ack : out std_logic;
-- The valid signal is asserted when there is a valid word on the output
-- data bus.
valid : out std_logic;
-- output data bus
q : out std_logic_vector(DATA_WIDTH-1 downto 0);
-- SDRAM interface (e.g. AS4C16M16SA-6TCN, IS42S16400F, etc.)
sdram_a : out unsigned(SDRAM_ADDR_WIDTH-1 downto 0);
sdram_ba : out unsigned(SDRAM_BANK_WIDTH-1 downto 0);
sdram_dq : inout std_logic_vector(SDRAM_DATA_WIDTH-1 downto 0);
sdram_cke : out std_logic;
sdram_cs_n : out std_logic;
sdram_ras_n : out std_logic;
sdram_cas_n : out std_logic;
sdram_we_n : out std_logic;
sdram_dqml : out std_logic;
sdram_dqmh : out std_logic
);
end sdram;
architecture arch of sdram is
subtype command_t is std_logic_vector(3 downto 0);
-- commands
constant CMD_DESELECT : command_t := "1---";
constant CMD_LOAD_MODE : command_t := "0000";
constant CMD_AUTO_REFRESH : command_t := "0001";
constant CMD_PRECHARGE : command_t := "0010";
constant CMD_ACTIVE : command_t := "0011";
constant CMD_WRITE : command_t := "0100";
constant CMD_READ : command_t := "0101";
constant CMD_STOP : command_t := "0110";
constant CMD_NOP : command_t := "0111";
-- the ordering of the accesses within a burst
constant BURST_TYPE : std_logic := '0'; -- 0=sequential, 1=interleaved
-- the write burst mode enables bursting for write operations
constant WRITE_BURST_MODE : std_logic := '0'; -- 0=burst, 1=single
-- the value written to the mode register to configure the memory
constant MODE_REG : unsigned(SDRAM_ADDR_WIDTH-1 downto 0) := (
"000" &
WRITE_BURST_MODE &
"00" &
to_unsigned(CAS_LATENCY, 3) &
BURST_TYPE &
to_unsigned(ilog2(BURST_LENGTH), 3)
);
-- calculate the clock period (in nanoseconds)
constant CLK_PERIOD : real := 1.0/CLK_FREQ*1000.0;
-- the number of clock cycles to wait before initialising the device
constant INIT_WAIT : natural := natural(ceil(T_DESL/CLK_PERIOD));
-- the number of clock cycles to wait while a LOAD MODE command is being
-- executed
constant LOAD_MODE_WAIT : natural := natural(ceil(T_MRD/CLK_PERIOD));
-- the number of clock cycles to wait while an ACTIVE command is being
-- executed
constant ACTIVE_WAIT : natural := natural(ceil(T_RCD/CLK_PERIOD));
-- the number of clock cycles to wait while a REFRESH command is being
-- executed
constant REFRESH_WAIT : natural := natural(ceil(T_RC/CLK_PERIOD));
-- the number of clock cycles to wait while a PRECHARGE command is being
-- executed
constant PRECHARGE_WAIT : natural := natural(ceil(T_RP/CLK_PERIOD));
-- the number of clock cycles to wait while a READ command is being executed
constant READ_WAIT : natural := CAS_LATENCY+BURST_LENGTH;
-- the number of clock cycles to wait while a WRITE command is being executed
constant WRITE_WAIT : natural := BURST_LENGTH+natural(ceil((T_WR+T_RP)/CLK_PERIOD));
-- the number of clock cycles before the memory controller needs to refresh
-- the SDRAM
constant REFRESH_INTERVAL : natural := natural(floor(T_REFI/CLK_PERIOD))-10;
type state_t is (INIT, MODE, IDLE, ACTIVE, READ, WRITE, REFRESH);
-- state signals
signal state, next_state : state_t;
-- command signals
signal cmd, next_cmd : command_t := CMD_NOP;
-- control signals
signal start : std_logic;
signal load_mode_done : std_logic;
signal active_done : std_logic;
signal refresh_done : std_logic;
signal first_word : std_logic;
signal read_done : std_logic;
signal write_done : std_logic;
signal should_refresh : std_logic;
-- counters
signal wait_counter : natural range 0 to 16383;
signal refresh_counter : natural range 0 to 1023;
-- registers
signal addr_reg : unsigned(SDRAM_COL_WIDTH+SDRAM_ROW_WIDTH+SDRAM_BANK_WIDTH-1 downto 0);
signal data_reg : std_logic_vector(DATA_WIDTH-1 downto 0);
signal we_reg : std_logic;
signal q_reg : std_logic_vector(DATA_WIDTH-1 downto 0);
-- aliases to decode the address register
alias col : unsigned(SDRAM_COL_WIDTH-1 downto 0) is addr_reg(SDRAM_COL_WIDTH-1 downto 0);
alias row : unsigned(SDRAM_ROW_WIDTH-1 downto 0) is addr_reg(SDRAM_COL_WIDTH+SDRAM_ROW_WIDTH-1 downto SDRAM_COL_WIDTH);
alias bank : unsigned(SDRAM_BANK_WIDTH-1 downto 0) is addr_reg(SDRAM_COL_WIDTH+SDRAM_ROW_WIDTH+SDRAM_BANK_WIDTH-1 downto SDRAM_COL_WIDTH+SDRAM_ROW_WIDTH);
begin
-- state machine
fsm : process (state, wait_counter, req, we_reg, load_mode_done, active_done, refresh_done, read_done, write_done, should_refresh)
begin
next_state <= state;
-- default to a NOP command
next_cmd <= CMD_NOP;
case state is
-- execute the initialisation sequence
when INIT =>
if wait_counter = 0 then
next_cmd <= CMD_DESELECT;
elsif wait_counter = INIT_WAIT-1 then
next_cmd <= CMD_PRECHARGE;
elsif wait_counter = INIT_WAIT+PRECHARGE_WAIT-1 then
next_cmd <= CMD_AUTO_REFRESH;
elsif wait_counter = INIT_WAIT+PRECHARGE_WAIT+REFRESH_WAIT-1 then
next_cmd <= CMD_AUTO_REFRESH;
elsif wait_counter = INIT_WAIT+PRECHARGE_WAIT+REFRESH_WAIT+REFRESH_WAIT-1 then
next_state <= MODE;
next_cmd <= CMD_LOAD_MODE;
end if;
-- load the mode register
when MODE =>
if load_mode_done = '1' then
next_state <= IDLE;
end if;
-- wait for a read/write request
when IDLE =>
if should_refresh = '1' then
next_state <= REFRESH;
next_cmd <= CMD_AUTO_REFRESH;
elsif req = '1' then
next_state <= ACTIVE;
next_cmd <= CMD_ACTIVE;
end if;
-- activate the row
when ACTIVE =>
if active_done = '1' then
if we_reg = '1' then
next_state <= WRITE;
next_cmd <= CMD_WRITE;
else
next_state <= READ;
next_cmd <= CMD_READ;
end if;
end if;
-- execute a read command
when READ =>
if read_done = '1' then
if should_refresh = '1' then
next_state <= REFRESH;
next_cmd <= CMD_AUTO_REFRESH;
elsif req = '1' then
next_state <= ACTIVE;
next_cmd <= CMD_ACTIVE;
else
next_state <= IDLE;
end if;
end if;
-- execute a write command
when WRITE =>
if write_done = '1' then
if should_refresh = '1' then
next_state <= REFRESH;
next_cmd <= CMD_AUTO_REFRESH;
elsif req = '1' then
next_state <= ACTIVE;
next_cmd <= CMD_ACTIVE;
else
next_state <= IDLE;
end if;
end if;
-- execute an auto refresh
when REFRESH =>
if refresh_done = '1' then
if req = '1' then
next_state <= ACTIVE;
next_cmd <= CMD_ACTIVE;
else
next_state <= IDLE;
end if;
end if;
end case;
end process;
-- latch the next state
latch_next_state : process (clk, reset)
begin
if reset = '1' then
state <= INIT;
cmd <= CMD_NOP;
elsif rising_edge(clk) then
state <= next_state;
cmd <= next_cmd;
end if;
end process;
-- the wait counter is used to hold the current state for a number of clock
-- cycles
update_wait_counter : process (clk, reset)
begin
if reset = '1' then
wait_counter <= 0;
elsif rising_edge(clk) then
if state /= next_state then -- state changing
wait_counter <= 0;
else
wait_counter <= wait_counter + 1;
end if;
end if;
end process;
-- the refresh counter is used to periodically trigger a refresh operation
update_refresh_counter : process (clk, reset)
begin
if reset = '1' then
refresh_counter <= 0;
elsif rising_edge(clk) then
if state = REFRESH and wait_counter = 0 then
refresh_counter <= 0;
else
refresh_counter <= refresh_counter + 1;
end if;
end if;
end process;
-- latch the rquest
latch_request : process (clk)
begin
if rising_edge(clk) then
if start = '1' then
-- we need to multiply the address by two, because we are converting
-- from a 32-bit controller address to a 16-bit SDRAM address
addr_reg <= shift_left(resize(addr, addr_reg'length), 1);
data_reg <= data;
we_reg <= we;
end if;
end if;
end process;
-- latch the output data as it's bursted from the SDRAM
latch_sdram_data : process (clk)
begin
if rising_edge(clk) then
valid <= '0';
if state = READ then
if first_word = '1' then
q_reg(31 downto 16) <= sdram_dq;
elsif read_done = '1' then
q_reg(15 downto 0) <= sdram_dq;
valid <= '1';
end if;
end if;
end if;
end process;
-- set wait signals
load_mode_done <= '1' when wait_counter = LOAD_MODE_WAIT-1 else '0';
active_done <= '1' when wait_counter = ACTIVE_WAIT-1 else '0';
refresh_done <= '1' when wait_counter = REFRESH_WAIT-1 else '0';
first_word <= '1' when wait_counter = CAS_LATENCY else '0';
read_done <= '1' when wait_counter = READ_WAIT-1 else '0';
write_done <= '1' when wait_counter = WRITE_WAIT-1 else '0';
-- the SDRAM should be refreshed when the refresh interval has elapsed
should_refresh <= '1' when refresh_counter >= REFRESH_INTERVAL-1 else '0';
-- a new request is only allowed at the end of the IDLE, READ, WRITE, and
-- REFRESH states
start <= '1' when (state = IDLE) or
(state = READ and read_done = '1') or
(state = WRITE and write_done = '1') or
(state = REFRESH and refresh_done = '1') else '0';
-- assert the acknowledge signal at the beginning of the ACTIVE state
ack <= '1' when state = ACTIVE and wait_counter = 0 else '0';
-- set output data
q <= q_reg;
-- deassert the clock enable at the beginning of the INIT state
sdram_cke <= '0' when state = INIT and wait_counter = 0 else '1';
-- set SDRAM control signals
(sdram_cs_n, sdram_ras_n, sdram_cas_n, sdram_we_n) <= cmd;
-- set SDRAM bank
with state select
sdram_ba <=
bank when ACTIVE,
bank when READ,
bank when WRITE,
(others => '0') when others;
-- set SDRAM address
with state select
sdram_a <=
"0010000000000" when INIT,
MODE_REG when MODE,
row when ACTIVE,
"0010" & col when READ, -- auto precharge
"0010" & col when WRITE, -- auto precharge
(others => '0') when others;
-- decode the next 16-bit word from the write buffer
sdram_dq <= data_reg((BURST_LENGTH-wait_counter)*SDRAM_DATA_WIDTH-1 downto (BURST_LENGTH-wait_counter-1)*SDRAM_DATA_WIDTH) when state = WRITE else (others => 'Z');
-- set SDRAM data mask
sdram_dqmh <= '0';
sdram_dqml <= '0';
end architecture arch;

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Arcade_MiST/Toaplan v1 Hardware/rtl/rtl_demonsworld/demonwld.sv
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////============================================================================
////
//// This program is free software; you can redistribute it and/or modify it
//// under the terms of the GNU General Public License as published by the Free
//// Software Foundation; either version 2 of the License, or (at your option)
//// any later version.
////
//// This program is distributed in the hope that it will be useful, but WITHOUT
//// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
//// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
//// more details.
////
//// You should have received a copy of the GNU General Public License along
//// with this program; if not, write to the Free Software Foundation, Inc.,
//// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
////
////============================================================================
//
//`default_nettype none
//
//module emu
//(
// //Master input clock
// input CLK_50M,
//
// //Async reset from top-level module.
// //Can be used as initial reset.
// input RESET,
//
// //Must be passed to hps_io module
// inout [48:0] HPS_BUS,
//
// //Base video clock. Usually equals to CLK_SYS.
// output CLK_VIDEO,
//
// //Multiple resolutions are supported using different CE_PIXEL rates.
// //Must be based on CLK_VIDEO
// output CE_PIXEL,
//
// //Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
// //if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
// output [12:0] VIDEO_ARX,
// output [12:0] VIDEO_ARY,
//
// output [7:0] VGA_R,
// output [7:0] VGA_G,
// output [7:0] VGA_B,
// output VGA_HS,
// output VGA_VS,
// output VGA_DE, // = ~(VBlank | HBlank)
// output VGA_F1,
// output [2:0] VGA_SL,
// output VGA_SCALER, // Force VGA scaler
//
// input [11:0] HDMI_WIDTH,
// input [11:0] HDMI_HEIGHT,
// output HDMI_FREEZE,
//
//`ifdef MISTER_FB
// // Use framebuffer in DDRAM (USE_FB=1 in qsf)
// // FB_FORMAT:
// // [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
// // [3] : 0=16bits 565 1=16bits 1555
// // [4] : 0=RGB 1=BGR (for 16/24/32 modes)
// //
// // FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
// output FB_EN,
// output [4:0] FB_FORMAT,
// output [11:0] FB_WIDTH,
// output [11:0] FB_HEIGHT,
// output [31:0] FB_BASE,
// output [13:0] FB_STRIDE,
// input FB_VBL,
// input FB_LL,
// output FB_FORCE_BLANK,
//
//`ifdef MISTER_FB_PALETTE
// // Palette control for 8bit modes.
// // Ignored for other video modes.
// output FB_PAL_CLK,
// output [7:0] FB_PAL_ADDR,
// output [23:0] FB_PAL_DOUT,
// input [23:0] FB_PAL_DIN,
// output FB_PAL_WR,
//`endif
//`endif
//
// output LED_USER, // 1 - ON, 0 - OFF.
//
// // b[1]: 0 - LED status is system status OR'd with b[0]
// // 1 - LED status is controled solely by b[0]
// // hint: supply 2'b00 to let the system control the LED.
// output [1:0] LED_POWER,
// output [1:0] LED_DISK,
//
// // I/O board button press simulation (active high)
// // b[1]: user button
// // b[0]: osd button
// output [1:0] BUTTONS,
//
// //Audio
// input CLK_AUDIO, // 24.576 MHz
// output [15:0] AUDIO_L,
// output [15:0] AUDIO_R,
// output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
// output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
//
// //ADC
// inout [3:0] ADC_BUS,
//
// //SD-SPI
// output SD_SCK,
// output SD_MOSI,
// input SD_MISO,
// output SD_CS,
// input SD_CD,
//
// //High latency DDR3 RAM interface
// //Use for non-critical time purposes
// output DDRAM_CLK,
// input DDRAM_BUSY,
// output [7:0] DDRAM_BURSTCNT,
// output [28:0] DDRAM_ADDR,
// input [63:0] DDRAM_DOUT,
// input DDRAM_DOUT_READY,
// output DDRAM_RD,
// output [63:0] DDRAM_DIN,
// output [7:0] DDRAM_BE,
// output DDRAM_WE,
//
// //SDRAM interface with lower latency
// output SDRAM_CLK,
// output SDRAM_CKE,
// output [12:0] SDRAM_A,
// output [1:0] SDRAM_BA,
// inout [15:0] SDRAM_DQ,
// output SDRAM_DQML,
// output SDRAM_DQMH,
// output SDRAM_nCS,
// output SDRAM_nCAS,
// output SDRAM_nRAS,
// output SDRAM_nWE,
//
//`ifdef MISTER_DUAL_SDRAM
// //Secondary SDRAM
// //Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
// input SDRAM2_EN,
// output SDRAM2_CLK,
// output [12:0] SDRAM2_A,
// output [1:0] SDRAM2_BA,
// inout [15:0] SDRAM2_DQ,
// output SDRAM2_nCS,
// output SDRAM2_nCAS,
// output SDRAM2_nRAS,
// output SDRAM2_nWE,
//`endif
//
// input UART_CTS,
// output UART_RTS,
// input UART_RXD,
// output UART_TXD,
// output UART_DTR,
// input UART_DSR,
//
//`ifdef MISTER_ENABLE_YC
// output [39:0] CHROMA_PHASE_INC,
// output YC_EN,
// output PALFLAG,
//`endif
//
// // Open-drain User port.
// // 0 - D+/RX
// // 1 - D-/TX
// // 2..6 - USR2..USR6
// // Set USER_OUT to 1 to read from USER_IN.
// input [6:0] USER_IN,
// output [6:0] USER_OUT,
//
// input OSD_STATUS
//);
//
/////////// Default values for ports not used in this core /////////
//
//assign ADC_BUS = 'Z;
//assign USER_OUT = 0;
//assign {UART_RTS, UART_TXD, UART_DTR} = 0;
//assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
////assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
////assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0;
//assign VGA_F1 = 0;
//assign VGA_SCALER = 0;
//assign HDMI_FREEZE = 0;
//
//assign AUDIO_MIX = 0;
//assign LED_USER = ioctl_download & cpu_a[0] & & tms_addr & & tms_dout & & tms_rom_addr & & tms_rom_dout ;
//assign LED_DISK = 0;
//assign LED_POWER = 0;
//assign BUTTONS = 0;
//
//// Status Bit Map:
//// Upper Case Lower Case
//// 0 1 2 3 4 5 6
//// 01234567890123456789012345678901 23456789012345678901234567890123
//// 0123456789ABCDEFGHIJKLMNOPQRSTUV 0123456789ABCDEFGHIJKLMNOPQRSTUV
//// X XXXXXXXX X XXXX XXXXXXXX X X XX XXXXXXXX
//
//wire [1:0] aspect_ratio = status[9:8];
//wire orientation = ~status[3];
//wire [2:0] scan_lines = status[6:4];
//reg refresh_mod;
//reg new_vmode;
//
//always @(posedge clk_sys) begin
// if (refresh_mod != status[19]) begin
// refresh_mod <= status[19];
// new_vmode <= ~new_vmode;
// end
//end
//
//wire [3:0] hs_offset = status[27:24];
//wire [3:0] vs_offset = status[31:28];
//wire [3:0] hs_width = status[59:56];
//wire [3:0] vs_width = status[63:60];
//
//assign VIDEO_ARX = (!aspect_ratio) ? (orientation ? 8'd4 : 8'd3) : (aspect_ratio - 1'd1);
//assign VIDEO_ARY = (!aspect_ratio) ? (orientation ? 8'd3 : 8'd4) : 12'd0;
//
//`include "build_id.v"
//localparam CONF_STR = {
// "Toaplan V1;;",
// "-;",
// "P1,Video Settings;",
// "P1-;",
// "P1O89,Aspect Ratio,Original,Full Screen,[ARC1],[ARC2];",
// "P1O3,Orientation,Horz,Vert;",
// "P1-;",
// "P1O46,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%,CRT 100%;",
// "P1OA,Force Scandoubler,Off,On;",
// "P1-;",
// "P1O7,Video Mode,NTSC,PAL;",
// "P1OM,Video Signal,RGBS/YPbPr,Y/C;",
// "P1OJ,Refresh Rate,Native,NTSC;",
// "P1-;",
// "P1OOR,H-sync Pos Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;",
// "P1OSV,V-sync Pos Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;",
// "P1-;",
// "P1oOR,H-sync Width Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;",
// "P1oSV,V-sync Width Adj,0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1;",
// "P1-;",
// "P2,Audio Settings;",
// "P2-;",
// "P2oBC,OPL2 Volume,Default,50%,25%,0%;",
// "P2-;",
// "-;",
// "P3,Core Options;",
// "P3-;",
// "P3o6,Swap P1/P2 Joystick,Off,On;",
// "P3-;",
// "P3OF,68k Freq.,10Mhz,17.5MHz;",
// "P3-;",
// "P3o0,Scroll Debug,Off,On;",
// "P3-;",
// "DIP;",
// "-;",
// "OK,Pause OSD,Off,When Open;",
// "OL,Dim Video,Off,10s;",
// "-;",
// "R0,Reset;",
// "V,v",`BUILD_DATE
//};
//
//wire hps_forced_scandoubler;
//wire forced_scandoubler = hps_forced_scandoubler | status[10];
//
//wire [1:0] buttons;
//wire [63:0] status;
//wire [10:0] ps2_key;
//wire [15:0] joy0, joy1;
//
//hps_io #(.CONF_STR(CONF_STR)) hps_io
//(
// .clk_sys(clk_sys),
// .HPS_BUS(HPS_BUS),
//
// .buttons(buttons),
// .ps2_key(ps2_key),
// .status(status),
// .status_menumask(direct_video),
// .forced_scandoubler(hps_forced_scandoubler),
// .gamma_bus(gamma_bus),
// .new_vmode(new_vmode),
// .direct_video(direct_video),
// .video_rotated(video_rotated),
//
// .ioctl_download(ioctl_download),
// .ioctl_upload(ioctl_upload),
// .ioctl_wr(ioctl_wr),
// .ioctl_addr(ioctl_addr),
// .ioctl_dout(ioctl_dout),
// .ioctl_din(ioctl_din),
// .ioctl_index(ioctl_index),
// .ioctl_wait(ioctl_wait),
//
// .joystick_0(joy0),
// .joystick_1(joy1)
//);
//
//// INPUT
//
//// 8 dip switches of 8 bits
//reg [7:0] sw[8];
//always @(posedge clk_sys) begin
// if (ioctl_wr && (ioctl_index==254) && !ioctl_addr[24:3]) begin
// sw[ioctl_addr[2:0]] <= ioctl_dout;
// end
//end
//
//wire direct_video;
//
//wire ioctl_download;
//wire ioctl_upload;
//wire ioctl_upload_req;
//wire ioctl_wait;
//wire ioctl_wr;
//wire [15:0] ioctl_index;
//wire [26:0] ioctl_addr;
//wire [15:0] ioctl_dout;
//wire [15:0] ioctl_din;
//
//wire tile_priority_type;
//wire [15:0] scroll_y_offset;
//
//wire [21:0] gamma_bus;
//
////<buttons names="Fire,Jump,Start,Coin,Pause" default="A,B,R,L,Start" />
//// Inputs tied to z80_din
//reg [7:0] p1;
//reg [7:0] p2;
//reg [7:0] z80_dswa;
//reg [7:0] z80_dswb;
//reg [7:0] z80_tjump;
//reg [7:0] system;
//
//always @ (posedge clk_sys ) begin
// p1 <= { 1'b0, p1_buttons[2:0], p1_right, p1_left, p1_down, p1_up };
// p2 <= { 1'b0, p2_buttons[2:0], p2_right, p2_left, p2_down, p2_up };
// z80_dswa <= sw[0];
// z80_dswb <= sw[1];
// z80_tjump <= sw[2];
//
// if ( status[32] == 1 ) begin
// system <= { vbl, start2 | p1_buttons[3], start1 | p1_buttons[3], coin_b, coin_a, service | status[32], key_tilt, key_service };
// end else begin
// system <= { vbl, start2, start1, coin_b, coin_a, service, key_tilt, key_service };
// end
//end
//
//reg p1_swap;
//
//reg p1_right;
//reg p1_left;
//reg p1_down;
//reg p1_up;
//reg [3:0] p1_buttons;
//
//reg p2_right;
//reg p2_left;
//reg p2_down;
//reg p2_up;
//reg [3:0] p2_buttons;
//
//reg start1;
//reg start2;
//reg coin_a;
//reg coin_b;
//reg b_pause;
//reg service;
//
//always @ * begin
// p1_swap <= status[38];
//
// if ( status[38] == 0 ) begin
// p1_right <= joy0[0] | key_p1_right;
// p1_left <= joy0[1] | key_p1_left;
// p1_down <= joy0[2] | key_p1_down;
// p1_up <= joy0[3] | key_p1_up;
// p1_buttons <= joy0[7:4] | {key_p1_c, key_p1_b, key_p1_a};
//
// p2_right <= joy1[0] | key_p2_right;
// p2_left <= joy1[1] | key_p2_left;
// p2_down <= joy1[2] | key_p2_down;
// p2_up <= joy1[3] | key_p2_up;
// p2_buttons <= joy1[7:4] | {key_p2_c, key_p2_b, key_p2_a};
// end else begin
// p2_right <= joy0[0] | key_p1_right;
// p2_left <= joy0[1] | key_p1_left;
// p2_down <= joy0[2] | key_p1_down;
// p2_up <= joy0[3] | key_p1_up;
// p2_buttons <= joy0[7:4] | {key_p1_c, key_p1_b, key_p1_a};
//
// p1_right <= joy1[0] | key_p2_right;
// p1_left <= joy1[1] | key_p2_left;
// p1_down <= joy1[2] | key_p2_down;
// p1_up <= joy1[3] | key_p2_up;
// p1_buttons <= joy1[7:4] | {key_p2_c, key_p2_b, key_p2_a};
// end
//end
//
//always @ * begin
// start1 <= joy0[8] | joy1[8] | key_start_1p;
// start2 <= joy0[9] | joy1[9] | key_start_2p;
//
// coin_a <= joy0[10] | joy1[10] | key_coin_a;
// coin_b <= joy0[11] | joy1[11] | key_coin_b;
//
// b_pause <= joy0[12] | key_pause;
// service <= key_test;
//end
//
//// Keyboard handler
//
//reg key_start_1p, key_start_2p, key_coin_a, key_coin_b;
//reg key_tilt, key_test, key_reset, key_service, key_pause;
//
//reg key_p1_up, key_p1_left, key_p1_down, key_p1_right, key_p1_a, key_p1_b, key_p1_c;
//reg key_p2_up, key_p2_left, key_p2_down, key_p2_right, key_p2_a, key_p2_b, key_p2_c;
//
//wire pressed = ps2_key[9];
//
//always @(posedge clk_sys) begin
// reg old_state;
// old_state <= ps2_key[10];
// if ( old_state ^ ps2_key[10] ) begin
// casex ( ps2_key[8:0] )
// 'h016 : key_start_1p <= pressed; // 1
// 'h01E : key_start_2p <= pressed; // 2
// 'h02E : key_coin_a <= pressed; // 5
// 'h036 : key_coin_b <= pressed; // 6
// 'h006 : key_test <= key_test ^ pressed; // f2
// 'h004 : key_reset <= pressed; // f3
// 'h046 : key_service <= pressed; // 9
// 'h02C : key_tilt <= pressed; // t
// 'h04D : key_pause <= pressed; // p
//
// 'h175 : key_p1_up <= pressed; // up
// 'h172 : key_p1_down <= pressed; // down
// 'h16B : key_p1_left <= pressed; // left
// 'h174 : key_p1_right <= pressed; // right
// 'h014 : key_p1_a <= pressed; // lctrl
// 'h011 : key_p1_b <= pressed; // lalt
// 'h029 : key_p1_c <= pressed; // spacebar
//
// 'h02D : key_p2_up <= pressed; // r
// 'h02B : key_p2_down <= pressed; // f
// 'h023 : key_p2_left <= pressed; // d
// 'h034 : key_p2_right <= pressed; // g
// 'h01C : key_p2_a <= pressed; // a
// 'h01B : key_p2_b <= pressed; // s
// 'h015 : key_p2_c <= pressed; // q
// endcase
// end
//end
//
//
//
//
//
//
//
//endmodule

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