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78 lines
2.3 KiB
Verilog
78 lines
2.3 KiB
Verilog
/* This file is part of JTOPL.
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JTOPL program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JTOPL program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JTOPL. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 17-6-2020
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*/
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module jtopl_csr #(
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parameter LEN=18, W=34, OPL_TYPE=1
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) ( // Circular Shift Register + input mux
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input rst,
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input clk,
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input cen,
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input [ 7:0] din,
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output [W-1:0] shift_out,
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input up_mult,
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input up_ksl_tl,
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input up_ar_dr,
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input up_sl_rr,
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input up_wav,
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input update_op_I,
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input update_op_II,
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input update_op_IV
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);
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wire [W-1:0] regop_in;
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jtopl_sh_rst #(.width(W),.stages(LEN)) u_regch(
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.clk ( clk ),
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.cen ( cen ),
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.rst ( rst ),
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.din ( regop_in ),
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.drop ( shift_out )
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);
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wire up_mult_I = up_mult & update_op_I;
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wire up_mult_II = up_mult & update_op_II;
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wire up_mult_IV = up_mult & update_op_IV;
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wire up_ksl_tl_IV = up_ksl_tl & update_op_IV;
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wire up_ar_dr_op = up_ar_dr & update_op_I;
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wire up_sl_rr_op = up_sl_rr & update_op_I;
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wire up_wav_I = up_wav & update_op_I;
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assign regop_in[31:0] = { // 4 bytes:
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up_mult_IV ? din[7] : shift_out[31], // AM enable
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up_mult_I ? din[6:5] : shift_out[30:29], // Vib enable, EG type, KSR
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up_mult_II ? din[4:0] : shift_out[28:24], // KSR + Mult
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up_ksl_tl_IV? din : shift_out[23:16], // KSL + TL
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up_ar_dr_op ? din : shift_out[15: 8],
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up_sl_rr_op ? din : shift_out[ 7: 0]
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};
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generate if (OPL_TYPE == 2) begin
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assign regop_in[33:32] = up_wav_I ? din[1:0] : shift_out[33:32];
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end
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endgenerate
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endmodule // jtopl_reg
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