Uploaded_4_12_2023
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MicroCoreLabs
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@ -1,15 +1,15 @@
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//
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// File Name : MDA_Video_core_v1_0.v
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// Used on :
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// Author : Ted Fried
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// Creation : 4/10/2023
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// Code Type : Synthesizable
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// File Name : MDA_Video_core_v1_0.v
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// Used on :
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// Author : Ted Fried
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// Creation : 4/10/2023
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// Code Type : Synthesizable
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//
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// Description:
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// ============
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//
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// This AXI slave reads an image held in dul ported RAM and
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// sends it out to an MDA Display
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// Description:
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// ============
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//
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// This AXI slave reads an image held in dul ported RAM and
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// sends it out to an MDA Display
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//
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//------------------------------------------------------------------------
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//
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@ -23,17 +23,17 @@
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//------------------------------------------------------------------------
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//
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// Copyright (c) 2023 Ted Fried
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//
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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//
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// The above copyright notice and this permission notice shall be included in all
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// copies or substantial portions of the Software.
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//
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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@ -48,94 +48,94 @@
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`timescale 1 ns / 1 ps
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module MDA_Video_core_v1_0 #
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module MDA_Video_core_v1_0 #
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(
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// Users to add parameters here
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// User parameters ends
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// Do not modify the parameters beyond this line
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// Parameters of Axi Slave Bus Interface S00_AXI
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parameter integer C_S00_AXI_DATA_WIDTH = 32,
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parameter integer C_S00_AXI_ADDR_WIDTH = 4,
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// Parameters of Axi Master Bus Interface M00_AXI
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parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
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parameter integer C_M00_AXI_BURST_LEN = 4,
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parameter integer C_M00_AXI_ID_WIDTH = 1,
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parameter integer C_M00_AXI_ADDR_WIDTH = 32,
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parameter integer C_M00_AXI_DATA_WIDTH = 32,
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parameter integer C_M00_AXI_AWUSER_WIDTH = 0,
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parameter integer C_M00_AXI_ARUSER_WIDTH = 0,
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parameter integer C_M00_AXI_WUSER_WIDTH = 0,
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parameter integer C_M00_AXI_RUSER_WIDTH = 0,
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parameter integer C_M00_AXI_BUSER_WIDTH = 0
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)
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(
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// Users to add parameters here
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// AXI Slave Interface
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// ------------------------------------------------------------------------------------
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input wire s00_axi_aclk, // Clock and Reset
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input wire s00_axi_aresetn,
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// User parameters ends
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// Do not modify the parameters beyond this line
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input wire [31:0] s00_axi_awaddr, // Write Address Channel
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input wire s00_axi_awvalid,
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output wire s00_axi_awready,
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input wire [31:0] s00_axi_wdata, // Write Data Channel
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input wire [3:0] s00_axi_wstrb,
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input wire s00_axi_wvalid,
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output wire s00_axi_wready,
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output wire [1:0] s00_axi_bresp, // Write Response Channel
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output wire s00_axi_bvalid,
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input wire s00_axi_bready,
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input wire [31:0] s00_axi_araddr, // Read Address Channel
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input wire s00_axi_arvalid,
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output wire s00_axi_arready,
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output wire [31:0] s00_axi_rdata, // Read Data Channel
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output wire [1:0] s00_axi_rresp,
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output wire s00_axi_rvalid,
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input wire s00_axi_rready,
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input wire [2:0] s00_axi_awprot, // AXI Protection
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input wire [2:0] s00_axi_arprot,
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// MDA Video display signals
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// ------------------------------------------------------------------------------------
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output MDA_HSYNC,
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output MDA_VSYNC,
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output MDA_DATA,
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output MDA_INTENSITY
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// Parameters of Axi Slave Bus Interface S00_AXI
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parameter integer C_S00_AXI_DATA_WIDTH = 32,
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parameter integer C_S00_AXI_ADDR_WIDTH = 4,
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// Parameters of Axi Master Bus Interface M00_AXI
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parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
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parameter integer C_M00_AXI_BURST_LEN = 4,
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parameter integer C_M00_AXI_ID_WIDTH = 1,
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parameter integer C_M00_AXI_ADDR_WIDTH = 32,
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parameter integer C_M00_AXI_DATA_WIDTH = 32,
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parameter integer C_M00_AXI_AWUSER_WIDTH = 0,
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parameter integer C_M00_AXI_ARUSER_WIDTH = 0,
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parameter integer C_M00_AXI_WUSER_WIDTH = 0,
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parameter integer C_M00_AXI_RUSER_WIDTH = 0,
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parameter integer C_M00_AXI_BUSER_WIDTH = 0
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)
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(
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// AXI Slave Interface
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// ------------------------------------------------------------------------------------
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input wire s00_axi_aclk, // Clock and Reset
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input wire s00_axi_aresetn,
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input wire [31:0] s00_axi_awaddr, // Write Address Channel
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input wire s00_axi_awvalid,
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output wire s00_axi_awready,
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input wire [31:0] s00_axi_wdata, // Write Data Channel
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input wire [3:0] s00_axi_wstrb,
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input wire s00_axi_wvalid,
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output wire s00_axi_wready,
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output wire [1:0] s00_axi_bresp, // Write Response Channel
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output wire s00_axi_bvalid,
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input wire s00_axi_bready,
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input wire [31:0] s00_axi_araddr, // Read Address Channel
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input wire s00_axi_arvalid,
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output wire s00_axi_arready,
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output wire [31:0] s00_axi_rdata, // Read Data Channel
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output wire [1:0] s00_axi_rresp,
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output wire s00_axi_rvalid,
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input wire s00_axi_rready,
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input wire [2:0] s00_axi_awprot, // AXI Protection
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input wire [2:0] s00_axi_arprot,
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// MDA Video display signals
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// ------------------------------------------------------------------------------------
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output MDA_HSYNC,
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output MDA_VSYNC,
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output MDA_DATA,
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output MDA_INTENSITY
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);
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);
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// Internal Signals
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//------------------------------------------------------------------------
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reg s00_axi_bvalid_int = 'h0;
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reg s00_axi_rvalid_int = 'h0;
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reg s00_axi_awready_int = 'h0;
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reg s00_axi_wready_int = 'h0;
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reg mda_hsync_int = 'h0;
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reg mda_vsync_int = 'h0;
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reg mda_data_int = 'h0;
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reg mda_intensity_int = 'h0;
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reg dpram_a_wr = 'h0;
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reg mda_shifter_load = 'h0;
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reg s00_axi_bvalid_int = 'h0;
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reg s00_axi_rvalid_int = 'h0;
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reg s00_axi_awready_int = 'h0;
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reg s00_axi_wready_int = 'h0;
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reg mda_hsync_int = 'h0;
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reg mda_vsync_int = 'h0;
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reg mda_data_int = 'h0;
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reg mda_intensity_int = 'h0;
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reg dpram_a_wr = 'h0;
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reg mda_shifter_load = 'h0;
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reg [31:0] s00_axi_rdata_int;
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reg [8:0] dpram_a_addr = 'h0;
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reg [719:0] dpram_a_data = 'h0;
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reg [8:0] dpram_b_addr = 'h0;
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reg [719:0] mda_shift_out = 'h0;
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reg [15:0] mda_bit_counter = 'h0;
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reg [31:0] s00_axi_rdata_int;
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reg [8:0] dpram_a_addr = 'h0;
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reg [719:0] dpram_a_data = 'h0;
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reg [8:0] dpram_b_addr = 'h0;
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reg [719:0] mda_shift_out = 'h0;
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reg [15:0] mda_bit_counter = 'h0;
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wire mda_clock;
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@ -150,19 +150,19 @@ wire [719:0] dpram_b_data;
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//------------------------------------------------------------------------
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// AXI Slave Controller signals
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assign s00_axi_awready = s00_axi_awready_int;
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assign s00_axi_arready = 1'b1;
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assign s00_axi_wready = s00_axi_wready_int;
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assign s00_axi_bresp = 2'b00;
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assign s00_axi_rresp = 2'b00;
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assign s00_axi_bvalid = s00_axi_bvalid_int;
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assign s00_axi_rvalid = s00_axi_rvalid_int;
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assign s00_axi_rdata = s00_axi_rdata_int;
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assign s00_axi_awready = s00_axi_awready_int;
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assign s00_axi_arready = 1'b1;
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assign s00_axi_wready = s00_axi_wready_int;
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assign s00_axi_bresp = 2'b00;
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assign s00_axi_rresp = 2'b00;
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assign s00_axi_bvalid = s00_axi_bvalid_int;
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assign s00_axi_rvalid = s00_axi_rvalid_int;
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assign s00_axi_rdata = s00_axi_rdata_int;
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assign MDA_HSYNC = mda_hsync_int;
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assign MDA_VSYNC = mda_vsync_int;
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assign MDA_DATA = mda_shift_out[719];
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assign MDA_HSYNC = mda_hsync_int;
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assign MDA_VSYNC = mda_vsync_int;
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assign MDA_DATA = mda_shift_out[719];
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assign MDA_INTENSITY = mda_intensity_int;
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@ -177,111 +177,111 @@ always @(posedge s00_axi_aclk)
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begin : AXI_SLAVE_CONTROLLER
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// For AXI Writes, the write data can come before the write address.
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// We will enforce that the address and data arrive simultaneously.
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// For AXI Writes, the write data can come before the write address.
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// We will enforce that the address and data arrive simultaneously.
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if (s00_axi_aresetn==1'b0)
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begin
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s00_axi_awready_int <= 1'b0;
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s00_axi_wready_int <= 1'b0;
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s00_axi_bvalid_int <= 1'b0;
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s00_axi_rvalid_int <= 1'b0;
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end
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if (s00_axi_aresetn==1'b0)
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begin
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s00_axi_awready_int <= 1'b0;
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s00_axi_wready_int <= 1'b0;
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s00_axi_bvalid_int <= 1'b0;
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s00_axi_rvalid_int <= 1'b0;
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end
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else
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begin
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else
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begin
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// AXI Write Controller
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//
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// Accept write data only when the address and data are available from the host
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// Assert the write response as soon as data is received
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//
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if (s00_axi_awvalid==1'b1 && s00_axi_wvalid==1'b1)
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begin
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s00_axi_awready_int <= 1'b1;
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s00_axi_wready_int <= 1'b1;
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s00_axi_bvalid_int <= 1'b1; // Assert write response
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// AXI Write Controller
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//
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// Accept write data only when the address and data are available from the host
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// Assert the write response as soon as data is received
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//
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if (s00_axi_awvalid==1'b1 && s00_axi_wvalid==1'b1)
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begin
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s00_axi_awready_int <= 1'b1;
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s00_axi_wready_int <= 1'b1;
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s00_axi_bvalid_int <= 1'b1; // Assert write response
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// Debounce the write address and data ready signals
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//
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if (s00_axi_awready_int==1'b1)
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begin
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s00_axi_awready_int <= 1'b0;
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s00_axi_wready_int <= 1'b0;
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end
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// Debounce the write response when the host is ready
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//
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if (s00_axi_bvalid_int==1'b1 && s00_axi_bready==1'b1)
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begin
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s00_axi_bvalid_int <= 1'b0;
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case (s00_axi_awaddr[7:0])
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8'h10 : dpram_a_data[31:0] <= s00_axi_wdata[31:0];
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8'h14 : dpram_a_data[63:32] <= s00_axi_wdata[31:0];
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8'h18 : dpram_a_data[95:64] <= s00_axi_wdata[31:0];
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8'h1C : dpram_a_data[127:96] <= s00_axi_wdata[31:0];
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// Debounce the write address and data ready signals
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//
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if (s00_axi_awready_int==1'b1)
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begin
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s00_axi_awready_int <= 1'b0;
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s00_axi_wready_int <= 1'b0;
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end
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// Debounce the write response when the host is ready
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//
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if (s00_axi_bvalid_int==1'b1 && s00_axi_bready==1'b1)
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begin
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s00_axi_bvalid_int <= 1'b0;
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case (s00_axi_awaddr[7:0])
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8'h10 : dpram_a_data[31:0] <= s00_axi_wdata[31:0];
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8'h14 : dpram_a_data[63:32] <= s00_axi_wdata[31:0];
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8'h18 : dpram_a_data[95:64] <= s00_axi_wdata[31:0];
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8'h1C : dpram_a_data[127:96] <= s00_axi_wdata[31:0];
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8'h20 : dpram_a_data[159:128] <= s00_axi_wdata[31:0];
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8'h24 : dpram_a_data[191:160] <= s00_axi_wdata[31:0];
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8'h28 : dpram_a_data[223:192] <= s00_axi_wdata[31:0];
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8'h2C : dpram_a_data[255:224] <= s00_axi_wdata[31:0];
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8'h20 : dpram_a_data[159:128] <= s00_axi_wdata[31:0];
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8'h24 : dpram_a_data[191:160] <= s00_axi_wdata[31:0];
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8'h28 : dpram_a_data[223:192] <= s00_axi_wdata[31:0];
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8'h2C : dpram_a_data[255:224] <= s00_axi_wdata[31:0];
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8'h30 : dpram_a_data[287:256] <= s00_axi_wdata[31:0];
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8'h34 : dpram_a_data[319:288] <= s00_axi_wdata[31:0];
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8'h38 : dpram_a_data[351:320] <= s00_axi_wdata[31:0];
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8'h3C : dpram_a_data[383:352] <= s00_axi_wdata[31:0];
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8'h30 : dpram_a_data[287:256] <= s00_axi_wdata[31:0];
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8'h34 : dpram_a_data[319:288] <= s00_axi_wdata[31:0];
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8'h38 : dpram_a_data[351:320] <= s00_axi_wdata[31:0];
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8'h3C : dpram_a_data[383:352] <= s00_axi_wdata[31:0];
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8'h40 : dpram_a_data[415:384] <= s00_axi_wdata[31:0];
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8'h44 : dpram_a_data[447:416] <= s00_axi_wdata[31:0];
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8'h48 : dpram_a_data[479:448] <= s00_axi_wdata[31:0];
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8'h4C : dpram_a_data[511:480] <= s00_axi_wdata[31:0];
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8'h40 : dpram_a_data[415:384] <= s00_axi_wdata[31:0];
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8'h44 : dpram_a_data[447:416] <= s00_axi_wdata[31:0];
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8'h48 : dpram_a_data[479:448] <= s00_axi_wdata[31:0];
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8'h4C : dpram_a_data[511:480] <= s00_axi_wdata[31:0];
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8'h50 : dpram_a_data[543:512] <= s00_axi_wdata[31:0];
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8'h54 : dpram_a_data[575:544] <= s00_axi_wdata[31:0];
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8'h58 : dpram_a_data[607:576] <= s00_axi_wdata[31:0];
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8'h5C : dpram_a_data[639:608] <= s00_axi_wdata[31:0];
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8'h50 : dpram_a_data[543:512] <= s00_axi_wdata[31:0];
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8'h54 : dpram_a_data[575:544] <= s00_axi_wdata[31:0];
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8'h58 : dpram_a_data[607:576] <= s00_axi_wdata[31:0];
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8'h5C : dpram_a_data[639:608] <= s00_axi_wdata[31:0];
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8'h60 : dpram_a_data[671:640] <= s00_axi_wdata[31:0];
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8'h64 : dpram_a_data[703:672] <= s00_axi_wdata[31:0];
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8'h68 : dpram_a_data[719:704] <= s00_axi_wdata[15:0];
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8'h70 : dpram_a_addr <= s00_axi_wdata[8:0];
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8'h74 : dpram_a_wr <= s00_axi_wdata[0];
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8'h60 : dpram_a_data[671:640] <= s00_axi_wdata[31:0];
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8'h64 : dpram_a_data[703:672] <= s00_axi_wdata[31:0];
|
||||
8'h68 : dpram_a_data[719:704] <= s00_axi_wdata[15:0];
|
||||
|
||||
8'h70 : dpram_a_addr <= s00_axi_wdata[8:0];
|
||||
8'h74 : dpram_a_wr <= s00_axi_wdata[0];
|
||||
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// AXI Read Controller
|
||||
//
|
||||
if (s00_axi_arvalid==1'b1)
|
||||
begin
|
||||
s00_axi_rvalid_int <= 1'b1; // Assert read response
|
||||
|
||||
case (s00_axi_araddr[8:0])
|
||||
9'h000: s00_axi_rdata_int <= 32'hDEAD_BEEF; // FPGA_ID
|
||||
9'h004: s00_axi_rdata_int <= 32'h0000_0088; // FPGA Version
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// AXI Read Controller
|
||||
//
|
||||
if (s00_axi_arvalid==1'b1)
|
||||
begin
|
||||
s00_axi_rvalid_int <= 1'b1; // Assert read response
|
||||
|
||||
case (s00_axi_araddr[8:0])
|
||||
9'h000: s00_axi_rdata_int <= 32'hDEAD_BEEF; // FPGA_ID
|
||||
9'h004: s00_axi_rdata_int <= 32'h0000_0088; // FPGA Version
|
||||
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
|
||||
// Debounce Read Response
|
||||
//
|
||||
if (s00_axi_rvalid_int==1'b1 && s00_axi_rready==1'b1)
|
||||
begin
|
||||
s00_axi_rvalid_int <= 1'b0;
|
||||
end
|
||||
// Debounce Read Response
|
||||
//
|
||||
if (s00_axi_rvalid_int==1'b1 && s00_axi_rready==1'b1)
|
||||
begin
|
||||
s00_axi_rvalid_int <= 1'b0;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
@ -292,10 +292,10 @@ end
|
||||
//
|
||||
//------------------------------------------------------------------------
|
||||
|
||||
MDA_DCM i_MDA_DCM (
|
||||
.clk_in1 (s00_axi_aclk),
|
||||
.clk_out1 (mda_clock)
|
||||
);
|
||||
MDA_DCM i_MDA_DCM (
|
||||
.clk_in1 (s00_axi_aclk),
|
||||
.clk_out1 (mda_clock)
|
||||
);
|
||||
|
||||
|
||||
//------------------------------------------------------------------------
|
||||
@ -304,15 +304,15 @@ MDA_DCM i_MDA_DCM (
|
||||
//
|
||||
//------------------------------------------------------------------------
|
||||
|
||||
MDA_VIDEO_DPRAM i_MDA_VIDEO_DPRAM (
|
||||
.clka (s00_axi_aclk),
|
||||
.wea (dpram_a_wr),
|
||||
.addra (dpram_a_addr),
|
||||
.dina (dpram_a_data),
|
||||
MDA_VIDEO_DPRAM i_MDA_VIDEO_DPRAM (
|
||||
.clka (s00_axi_aclk),
|
||||
.wea (dpram_a_wr),
|
||||
.addra (dpram_a_addr),
|
||||
.dina (dpram_a_data),
|
||||
|
||||
.clkb (mda_clock),
|
||||
.addrb (dpram_b_addr),
|
||||
.doutb (dpram_b_data)
|
||||
.clkb (mda_clock),
|
||||
.addrb (dpram_b_addr),
|
||||
.doutb (dpram_b_data)
|
||||
);
|
||||
|
||||
|
||||
@ -327,31 +327,31 @@ always @(posedge mda_clock)
|
||||
begin : MDA_CONTROLLER
|
||||
|
||||
|
||||
// Shift out a video row
|
||||
//
|
||||
if (mda_shifter_load==1'b1) mda_shift_out <= dpram_b_data[719:0];
|
||||
else mda_shift_out <= { mda_shift_out[718:0] , 1'b0 };
|
||||
|
||||
|
||||
mda_bit_counter <= mda_bit_counter + 1'b1;
|
||||
case (mda_bit_counter)
|
||||
|
||||
'd000 : mda_shifter_load <= 1'b1; // Load DPRAM contents into shift register
|
||||
'd001 : mda_shifter_load <= 1'b0; // Debounce shift register loader
|
||||
'd002 : dpram_b_addr <= dpram_b_addr + 1'b1; // Advance to the next DPRAM row
|
||||
|
||||
'd731 : mda_hsync_int <= 1'b1; // 720 clocks for active video and another 10 clocks, then assert HSYNC
|
||||
'd866 : mda_hsync_int <= 1'b0; // 135 clocks for HSYNC active
|
||||
|
||||
'd883 : begin
|
||||
mda_bit_counter <= 'd0; // Return to the beginning of this state machine
|
||||
if (dpram_b_addr=='d349) mda_vsync_int <= 1'b0; // 17 clocks after HSYNC de-asserted, then check to start VSYNC at end of 350 lines
|
||||
if (dpram_b_addr=='d365) mda_vsync_int <= 1'b1; // De-assert VSYNC after 16 lines
|
||||
if (dpram_b_addr=='d369) dpram_b_addr <= 'h0; // After four lines of nothing, return to the beginning of the video DPRAM
|
||||
end
|
||||
|
||||
default: ;
|
||||
endcase
|
||||
// Shift out a video row
|
||||
//
|
||||
if (mda_shifter_load==1'b1) mda_shift_out <= dpram_b_data[719:0];
|
||||
else mda_shift_out <= { mda_shift_out[718:0] , 1'b0 };
|
||||
|
||||
|
||||
mda_bit_counter <= mda_bit_counter + 1'b1;
|
||||
case (mda_bit_counter)
|
||||
|
||||
'd000 : mda_shifter_load <= 1'b1; // Load DPRAM contents into shift register
|
||||
'd001 : mda_shifter_load <= 1'b0; // Debounce shift register loader
|
||||
'd002 : dpram_b_addr <= dpram_b_addr + 1'b1; // Advance to the next DPRAM row
|
||||
|
||||
'd731 : mda_hsync_int <= 1'b1; // 720 clocks for active video and another 10 clocks, then assert HSYNC
|
||||
'd866 : mda_hsync_int <= 1'b0; // 135 clocks for HSYNC active
|
||||
|
||||
'd883 : begin
|
||||
mda_bit_counter <= 'd0; // Return to the beginning of this state machine
|
||||
if (dpram_b_addr=='d349) mda_vsync_int <= 1'b0; // 17 clocks after HSYNC de-asserted, then check to start VSYNC at end of 350 lines
|
||||
if (dpram_b_addr=='d365) mda_vsync_int <= 1'b1; // De-assert VSYNC after 16 lines
|
||||
if (dpram_b_addr=='d369) dpram_b_addr <= 'h0; // After four lines of nothing, return to the beginning of the video DPRAM
|
||||
end
|
||||
|
||||
default: ;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user