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Uploaded_11_26_2024

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Ted Fried 2024-11-26 10:46:21 -08:00
parent 693d05b755
commit 2dad183f53
1 changed files with 180 additions and 164 deletions
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344
XTMax/Code/XTMax/XTMax.ino
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@ -1,7 +1,7 @@
//
//
// File Name : XTMax.ino
// Used on :
// Used on :
// Author : Ted Fried, MicroCore Labs
// Creation : 9/7/2024
//
@ -24,24 +24,27 @@
// Revision 3 10/11/2024
// Added variable wait states for Expanded RAM
// - For 4.77 Mhz, can be changed to zero wait states for Write cycles and two for Read cycles
//
//
// Revision 4 11/11/2024
// - Updated MicroSD support and conventional memory to 640 KB
//
// Revision 5 11/26/2024
// - XTMsx automatically configured addition to conventional memory to 640 KB
//
//------------------------------------------------------------------------
//
// Copyright (c) 2024 Ted Fried
//
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
@ -51,7 +54,7 @@
// SOFTWARE.
//
//------------------------------------------------------------------------
#include <stdint.h>
@ -60,22 +63,22 @@
// Teensy 4.1 pin assignments
//
#define PIN_BCLK 34
#define PIN_BALE 5
#define PIN_AEN 29
#define PIN_CHRDY_OE_n 28
#define PIN_CHRDY_OUT 6
#define PIN_REFRESH 32
#define PIN_MEMWR_n 33
#define PIN_MEMRD_n 4
#define PIN_IOWR_n 3
#define PIN_IORD_n 2
#define PIN_BCLK 34
#define PIN_BALE 5
#define PIN_AEN 29
#define PIN_CHRDY_OE_n 28
#define PIN_CHRDY_OUT 6
#define PIN_REFRESH 32
#define PIN_MEMWR_n 33
#define PIN_MEMRD_n 4
#define PIN_IOWR_n 3
#define PIN_IORD_n 2
#define PIN_MUX_DATA_n 31
#define PIN_DATA_OE_n 30
#define PIN_MUX_ADDR_n 9
#define PIN_TRIG_OUT 35
#define PIN_MUX_DATA_n 31
#define PIN_DATA_OE_n 30
#define PIN_MUX_ADDR_n 9
#define PIN_TRIG_OUT 35
#define PIN_ADDR19 27
#define PIN_ADDR18 26
#define PIN_ADDR17 39
@ -94,13 +97,13 @@
#define PIN_AD4 19
#define PIN_AD3 25
#define PIN_AD2 24
#define PIN_AD1 0
#define PIN_AD0 1
#define PIN_AD1 0
#define PIN_AD0 1
#define PIN_DOUT7 37
#define PIN_DOUT6 36
#define PIN_DOUT5 7
#define PIN_DOUT4 8
#define PIN_DOUT5 7
#define PIN_DOUT4 8
#define PIN_DOUT3 13
#define PIN_DOUT2 11 // temp spi_mosi
#define PIN_DOUT1 12 // temp spi_cs
@ -127,7 +130,7 @@
#define DATA_OE_n_LOW 0x0
#define DATA_OE_n_HIGH 0x00800000
#define TRIG_OUT_LOW 0x0
#define TRIG_OUT_HIGH 0x10000000
@ -146,18 +149,8 @@
#define PSRAM_RESET_VALUE 0x01000000
#define PSRAM_CLK_HIGH 0x02000000
// XTMax extends expanded memory after motherboard installed RAM.
// Set to:
// 0x10000 when motherboard contains 64 KB
// 0x20000 when motherboard contains 128 KB
// 0x40000 when motherboard contains 256 KB
// 0x80000 when motherboard contains 512 KB
#define EXPANDED_RAM_BASE_ADDRESS 0x40000
// --------------------------------------------------------------------------------------------------
// --------------------------------------------------------------------------------------------------
@ -188,7 +181,7 @@ uint8_t sd_spi_datain =0;
uint32_t sd_spi_cs_n = 0x0;
uint32_t sd_spi_dataout =0;
uint8_t XTMax_MEM_Response_Array[16];
DMAMEM uint8_t internal_RAM1[0x60000];
uint8_t internal_RAM2[0x40000];
@ -201,22 +194,22 @@ DMAMEM uint8_t internal_RAM1[0x60000];
//
void setup() {
pinMode(PIN_BCLK, INPUT);
pinMode(PIN_BCLK, INPUT);
pinMode(PIN_BALE, INPUT);
pinMode(PIN_AEN, INPUT);
pinMode(PIN_AEN, INPUT);
pinMode(PIN_CHRDY_OE_n, OUTPUT);
pinMode(PIN_CHRDY_OUT, OUTPUT);
pinMode(PIN_REFRESH, INPUT);
pinMode(PIN_REFRESH, INPUT);
pinMode(PIN_MEMWR_n, INPUT);
pinMode(PIN_MEMRD_n, INPUT);
pinMode(PIN_IOWR_n, INPUT);
pinMode(PIN_IORD_n, INPUT);
pinMode(PIN_MUX_DATA_n, OUTPUT);
pinMode(PIN_DATA_OE_n, OUTPUT);
pinMode(PIN_MUX_DATA_n, OUTPUT);
pinMode(PIN_DATA_OE_n, OUTPUT);
pinMode(PIN_MUX_ADDR_n, OUTPUT);
pinMode(PIN_TRIG_OUT, OUTPUT);
pinMode(PIN_ADDR19, INPUT);
pinMode(PIN_ADDR18, INPUT);
pinMode(PIN_ADDR17, INPUT);
@ -237,7 +230,7 @@ void setup() {
pinMode(PIN_AD2, INPUT);
pinMode(PIN_AD1, INPUT);
pinMode(PIN_AD0, INPUT);
pinMode(PIN_DOUT7, OUTPUT);
pinMode(PIN_DOUT6, OUTPUT);
pinMode(PIN_DOUT5, OUTPUT);
@ -246,15 +239,15 @@ void setup() {
pinMode(PIN_DOUT2, OUTPUT);
pinMode(PIN_DOUT1, OUTPUT);
pinMode(PIN_DOUT0, OUTPUT);
pinMode(PIN_PSRAM_CLK, OUTPUT);
pinMode(PIN_PSRAM_CS_n, OUTPUT);
pinMode(PIN_PSRAM_D3, INPUT);
pinMode(PIN_PSRAM_D3, INPUT);
pinMode(PIN_PSRAM_D2, INPUT);
pinMode(PIN_PSRAM_D1, INPUT);
pinMode(PIN_PSRAM_D0, OUTPUT);
pinMode(PIN_SD_CLK, OUTPUT);
pinMode(PIN_SD_CS_n, OUTPUT);
pinMode(PIN_SD_MOSI, OUTPUT);
@ -262,18 +255,18 @@ void setup() {
GPIO9_DR = PSRAM_RESET_VALUE; // Set CLK=0, CS_n=1, DATA=0
digitalWriteFast(PIN_CHRDY_OE_n, 0x1);
digitalWriteFast(PIN_CHRDY_OUT, 0x0);
digitalWriteFast(PIN_DATA_OE_n, 0x1);
digitalWriteFast(PIN_MUX_ADDR_n, 0x0);
digitalWriteFast(PIN_MUX_DATA_n, 0x1);
digitalWriteFast(PIN_TRIG_OUT, 0x1);
//noInterrupts(); // Disable Teensy interupts
//Serial.begin(9600);
}
@ -283,14 +276,14 @@ void setup() {
// --------------------------------------------------------------------------------------------------
inline void SD_SPI_TXRXBit() {
// Drive CLK low and MOSI
//
GPIO7_DR = GPIO7_DR & 0xE0000000; // Trigger out
sd_pin_outputs = (sd_spi_cs_n<<17) | (0x0<<13) | databit_out; // SD_CS_n - SD_CLK - SD_MOSI
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_LOW + DATA_OE_n_HIGH;
delayNanoseconds(10);
// Drive CLK high
//
GPIO7_DR = GPIO7_DR | 0x10000000; // Trigger out
@ -304,7 +297,7 @@ inline void SD_SPI_TXRXBit() {
//
sd_pin_outputs = (sd_spi_cs_n<<17) | (0x0<<13) | 0x0; // SD_CS_n - SD_CLK - SD_MOSI
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_LOW + DATA_OE_n_HIGH;
return;
}
@ -312,7 +305,7 @@ inline void SD_SPI_TXRXBit() {
// --------------------------------------------------------------------------------------------------
inline void SD_SPI_Cycle() {
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_LOW + DATA_OE_n_HIGH ; // Assert CHRDY_n=0 to begin wait states
databit_out = ((sd_spi_dataout&0x80)<<5 ); SD_SPI_TXRXBit(); // Bit 7
@ -334,12 +327,12 @@ inline void SD_SPI_Cycle() {
// --------------------------------------------------------------------------------------------------
inline void PSRAM_Write_Clk_Cycle() {
GPIO9_DR = (nibble_out&0xF) << 26; // Drive nibble data , CLK=0 , CS_n=0
delayNanoseconds(1);
GPIO9_DR = (nibble_out<<26) | PSRAM_CLK_HIGH; // Drive nibble data and CLK=1
delayNanoseconds(1);
return;
}
@ -347,13 +340,13 @@ inline void PSRAM_Write_Clk_Cycle() {
// --------------------------------------------------------------------------------------------------
inline void PSRAM_Read_Clk_Cycle() {
GPIO9_DR = 0x0; // Drive CLK=0 , CS_n=0
delayNanoseconds(1);
GPIO9_DR = PSRAM_CLK_HIGH; // Drive CLK=1
delayNanoseconds(1);
nibble_in = (GPIO9_DR>>26) & 0xF; // Sample nibble data
nibble_in = (GPIO9_DR>>26) & 0xF; // Sample nibble data
return;
}
@ -366,21 +359,21 @@ inline void PSRAM_Configure() {
delayMicroseconds(200);
nibble_out = 0x0; PSRAM_Write_Clk_Cycle(); // Set PSRAM to Quad Mode 0x35
nibble_out = 0x0; PSRAM_Write_Clk_Cycle();
nibble_out = 0x1; PSRAM_Write_Clk_Cycle();
nibble_out = 0x1; PSRAM_Write_Clk_Cycle();
nibble_out = 0x0; PSRAM_Write_Clk_Cycle();
nibble_out = 0x1; PSRAM_Write_Clk_Cycle();
nibble_out = 0x0; PSRAM_Write_Clk_Cycle();
nibble_out = 0x1; PSRAM_Write_Clk_Cycle();
nibble_out = 0x0; PSRAM_Write_Clk_Cycle();
nibble_out = 0x1; PSRAM_Write_Clk_Cycle();
nibble_out = 0x1; PSRAM_Write_Clk_Cycle();
nibble_out = 0x0; PSRAM_Write_Clk_Cycle();
nibble_out = 0x1; PSRAM_Write_Clk_Cycle();
nibble_out = 0x0; PSRAM_Write_Clk_Cycle();
nibble_out = 0x1; PSRAM_Write_Clk_Cycle();
GPIO9_DR = PSRAM_RESET_VALUE; // Drive CLK=0 , CS_n=1
GPIO9_GDIR = 0x3F000000; // Change Data[3:0] to outputs quickly
return;
}
@ -391,8 +384,8 @@ inline uint8_t PSRAM_Read(uint32_t address_in) {
// Send Command = Quad Read = 0x0B
//
nibble_out = 0x0; PSRAM_Write_Clk_Cycle();
nibble_out = 0xB; PSRAM_Write_Clk_Cycle();
nibble_out = 0x0; PSRAM_Write_Clk_Cycle();
nibble_out = 0xB; PSRAM_Write_Clk_Cycle();
// Send 24-bit address in four clock cycles
@ -406,14 +399,14 @@ inline uint8_t PSRAM_Read(uint32_t address_in) {
//GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_LOW; // De-assert CHRDY early for 4.77 Mhz
// Four clocks of hi-Z - Make PSRAM Data signals hi-Z during this time
//
GPIO9_GDIR = 0x03000000; // Change Data[3:0] to inputs quickly
PSRAM_Write_Clk_Cycle();
GPIO9_GDIR = 0x03000000; // Change Data[3:0] to inputs quickly
PSRAM_Write_Clk_Cycle();
PSRAM_Write_Clk_Cycle();
PSRAM_Write_Clk_Cycle();
PSRAM_Write_Clk_Cycle();
PSRAM_Write_Clk_Cycle();
// Clock in the data
@ -437,8 +430,8 @@ inline uint8_t PSRAM_Write(uint32_t address_in , int8_t local_data) {
// Send Command = Quad Write = 0x02
//
nibble_out = 0x0; PSRAM_Write_Clk_Cycle();
nibble_out = 0x2; PSRAM_Write_Clk_Cycle();
nibble_out = 0x0; PSRAM_Write_Clk_Cycle();
nibble_out = 0x2; PSRAM_Write_Clk_Cycle();
// Send 24-bit address in four clock cycles
@ -452,7 +445,7 @@ inline uint8_t PSRAM_Write(uint32_t address_in , int8_t local_data) {
//GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_LOW; // De-assert CHRDY early for 4.77 Mhz
// Send byte data in twp clock cycles
//
nibble_out = local_data >> 4; PSRAM_Write_Clk_Cycle();
@ -469,18 +462,18 @@ return read_byte;
inline uint8_t Internal_RAM_Read() {
uint8_t local_temp;
if (isa_address<0x60000) local_temp = internal_RAM1[isa_address];
else local_temp = internal_RAM2[isa_address-0x60000];
return local_temp;
}
inline void Internal_RAM_Write() {
if (isa_address<0x60000) internal_RAM1[isa_address] = 0xFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
else internal_RAM2[isa_address-0x60000] = 0xFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
return;
}
@ -488,40 +481,71 @@ inline void Internal_RAM_Write() {
// --------------------------------------------------------------------------------------------------
inline void Mem_Read_Cycle() {
isa_address = ADDRESS_DATA_GPIO6_UNSCRAMBLE;
if ( (isa_address>=0xE0000) && (isa_address<0xF0000) ) { // Expanded RAM page frame
page_base_address = (isa_address & 0xFC000);
if (page_base_address == 0xEC000) { psram_address = (reg_0x263<<14) | (isa_address & 0x03FFF); }
else if (page_base_address == 0xE8000) { psram_address = (reg_0x262<<14) | (isa_address & 0x03FFF); }
else if (page_base_address == 0xE4000) { psram_address = (reg_0x261<<14) | (isa_address & 0x03FFF); }
else if (page_base_address == 0xE0000) { psram_address = (reg_0x260<<14) | (isa_address & 0x03FFF); }
GPIO7_DR = MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_LOW + DATA_OE_n_LOW ; // Assert CHRDY_n=0 to begin wait states
isa_data_out = PSRAM_Read(psram_address);
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out; // Output data
isa_data_out = PSRAM_Read(psram_address);
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out; // Output data
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_LOW; // De-assert CHRDY
while ( (gpio9_int&0xF0) != 0xF0 ) { gpio9_int = GPIO9_DR; } // Wait here until cycle is complete
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
}
else if ( (isa_address>=EXPANDED_RAM_BASE_ADDRESS) && (isa_address<0xA0000) ) { // Expanded RAM
/*
XTMax_MEM_Response_Array
- Array holds value 0,1,2
0 = unitiailzed - add wait states and snoop
1 = No wait states and no response
2 = No wait states and yes respond
*/
else if (isa_address<0xA0000) { // "Conventional" RAM
isa_data_out = Internal_RAM_Read();
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_LOW;
// If XTMax has not seen a read access to this 64 KB page yet, add wait states to give physical RAM (if present) a chance to respond
//
if (XTMax_MEM_Response_Array[(isa_address>>16)] == 2) {
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_LOW; // Physical RAM is NOT present at this page so XTMax will respond
}
else if (XTMax_MEM_Response_Array[(isa_address>>16)] == 0) {
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_LOW + DATA_OE_n_HIGH ; // Assert CHRDY_n=0 to begin wait states
delayNanoseconds(800);
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH; // De-assert CHRDY
gpio6_int = GPIO6_DR; // Read the data bus value currently on the ISA bus
data_in = 0xFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
if (data_in == isa_data_out) {
XTMax_MEM_Response_Array[(isa_address>>16)] = 1; // Physical RAM is present at this page so XTMax should not respond
}
else {
XTMax_MEM_Response_Array[(isa_address>>16)] = 2;
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_LOW; // Physical RAM is NOT present at this page so XTMax will respond
}
}
while ( (gpio9_int&0xF0) != 0xF0 ) { gpio9_int = GPIO9_DR; } // Wait here until cycle is complete
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
}
return;
@ -532,50 +556,50 @@ inline void Mem_Read_Cycle() {
// --------------------------------------------------------------------------------------------------
inline void Mem_Write_Cycle() {
isa_address = ADDRESS_DATA_GPIO6_UNSCRAMBLE;
if ( (isa_address>=0xE0000) && (isa_address<0xF0000) ) { // Expanded RAM page frame
page_base_address = (isa_address & 0xFC000);
if (page_base_address == 0xEC000) { psram_address = (reg_0x263<<14) | (isa_address & 0x03FFF); }
else if (page_base_address == 0xE8000) { psram_address = (reg_0x262<<14) | (isa_address & 0x03FFF); }
else if (page_base_address == 0xE4000) { psram_address = (reg_0x261<<14) | (isa_address & 0x03FFF); }
else if (page_base_address == 0xE0000) { psram_address = (reg_0x260<<14) | (isa_address & 0x03FFF); }
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_HIGH + CHRDY_OUT_LOW + trigger_out;
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_LOW + CHRDY_OE_n_LOW + DATA_OE_n_HIGH; // Steer data mux to Data[7:0] and Assert CHRDY_n=0 to begin wait states
delayNanoseconds(10); // Wait some time for buffers to switch from address to data
gpio6_int = GPIO6_DR;
data_in = 0xFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
PSRAM_Write(psram_address , data_in);
PSRAM_Write(psram_address , data_in);
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_LOW + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH; // De-assert CHRDY
while ( (gpio9_int&0xF0) != 0xF0 ) { // Wait here until cycle is complete
gpio6_int = GPIO6_DR;
gpio9_int = GPIO9_DR;
}
gpio9_int = GPIO9_DR;
}
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
}
else if ( (isa_address>=EXPANDED_RAM_BASE_ADDRESS) && (isa_address<0xA0000) ) { // Expanded RAM
else if (isa_address<0xA0000) { // XTMax stores the full 640 KB conventional memory
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_HIGH + CHRDY_OUT_LOW + trigger_out;
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_LOW + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
while ( (gpio9_int&0xF0) != 0xF0 ) { // Wait here until cycle is complete
gpio6_int = GPIO6_DR;
gpio9_int = GPIO9_DR;
}
gpio9_int = GPIO9_DR;
}
Internal_RAM_Write();
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
}
@ -588,64 +612,64 @@ inline void Mem_Write_Cycle() {
// --------------------------------------------------------------------------------------------------
inline void IO_Read_Cycle() {
isa_address = 0xFFFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
if ((isa_address&0x0FFC)==0x260 ) { // Location of 16 KB Expanded Memory page frame pointers
switch (isa_address) {
case 0x260: isa_data_out = reg_0x260; break;
case 0x261: isa_data_out = reg_0x261; break;
case 0x262: isa_data_out = reg_0x262; break;
case 0x263: isa_data_out = reg_0x263; break;
}
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_LOW;
while ( (gpio9_int&0xF0) != 0xF0 ) { gpio9_int = GPIO9_DR; } // Wait here until cycle is complete
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
}
else if ((isa_address&0x0FF8)==0x378 ) { // Location of Parallel Port
switch (isa_address) {
case 0x378: sd_spi_dataout = 0xff; SD_SPI_Cycle(); isa_data_out = sd_spi_datain; break;
}
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_LOW;
while ( (gpio9_int&0xF0) != 0xF0 ) { gpio9_int = GPIO9_DR; } // Wait here until cycle is complete
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
}
return;
}
// --------------------------------------------------------------------------------------------------
// --------------------------------------------------------------------------------------------------
inline void IO_Write_Cycle() {
isa_address = 0xFFFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
if ((isa_address&0x0FFC)==0x260 ) { // Location of 16 KB Expanded Memory page frame pointers
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_HIGH + CHRDY_OUT_LOW + trigger_out;
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_LOW + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
while ( (gpio9_int&0xF0) != 0xF0 ) { // Wait here until cycle is complete
gpio6_int = GPIO6_DR;
gpio9_int = GPIO9_DR;
}
gpio6_int = GPIO6_DR;
gpio9_int = GPIO9_DR;
}
data_in = 0xFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
switch (isa_address) {
case 0x260: reg_0x260 = data_in; break;
case 0x261: reg_0x261 = data_in; break;
@ -656,29 +680,29 @@ inline void IO_Write_Cycle() {
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
}
else if ((isa_address&0x0FF8)==0x378 ) { // Location of Parallel Port
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_HIGH + CHRDY_OUT_LOW + trigger_out;
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_LOW + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
delayNanoseconds(50); // Give some time for write data to be available after IOWR_n goes low
gpio6_int = GPIO6_DR;
data_in = 0xFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
switch (isa_address) {
case 0x378: sd_spi_dataout = data_in; SD_SPI_Cycle(); break;
case 0x379: sd_spi_cs_n = data_in&0x1; break;
}
//gpio9_int = GPIO9_DR;
while ( (gpio9_int&0xF0) != 0xF0 ) { // Wait here until cycle is complete
gpio6_int = GPIO6_DR;
gpio9_int = GPIO9_DR;
}
gpio6_int = GPIO6_DR;
gpio9_int = GPIO9_DR;
}
sd_pin_outputs = (sd_spi_cs_n<<17); // SD_CS_n - SD_CLK - SD_MOSI
//trigger_out = ((lpt_data&0x1)<<28); // SD_MOSI
//trigger_out = ((lpt_data&0x2)<<27); // SD_CLK
//trigger_out = ((lpt_data&0x4)<<26); // SD_CS_n
@ -686,12 +710,12 @@ inline void IO_Write_Cycle() {
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
}
return;
}
// -------------------------------------------------
//
// Main loop
@ -707,21 +731,13 @@ void loop() {
PSRAM_Configure();
while (1) {
gpio6_int = GPIO6_DR;
gpio9_int = GPIO9_DR;
if ((gpio9_int&0x80000010)==0) IO_Read_Cycle(); // Isolate and check AEN and IO Rd/Wr
else if ((gpio9_int&0x80000020)==0) IO_Write_Cycle();
else if ((gpio9_int&0x00000040)==0) Mem_Read_Cycle();
else if ((gpio9_int&0x00000080)==0) Mem_Write_Cycle();
}
}
}
}