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Uploaded_11_26_2024

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Ted Fried
2024-11-26 10:46:21 -08:00
parent 693d05b755
commit 2dad183f53
1 changed files with 180 additions and 164 deletions
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60
XTMax/Code/XTMax/XTMax.ino
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@@ -28,6 +28,9 @@
// Revision 4 11/11/2024
// - Updated MicroSD support and conventional memory to 640 KB
//
// Revision 5 11/26/2024
// - XTMsx automatically configured addition to conventional memory to 640 KB
//
//------------------------------------------------------------------------
//
// Copyright (c) 2024 Ted Fried
@@ -147,16 +150,6 @@
#define PSRAM_CLK_HIGH 0x02000000
// XTMax extends expanded memory after motherboard installed RAM.
// Set to:
// 0x10000 when motherboard contains 64 KB
// 0x20000 when motherboard contains 128 KB
// 0x40000 when motherboard contains 256 KB
// 0x80000 when motherboard contains 512 KB
#define EXPANDED_RAM_BASE_ADDRESS 0x40000
// --------------------------------------------------------------------------------------------------
// --------------------------------------------------------------------------------------------------
@@ -188,7 +181,7 @@ uint8_t sd_spi_datain =0;
uint32_t sd_spi_cs_n = 0x0;
uint32_t sd_spi_dataout =0;
uint8_t XTMax_MEM_Response_Array[16];
DMAMEM uint8_t internal_RAM1[0x60000];
uint8_t internal_RAM2[0x40000];
@@ -515,10 +508,41 @@ inline void Mem_Read_Cycle() {
}
else if ( (isa_address>=EXPANDED_RAM_BASE_ADDRESS) && (isa_address<0xA0000) ) { // Expanded RAM
/*
XTMax_MEM_Response_Array
- Array holds value 0,1,2
0 = unitiailzed - add wait states and snoop
1 = No wait states and no response
2 = No wait states and yes respond
*/
else if (isa_address<0xA0000) { // "Conventional" RAM
isa_data_out = Internal_RAM_Read();
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_LOW;
// If XTMax has not seen a read access to this 64 KB page yet, add wait states to give physical RAM (if present) a chance to respond
//
if (XTMax_MEM_Response_Array[(isa_address>>16)] == 2) {
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_LOW; // Physical RAM is NOT present at this page so XTMax will respond
}
else if (XTMax_MEM_Response_Array[(isa_address>>16)] == 0) {
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_LOW + DATA_OE_n_HIGH ; // Assert CHRDY_n=0 to begin wait states
delayNanoseconds(800);
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH; // De-assert CHRDY
gpio6_int = GPIO6_DR; // Read the data bus value currently on the ISA bus
data_in = 0xFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
if (data_in == isa_data_out) {
XTMax_MEM_Response_Array[(isa_address>>16)] = 1; // Physical RAM is present at this page so XTMax should not respond
}
else {
XTMax_MEM_Response_Array[(isa_address>>16)] = 2;
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_LOW; // Physical RAM is NOT present at this page so XTMax will respond
}
}
while ( (gpio9_int&0xF0) != 0xF0 ) { gpio9_int = GPIO9_DR; } // Wait here until cycle is complete
@@ -565,7 +589,7 @@ inline void Mem_Write_Cycle() {
}
else if ( (isa_address>=EXPANDED_RAM_BASE_ADDRESS) && (isa_address<0xA0000) ) { // Expanded RAM
else if (isa_address<0xA0000) { // XTMax stores the full 640 KB conventional memory
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_HIGH + CHRDY_OUT_LOW + trigger_out;
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_LOW + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
@@ -717,11 +741,3 @@ void loop() {
else if ((gpio9_int&0x00000080)==0) Mem_Write_Cycle();
}
}