Uploaded 10_5_2024
This commit is contained in:
Ted Fried
parent
e7bf88f3fd
commit
7def95c232
@ -18,6 +18,9 @@
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// Revision 1 9/7/2024
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// Initial revision
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//
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// Revision 2 10/5/2024
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// Added support for SD to Parallel interface
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//
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//------------------------------------------------------------------------
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//
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// Copyright (c) 2024 Ted Fried
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@ -96,39 +99,73 @@
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#define PIN_DOUT1 12
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#define PIN_DOUT0 10
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#define PIN_PSRAM_D3 54 // GPIO9-29
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#define PIN_PSRAM_D2 50 // GPIO9-28
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#define PIN_PSRAM_D1 49 // GPIO9-27
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#define PIN_PSRAM_D0 52 // GPIO9-26
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#define PIN_PSRAM_CLK 53 // GPIO9-25
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#define PIN_PSRAM_CS_n 48 // GPIO9-24
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# define ADDRESS_DATA_GPIO6_UNSCRAMBLE ( ((gpio6_int&0xFFFF0000)>>12) | ((gpio6_int&0x3000)>>10) | ((gpio6_int&0xC)>>2) )
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#define PIN_SD_CS_n 46 // GPIO8-17
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#define PIN_SD_MOSI 45 // GPIO8-12
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#define PIN_SD_CLK 44 // GPIO8-13
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#define PIN_SD_MISO 43 // GPIO8-14
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#define DATA_OE_n_LOW 0xFF7FFFFF
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#define DATA_OE_n_HIGH 0x00800000
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#define MUX_DATA_n_LOW 0xFFBFFFFF
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#define MUX_DATA_n_HIGH 0x00400000
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#define ADDRESS_DATA_GPIO6_UNSCRAMBLE ( ((gpio6_int&0xFFFF0000)>>12) | ((gpio6_int&0x3000)>>10) | ((gpio6_int&0xC)>>2) )
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#define CHRDY_OE_n_LOW 0xFFFBFFFF
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#define CHRDY_OE_n_HIGH 0x00040000
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#define GPIO7_DATA_OUT_UNSCRAMBLE ( ( (isa_data_out&0xF0)<<12) | (isa_data_out&0x0F) )
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#define MUX_ADDR_n_LOW 0xFFFFF7FF
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#define MUX_ADDR_n_HIGH 0x00000800
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#define DATA_OE_n_LOW 0x0
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#define DATA_OE_n_HIGH 0x00800000
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#define TRIG_OUT_LOW 0x0
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#define TRIG_OUT_HIGH 0x10000000
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#define MUX_DATA_n_LOW 0x0
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#define MUX_DATA_n_HIGH 0x00400000
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#define CHRDY_OUT_LOW 0x0
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#define CHRDY_OUT_HIGH 0x00000400
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#define CHRDY_OE_n_LOW 0x0
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#define CHRDY_OE_n_HIGH 0x00040000
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#define MUX_ADDR_n_LOW 0x0
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#define MUX_ADDR_n_HIGH 0x00000800
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#define PSRAM_RESET_VALUE 0x01000000
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#define PSRAM_CLK_HIGH 0x02000000
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// --------------------------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------------------------
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uint8_t io_scratch = 0x5A;
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uint32_t trigger_out = 0;
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uint32_t gpio6_int = 0;
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uint32_t gpio9_int = 0;
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uint32_t isa_address = 0;
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uint32_t page_base_address = 0;
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uint32_t psram_address = 0;
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uint32_t sd_pin_outputs = 0;
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uint8_t data_in = 0;
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uint8_t isa_data_out = 0;
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uint8_t lpt_data = 0;
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uint8_t lpt_status = 0xD8;
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uint8_t lpt_control = 0xC;
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uint8_t internal_RAM[0x60000];
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uint8_t lpt_status = 0x6F;
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uint8_t lpt_control = 0xEC;
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uint8_t nibble_in =0;
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uint8_t nibble_out =0;
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uint8_t read_byte =0;
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uint8_t reg_0x260 =0;
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uint8_t reg_0x261 =0;
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uint8_t reg_0x262 =0;
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uint8_t reg_0x263 =0;
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uint8_t internal_RAM[0x60000];
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// --------------------------------------------------------------------------------------------------
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@ -184,6 +221,22 @@ void setup() {
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pinMode(PIN_DOUT1, OUTPUT);
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pinMode(PIN_DOUT0, OUTPUT);
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pinMode(PIN_PSRAM_CLK, OUTPUT);
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pinMode(PIN_PSRAM_CS_n, OUTPUT);
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pinMode(PIN_PSRAM_D3, INPUT);
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pinMode(PIN_PSRAM_D2, INPUT);
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pinMode(PIN_PSRAM_D1, INPUT);
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pinMode(PIN_PSRAM_D0, OUTPUT);
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pinMode(PIN_SD_CLK, OUTPUT);
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pinMode(PIN_SD_CS_n, OUTPUT);
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pinMode(PIN_SD_MOSI, OUTPUT);
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pinMode(PIN_SD_MISO, INPUT_PULLUP);
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GPIO9_DR = PSRAM_RESET_VALUE; // Set CLK=0, CS_n=1, DATA=0
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digitalWriteFast(PIN_CHRDY_OE_n, 0x1);
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digitalWriteFast(PIN_CHRDY_OUT, 0x0);
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@ -191,6 +244,7 @@ void setup() {
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digitalWriteFast(PIN_MUX_ADDR_n, 0x0);
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digitalWriteFast(PIN_MUX_DATA_n, 0x1);
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digitalWriteFast(PIN_TRIG_OUT, 0x1);
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//noInterrupts(); // Disable Teensy interupts
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@ -199,113 +253,348 @@ void setup() {
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}
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// --------------------------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------------------------
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void Mem_Read_Cycle() {
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gpio6_int = GPIO6_DR;
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isa_address = ADDRESS_DATA_GPIO6_UNSCRAMBLE;
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if ( (isa_address>=0x40000) && (isa_address<0xA0000) ) { // 384 KB
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isa_data_out = internal_RAM[isa_address-0x40000];
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GPIO7_DR = ((isa_data_out&0xF0)<<12) | (isa_data_out&0x0F) ;
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GPIO8_DR = (MUX_DATA_n_HIGH | CHRDY_OE_n_HIGH) & DATA_OE_n_LOW;
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while ( (gpio9_int&0xF0) != 0xF0 ) { gpio9_int = GPIO9_DR; } // Wait here until cycle is complete
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GPIO8_DR = DATA_OE_n_HIGH | MUX_DATA_n_HIGH | CHRDY_OE_n_HIGH;
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}
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return;
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inline void PSRAM_Write_Clk_Cycle() {
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GPIO9_DR = (nibble_out&0xF) << 26; // Drive nibble data , CLK=0 , CS_n=0
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delayNanoseconds(1);
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GPIO9_DR = (nibble_out<<26) | PSRAM_CLK_HIGH; // Drive nibble data and CLK=1
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delayNanoseconds(1);
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return;
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}
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// --------------------------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------------------------
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void Mem_Write_Cycle() {
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inline void PSRAM_Read_Clk_Cycle() {
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GPIO9_DR = 0x0; // Drive CLK=0 , CS_n=0
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delayNanoseconds(1);
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GPIO9_DR = PSRAM_CLK_HIGH; // Drive CLK=1
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delayNanoseconds(1);
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nibble_in = (GPIO9_DR>>26) & 0xF; // Sample nibble data
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return;
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}
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// --------------------------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------------------------
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inline void PSRAM_Configure() {
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delayMicroseconds(200);
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nibble_out = 0x0; PSRAM_Write_Clk_Cycle(); // Set PSRAM to Quad Mode 0x35
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nibble_out = 0x0; PSRAM_Write_Clk_Cycle();
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nibble_out = 0x1; PSRAM_Write_Clk_Cycle();
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nibble_out = 0x1; PSRAM_Write_Clk_Cycle();
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nibble_out = 0x0; PSRAM_Write_Clk_Cycle();
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nibble_out = 0x1; PSRAM_Write_Clk_Cycle();
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nibble_out = 0x0; PSRAM_Write_Clk_Cycle();
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nibble_out = 0x1; PSRAM_Write_Clk_Cycle();
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GPIO9_DR = PSRAM_RESET_VALUE; // Drive CLK=0 , CS_n=1
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GPIO9_GDIR = 0x3F000000; // Change Data[3:0] to outputs quickly
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return;
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}
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// --------------------------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------------------------
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inline uint8_t PSRAM_Read(uint32_t address_in) {
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// Send Command = Quad Read = 0x0B
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//
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nibble_out = 0x0; PSRAM_Write_Clk_Cycle();
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nibble_out = 0xB; PSRAM_Write_Clk_Cycle();
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// Send 24-bit address in four clock cycles
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//
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nibble_out = address_in >> 20; PSRAM_Write_Clk_Cycle();
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nibble_out = address_in >> 16; PSRAM_Write_Clk_Cycle();
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nibble_out = address_in >> 12; PSRAM_Write_Clk_Cycle();
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nibble_out = address_in >> 8; PSRAM_Write_Clk_Cycle();
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nibble_out = address_in >> 4; PSRAM_Write_Clk_Cycle();
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nibble_out = address_in; PSRAM_Write_Clk_Cycle();
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + DATA_OE_n_LOW + CHRDY_OE_n_HIGH; // Two WAIT STATES
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// Four clocks of hi-Z - Make PSRAM Data signals hi-Z during this time
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//
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GPIO9_GDIR = 0x03000000; // Change Data[3:0] to inputs quickly
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PSRAM_Write_Clk_Cycle();
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PSRAM_Write_Clk_Cycle();
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PSRAM_Write_Clk_Cycle();
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PSRAM_Write_Clk_Cycle();
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// Clock in the data
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//
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PSRAM_Read_Clk_Cycle(); read_byte = nibble_in;
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PSRAM_Read_Clk_Cycle(); read_byte = (read_byte<<4) | nibble_in;
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GPIO9_DR = PSRAM_RESET_VALUE; // Drive CLK=0 , CS_n=1
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GPIO9_GDIR = 0x3F000000; // Change Data[3:0] to outputs quickly
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return read_byte;
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}
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// --------------------------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------------------------
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inline uint8_t PSRAM_Write(uint32_t address_in , int8_t local_data) {
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// Send Command = Quad Write = 0x02
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//
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nibble_out = 0x0; PSRAM_Write_Clk_Cycle();
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nibble_out = 0x2; PSRAM_Write_Clk_Cycle();
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// Send 24-bit address in four clock cycles
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//
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nibble_out = address_in >> 20; PSRAM_Write_Clk_Cycle();
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nibble_out = address_in >> 16; PSRAM_Write_Clk_Cycle();
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nibble_out = address_in >> 12; PSRAM_Write_Clk_Cycle();
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nibble_out = address_in >> 8; PSRAM_Write_Clk_Cycle();
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nibble_out = address_in >> 4; PSRAM_Write_Clk_Cycle();
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nibble_out = address_in; PSRAM_Write_Clk_Cycle();
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_LOW; // de-assert wait state
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// Send byte data in twp clock cycles
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//
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nibble_out = local_data >> 4; PSRAM_Write_Clk_Cycle();
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nibble_out = local_data; PSRAM_Write_Clk_Cycle();
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GPIO9_DR = PSRAM_RESET_VALUE; // Drive CLK=0 , CS_n=1
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return read_byte;
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}
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// --------------------------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------------------------
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inline void Mem_Read_Cycle() {
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gpio6_int = GPIO6_DR;
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isa_address = ADDRESS_DATA_GPIO6_UNSCRAMBLE;
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if ( (isa_address>=0x40000) && (isa_address<0xA0000) ) { // 384 KB
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GPIO7_DR = MUX_ADDR_n_HIGH;
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GPIO8_DR = (DATA_OE_n_HIGH | CHRDY_OE_n_HIGH) & MUX_DATA_n_LOW;
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if ( (isa_address>=0xE0000) && (isa_address<0xF0000) ) { // Expanded RAM page frame
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page_base_address = (isa_address & 0xFC000);
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if (page_base_address == 0xEC000) { psram_address = (reg_0x263<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == 0xE8000) { psram_address = (reg_0x262<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == 0xE4000) { psram_address = (reg_0x261<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == 0xE0000) { psram_address = (reg_0x260<<14) | (isa_address & 0x03FFF); }
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GPIO7_DR = MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_LOW + DATA_OE_n_LOW ; // Assert CHRDY_n=0 to begin wait states
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isa_data_out = PSRAM_Read(psram_address);
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out; // Output data
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while ( (gpio9_int&0xF0) != 0xF0 ) { gpio9_int = GPIO9_DR; } // Wait here until cycle is complete
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
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}
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else if ( (isa_address>=0x40000) && (isa_address<0xA0000) ) { // 384 KB
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isa_data_out = internal_RAM[isa_address-0x40000];
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_LOW;
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while ( (gpio9_int&0xF0) != 0xF0 ) { gpio9_int = GPIO9_DR; } // Wait here until cycle is complete
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
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}
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return;
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}
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// --------------------------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------------------------
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inline void Mem_Write_Cycle() {
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isa_address = ADDRESS_DATA_GPIO6_UNSCRAMBLE;
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if ( (isa_address>=0xE0000) && (isa_address<0xF0000) ) { // Expanded RAM page frame
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page_base_address = (isa_address & 0xFC000);
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if (page_base_address == 0xEC000) { psram_address = (reg_0x263<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == 0xE8000) { psram_address = (reg_0x262<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == 0xE4000) { psram_address = (reg_0x261<<14) | (isa_address & 0x03FFF); }
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else if (page_base_address == 0xE0000) { psram_address = (reg_0x260<<14) | (isa_address & 0x03FFF); }
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_HIGH + CHRDY_OUT_LOW + trigger_out;
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_LOW + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH; // Steer data mux to Data[7:0] and Assert CHRDY_n=0 to begin wait states
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delayNanoseconds(10); // Wait some time for buffers to switch from address to data
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gpio6_int = GPIO6_DR;
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data_in = 0xFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
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PSRAM_Write(psram_address , data_in);
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while ( (gpio9_int&0xF0) != 0xF0 ) { // Wait here until cycle is complete
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gpio6_int = GPIO6_DR; // Needed?
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gpio9_int = GPIO9_DR;
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}
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
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}
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else if ( (isa_address>=0x40000) && (isa_address<0xA0000) ) { // 384 KB
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_HIGH + CHRDY_OUT_LOW + trigger_out;
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_LOW + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
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while ( (gpio9_int&0xF0) != 0xF0 ) { // Wait here until cycle is complete
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gpio6_int = GPIO6_DR;
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gpio6_int = GPIO6_DR; // Needed?
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gpio9_int = GPIO9_DR;
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}
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internal_RAM[isa_address-0x40000] = 0xFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
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GPIO7_DR = MUX_ADDR_n_LOW;
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GPIO8_DR = DATA_OE_n_HIGH | MUX_DATA_n_HIGH | CHRDY_OE_n_HIGH;
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
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GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
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}
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return;
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}
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// --------------------------------------------------------------------------------------------------
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// --------------------------------------------------------------------------------------------------
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void IO_Read_Cycle() {
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inline void IO_Read_Cycle() {
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gpio6_int = GPIO6_DR;
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isa_address = 0xFFFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
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if ((isa_address&0x0FF8)==0x378 ) { // Location of Parallel Port
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if ((isa_address&0x0FFC)==0x260 ) { // Location of 16 KB Expanded Memory page frame pointers
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switch (isa_address) {
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case 0x260: isa_data_out = reg_0x260; break;
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case 0x261: isa_data_out = reg_0x261; break;
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case 0x262: isa_data_out = reg_0x262; break;
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case 0x263: isa_data_out = reg_0x263; break;
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}
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GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
|
||||
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_LOW;
|
||||
|
||||
while ( (gpio9_int&0xF0) != 0xF0 ) { gpio9_int = GPIO9_DR; } // Wait here until cycle is complete
|
||||
|
||||
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
|
||||
}
|
||||
|
||||
|
||||
else if ((isa_address&0x0FF8)==0x378 ) { // Location of Parallel Port
|
||||
|
||||
if ((GPIO8_DR&0x00004000)!=0) { lpt_status = lpt_status | 0xFF; }
|
||||
else { lpt_status = lpt_status & 0x00; } // PIN_SD_MISO 43 GPIO8-14
|
||||
|
||||
|
||||
switch (isa_address) {
|
||||
case 0x378: isa_data_out = lpt_data; break;
|
||||
case 0x379: isa_data_out = lpt_status; break;
|
||||
case 0x37A: isa_data_out = lpt_control; break;
|
||||
}
|
||||
|
||||
GPIO7_DR = ((isa_data_out&0xF0)<<12) | (isa_data_out&0x0F) ;
|
||||
GPIO8_DR = (MUX_DATA_n_HIGH | CHRDY_OE_n_HIGH) & DATA_OE_n_LOW;
|
||||
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
|
||||
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_LOW;
|
||||
|
||||
while ( (gpio9_int&0xF0) != 0xF0 ) { gpio9_int = GPIO9_DR; } // Wait here until cycle is complete
|
||||
|
||||
GPIO8_DR = DATA_OE_n_HIGH | MUX_DATA_n_HIGH | CHRDY_OE_n_HIGH;
|
||||
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------------------------
|
||||
// --------------------------------------------------------------------------------------------------
|
||||
|
||||
void IO_Write_Cycle() {
|
||||
|
||||
gpio6_int = GPIO6_DR;
|
||||
|
||||
// --------------------------------------------------------------------------------------------------
|
||||
// --------------------------------------------------------------------------------------------------
|
||||
|
||||
inline void IO_Write_Cycle() {
|
||||
|
||||
isa_address = 0xFFFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
|
||||
|
||||
if ((isa_address&0x0FF8)==0x378 ) { // Location of Parallel Port
|
||||
GPIO7_DR = MUX_ADDR_n_HIGH;
|
||||
GPIO8_DR = (DATA_OE_n_HIGH | CHRDY_OE_n_HIGH) & MUX_DATA_n_LOW;
|
||||
if ((isa_address&0x0FFC)==0x260 ) { // Location of 16 KB Expanded Memory page frame pointers
|
||||
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_HIGH + CHRDY_OUT_LOW + trigger_out;
|
||||
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_LOW + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
|
||||
|
||||
while ( (gpio9_int&0xF0) != 0xF0 ) { // Wait here until cycle is complete
|
||||
gpio6_int = GPIO6_DR;
|
||||
gpio6_int = GPIO6_DR; // Needed?
|
||||
gpio9_int = GPIO9_DR;
|
||||
}
|
||||
|
||||
data_in = 0xFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
|
||||
|
||||
switch (isa_address) {
|
||||
switch (isa_address) {
|
||||
case 0x260: reg_0x260 = data_in; break;
|
||||
case 0x261: reg_0x261 = data_in; break;
|
||||
case 0x262: reg_0x262 = data_in; break;
|
||||
case 0x263: reg_0x263 = data_in; break;
|
||||
}
|
||||
|
||||
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
|
||||
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
|
||||
}
|
||||
|
||||
else if ((isa_address&0x0FF8)==0x378 ) { // Location of Parallel Port
|
||||
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_HIGH + CHRDY_OUT_LOW + trigger_out;
|
||||
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_LOW + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
|
||||
|
||||
while ( (gpio9_int&0xF0) != 0xF0 ) { // Wait here until cycle is complete
|
||||
gpio6_int = GPIO6_DR; // Needed?
|
||||
gpio9_int = GPIO9_DR;
|
||||
}
|
||||
|
||||
data_in = 0xFF & ADDRESS_DATA_GPIO6_UNSCRAMBLE;
|
||||
|
||||
switch (isa_address) {
|
||||
case 0x378: lpt_data = data_in; break;
|
||||
case 0x37A: lpt_control = data_in; break;
|
||||
}
|
||||
|
||||
|
||||
GPIO7_DR = MUX_ADDR_n_LOW;
|
||||
GPIO8_DR = DATA_OE_n_HIGH | MUX_DATA_n_HIGH | CHRDY_OE_n_HIGH;
|
||||
|
||||
//Serial.printf("%x %x",gpio6_int,data_in);
|
||||
sd_pin_outputs = ((lpt_data&0x4)<<15) | ((lpt_data&0x2)<<12) | ((lpt_data&0x1)<<12); // lpt_data[2]=SD_CS_n - lpt_data[1]=SD_CLK - lpt_data[0]=SD_MOSI
|
||||
|
||||
//trigger_out = ((lpt_data&0x1)<<28); // SD_MOSI
|
||||
//trigger_out = ((lpt_data&0x2)<<27); // SD_CLK
|
||||
//trigger_out = ((lpt_data&0x4)<<26); // SD_CS_n
|
||||
|
||||
GPIO7_DR = GPIO7_DATA_OUT_UNSCRAMBLE + MUX_ADDR_n_LOW + CHRDY_OUT_LOW + trigger_out;
|
||||
GPIO8_DR = sd_pin_outputs + MUX_DATA_n_HIGH + CHRDY_OE_n_HIGH + DATA_OE_n_HIGH;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
// -------------------------------------------------
|
||||
//
|
||||
// Main loop
|
||||
@ -318,10 +607,12 @@ void loop() {
|
||||
//
|
||||
//delay (1000);
|
||||
|
||||
PSRAM_Configure();
|
||||
|
||||
while (1) {
|
||||
|
||||
|
||||
gpio6_int = GPIO6_DR;
|
||||
gpio9_int = GPIO9_DR;
|
||||
|
||||
if ((gpio9_int&0x80000010)==0) IO_Read_Cycle(); // Isolate and check AEN and IO Rd/Wr
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user