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MicroCoreLabs 2022-05-14 11:32:53 -07:00
parent efb9c703ad
commit 88fb3af3a3
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3086
MCLZ8/Code/MCLZ8.ino Normal file
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MCLZ8/PCB/MCLZ8_PCB-cache.lib Normal file
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 74xx_74LS573
#
DEF 74xx_74LS573 U 0 40 Y Y 1 L N
F0 "U" -300 650 50 H V C CNN
F1 "74xx_74LS573" -300 -650 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
DIP?20*
$ENDFPLIST
DRAW
S -300 600 300 -600 1 1 10 f
X OE 1 -500 -500 200 R 50 50 1 0 I I
X GND 10 0 -800 200 U 50 50 1 0 W
X Load 11 -500 -400 200 R 50 50 1 0 I
X Q7 12 500 -200 200 L 50 50 1 0 T
X Q6 13 500 -100 200 L 50 50 1 0 T
X Q5 14 500 0 200 L 50 50 1 0 T
X Q4 15 500 100 200 L 50 50 1 0 T
X Q3 16 500 200 200 L 50 50 1 0 T
X Q2 17 500 300 200 L 50 50 1 0 T
X Q1 18 500 400 200 L 50 50 1 0 T
X Q0 19 500 500 200 L 50 50 1 0 T
X D0 2 -500 500 200 R 50 50 1 0 I
X VCC 20 0 800 200 D 50 50 1 0 W
X D1 3 -500 400 200 R 50 50 1 0 I
X D2 4 -500 300 200 R 50 50 1 0 I
X D3 5 -500 200 200 R 50 50 1 0 I
X D4 6 -500 100 200 R 50 50 1 0 I
X D5 7 -500 0 200 R 50 50 1 0 I
X D6 8 -500 -100 200 R 50 50 1 0 I
X D7 9 -500 -200 200 R 50 50 1 0 I
ENDDRAW
ENDDEF
#
# CPU_Z80CPU
#
DEF CPU_Z80CPU U 0 40 Y Y 1 F N
F0 "U" -550 1400 50 H V L CNN
F1 "CPU_Z80CPU" 250 1400 50 H V L CNN
F2 "" 0 400 50 H I C CNN
F3 "" 0 400 50 H I C CNN
$FPLIST
DIP*
PDIP*
$ENDFPLIST
DRAW
S -550 1350 550 -1350 0 1 10 f
X A11 1 700 100 150 L 50 50 1 1 O
X D6 10 700 -1100 150 L 50 50 1 1 B
X VCC 11 0 1500 150 D 50 50 1 1 W
X D2 12 700 -700 150 L 50 50 1 1 B
X D7 13 700 -1200 150 L 50 50 1 1 B
X D0 14 700 -500 150 L 50 50 1 1 B
X D1 15 700 -600 150 L 50 50 1 1 B
X ~INT~ 16 -700 500 150 R 50 50 1 1 I
X ~NMI~ 17 -700 600 150 R 50 50 1 1 I
X ~HALT~ 18 -700 -100 150 R 50 50 1 1 O
X ~MREQ~ 19 -700 -700 150 R 50 50 1 1 O
X A12 2 700 0 150 L 50 50 1 1 O
X ~IORQ~ 20 -700 -800 150 R 50 50 1 1 O
X ~RD~ 21 -700 -500 150 R 50 50 1 1 O
X ~WR~ 22 -700 -600 150 R 50 50 1 1 O
X ~BUSACK~ 23 -700 -1200 150 R 50 50 1 1 O
X ~WAIT~ 24 -700 0 150 R 50 50 1 1 I
X ~BUSRQ~ 25 -700 -1100 150 R 50 50 1 1 I
X ~RESET~ 26 -700 1200 150 R 50 50 1 1 I
X ~M1~ 27 -700 200 150 R 50 50 1 1 O
X ~RFSH~ 28 -700 100 150 R 50 50 1 1 O
X GND 29 0 -1500 150 U 50 50 1 1 W
X A13 3 700 -100 150 L 50 50 1 1 O
X A0 30 700 1200 150 L 50 50 1 1 O
X A1 31 700 1100 150 L 50 50 1 1 O
X A2 32 700 1000 150 L 50 50 1 1 O
X A3 33 700 900 150 L 50 50 1 1 O
X A4 34 700 800 150 L 50 50 1 1 O
X A5 35 700 700 150 L 50 50 1 1 O
X A6 36 700 600 150 L 50 50 1 1 O
X A7 37 700 500 150 L 50 50 1 1 O
X A8 38 700 400 150 L 50 50 1 1 O
X A9 39 700 300 150 L 50 50 1 1 O
X A14 4 700 -200 150 L 50 50 1 1 O
X A10 40 700 200 150 L 50 50 1 1 O
X A15 5 700 -300 150 L 50 50 1 1 O
X ~CLK~ 6 -700 900 150 R 50 50 1 1 I C
X D4 7 700 -900 150 L 50 50 1 1 B
X D3 8 700 -800 150 L 50 50 1 1 B
X D5 9 700 -1000 150 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# power_+3.3V
#
DEF power_+3.3V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3.3V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# teensy_Teensy4.1
#
DEF teensy_Teensy4.1 U 0 40 Y Y 1 F N
F0 "U" 0 2550 50 H V C CNN
F1 "teensy_Teensy4.1" 0 2450 50 H V C CNN
F2 "" -400 400 50 H I C CNN
F3 "" -400 400 50 H I C CNN
DRAW
T 0 450 1950 40 0 0 0 "(250mA max)" Normal 0 C C
T 0 450 2150 40 0 0 0 "(3.6v to 5.5v)" Normal 0 C C
S -900 2400 900 -1100 0 1 0 N
S -800 -50 -800 -50 0 1 0 N
P 2 0 0 0 -900 -250 900 -250 N
X 8_TX2_IN1 10 -1100 1250 200 R 50 50 0 0 B
X 9_OUT1C 11 -1100 1150 200 R 50 50 0 0 B
X 10_CS_MQSR 12 -1100 1050 200 R 50 50 0 0 B
X 11_MOSI_CTX1 13 -1100 950 200 R 50 50 0 0 B
X 12_MISO_MQSL 14 -1100 850 200 R 50 50 0 0 B
X 3V3 15 -1100 750 200 R 50 50 0 0 W
X 24_A10_TX6_SCL2 16 -1100 650 200 R 50 50 0 0 B
X 25_A11_RX6_SDA2 17 -1100 550 200 R 50 50 0 0 B
X 26_A12_MOSI1 18 -1100 450 200 R 50 50 0 0 B
X 27_A13_SCK1 19 -1100 350 200 R 50 50 0 0 B
X 28_RX7 20 -1100 250 200 R 50 50 0 0 B
X 29_TX7 21 -1100 150 200 R 50 50 0 0 B
X 30_CRX3 22 -1100 50 200 R 50 50 0 0 B
X 31_CTX3 23 -1100 -50 200 R 50 50 0 0 B
X 32_OUT1B 24 -1100 -150 200 R 50 50 0 0 B
X 33_MCLK2 25 1100 -150 200 L 50 50 0 0 B
X 34_RX8 26 1100 -50 200 L 50 50 0 0 B
X 35_TX8 27 1100 50 200 L 50 50 0 0 B
X 36_CS 28 1100 150 200 L 50 50 0 0 B
X 37_CS 29 1100 250 200 L 50 50 0 0 B
X 38_CS1_IN1 30 1100 350 200 L 50 50 0 0 B
X 39_MISO1_OUT1A 31 1100 450 200 L 50 50 0 0 B
X 40_A16 32 1100 550 200 L 50 50 0 0 B
X 41_A17 33 1100 650 200 L 50 50 0 0 B
X 13_SCK_LED 35 1100 850 200 L 50 50 0 0 B
X 14_A0_TX3_SPDIF_OUT 36 1100 950 200 L 50 50 0 0 B
X 15_A1_RX3_SPDIF_IN 37 1100 1050 200 L 50 50 0 0 B
X 16_A2_RX4_SCL1 38 1100 1150 200 L 50 50 0 0 B
X 17_A3_TX4_SDA1 39 1100 1250 200 L 50 50 0 0 B
X 18_A4_SDA 40 1100 1350 200 L 50 50 0 0 B
X 19_A5_SCL 41 1100 1450 200 L 50 50 0 0 B
X 20_A6_TX5_LRCLK1 42 1100 1550 200 L 50 50 0 0 B
X 21_A7_RX5_BCLK1 43 1100 1650 200 L 50 50 0 0 B
X 22_A8_CTX1 44 1100 1750 200 L 50 50 0 0 B
X 23_A9_CRX1_MCLK1 45 1100 1850 200 L 50 50 0 0 B
X 3V3 46 1100 1950 200 L 50 50 0 0 O
X GND 47 1100 2050 200 L 50 50 0 0 O
X VIN 48 1100 2150 200 L 50 50 0 0 W
X 3_LRCLK2 5 -1100 1750 200 R 50 50 0 0 B
X 4_BCLK2 6 -1100 1650 200 R 50 50 0 0 B
X 5_IN2 7 -1100 1550 200 R 50 50 0 0 B
X 6_OUT1D 8 -1100 1450 200 R 50 50 0 0 B
X 7_RX2_OUT1A 9 -1100 1350 200 R 50 50 0 0 B
X GND 1 -1100 2150 200 R 50 50 1 1 W
X 0_RX1_CRX2_CS1 2 -1100 2050 200 R 50 50 1 1 B
X 1_TX1_CTX2_MISO1 3 -1100 1950 200 R 50 50 1 1 B
X GND 34 1100 750 200 L 50 50 1 1 W
X 2_OUT2 4 -1100 1850 200 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
#End Library

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MCLZ8/PCB/MCLZ8_PCB.kicad_pcb Normal file
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MCLZ8/PCB/MCLZ8_PCB.kicad_pcb-bak Normal file
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MCLZ8/PCB/MCLZ8_PCB.pro Normal file
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update=3/10/2022 10:42:43 PM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=4
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1524
MinViaDiameter=0.4
MinViaDrill=0.254
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.1524
ViaDiameter1=0.5842
ViaDrill1=0.254
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=L1.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=L2.Cu
Type=0
Enabled=1
[pcbnew/Layer.In2.Cu]
Name=L3.Cu
Type=0
Enabled=1
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=L4.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.1524
ViaDiameter=0.5842
ViaDrill=0.254
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=157
ERC_TestSimilarLabels=1

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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L power:GND #PWR015
U 1 1 61B99BEA
P 9550 5250
F 0 "#PWR015" H 9550 5000 50 0001 C CNN
F 1 "GND" H 9555 5077 50 0000 C CNN
F 2 "" H 9550 5250 50 0001 C CNN
F 3 "" H 9550 5250 50 0001 C CNN
1 9550 5250
1 0 0 -1
$EndComp
Text GLabel 10350 2400 2 50 Input ~ 0
CPU_A0
Wire Wire Line
10350 2400 10250 2400
Text GLabel 10350 2500 2 50 Input ~ 0
CPU_A1
Wire Wire Line
10350 2500 10250 2500
Text GLabel 10350 2600 2 50 Input ~ 0
CPU_A2
Wire Wire Line
10350 2600 10250 2600
Text GLabel 10350 2700 2 50 Input ~ 0
CPU_A3
Wire Wire Line
10350 2700 10250 2700
Text GLabel 10350 2800 2 50 Input ~ 0
CPU_A4
Wire Wire Line
10350 2800 10250 2800
Text GLabel 10350 2900 2 50 Input ~ 0
CPU_A5
Wire Wire Line
10350 2900 10250 2900
Text GLabel 10350 3000 2 50 Input ~ 0
CPU_A6
Wire Wire Line
10350 3000 10250 3000
Text GLabel 10350 3100 2 50 Input ~ 0
CPU_A7
Wire Wire Line
10350 3100 10250 3100
Text GLabel 10350 3200 2 50 Input ~ 0
CPU_A8
Wire Wire Line
10350 3200 10250 3200
Text GLabel 10350 3300 2 50 Input ~ 0
CPU_A9
Wire Wire Line
10350 3300 10250 3300
Text GLabel 10350 3400 2 50 Input ~ 0
CPU_A10
Wire Wire Line
10350 3400 10250 3400
Text GLabel 10350 3500 2 50 Input ~ 0
CPU_A11
Wire Wire Line
10350 3500 10250 3500
Text GLabel 10350 3600 2 50 Input ~ 0
CPU_A12
Wire Wire Line
10350 3600 10250 3600
Text GLabel 10350 3700 2 50 Input ~ 0
CPU_A13
Wire Wire Line
10350 3700 10250 3700
Text GLabel 10350 3800 2 50 Input ~ 0
CPU_A14
Wire Wire Line
10350 3800 10250 3800
Text GLabel 10350 3900 2 50 Input ~ 0
CPU_A15
Wire Wire Line
10350 3900 10250 3900
Text GLabel 8750 3100 0 50 Input ~ 0
CPU_INTR
Text GLabel 8750 3000 0 50 Input ~ 0
CPU_NMI
Text GLabel 8750 2400 0 50 Input ~ 0
CPU_RESET
Text GLabel 8750 3600 0 50 Input ~ 0
CPU_WAIT
Text GLabel 8750 2700 0 50 Input ~ 0
CPU_CLK
$Comp
L power:+5V #PWR016
U 1 1 61BB1FD6
P 9550 1950
F 0 "#PWR016" H 9550 1800 50 0001 C CNN
F 1 "+5V" H 9565 2123 50 0000 C CNN
F 2 "" H 9550 1950 50 0001 C CNN
F 3 "" H 9550 1950 50 0001 C CNN
1 9550 1950
1 0 0 -1
$EndComp
Wire Wire Line
9550 2100 9550 1950
Wire Wire Line
5900 3600 6000 3600
Wire Wire Line
5900 3700 6000 3700
Wire Wire Line
5900 3800 6000 3800
Wire Wire Line
5900 3900 6000 3900
Wire Wire Line
5900 4000 6000 4000
Wire Wire Line
5900 4100 6000 4100
Wire Wire Line
5900 4200 6000 4200
Wire Wire Line
5900 4300 6000 4300
$Comp
L power:GND #PWR012
U 1 1 61C0E7B7
P 6500 5000
F 0 "#PWR012" H 6500 4750 50 0001 C CNN
F 1 "GND" H 6505 4827 50 0000 C CNN
F 2 "" H 6500 5000 50 0001 C CNN
F 3 "" H 6500 5000 50 0001 C CNN
1 6500 5000
1 0 0 -1
$EndComp
$Comp
L power:+3.3V #PWR011
U 1 1 61C0E7BE
P 6500 3200
F 0 "#PWR011" H 6500 3050 50 0001 C CNN
F 1 "+3.3V" H 6515 3373 50 0000 C CNN
F 2 "" H 6500 3200 50 0001 C CNN
F 3 "" H 6500 3200 50 0001 C CNN
1 6500 3200
1 0 0 -1
$EndComp
Wire Wire Line
6500 3300 6500 3200
Wire Wire Line
5900 4500 6000 4500
Text GLabel 7100 3600 2 50 Input ~ 0
CPU_AD0
Text GLabel 7100 3700 2 50 Input ~ 0
CPU_AD1
Text GLabel 7100 3800 2 50 Input ~ 0
CPU_AD2
Text GLabel 7100 3900 2 50 Input ~ 0
CPU_AD3
Text GLabel 7100 4000 2 50 Input ~ 0
CPU_AD4
Text GLabel 7100 4100 2 50 Input ~ 0
CPU_AD5
Text GLabel 7100 4200 2 50 Input ~ 0
CPU_AD6
Text GLabel 7100 4300 2 50 Input ~ 0
CPU_AD7
Wire Wire Line
7100 4300 7000 4300
Wire Wire Line
7100 4200 7000 4200
Wire Wire Line
7100 4100 7000 4100
Wire Wire Line
7100 4000 7000 4000
Wire Wire Line
7100 3900 7000 3900
Wire Wire Line
7100 3800 7000 3800
Wire Wire Line
7100 3700 7000 3700
Wire Wire Line
7100 3600 7000 3600
Text GLabel 5900 3600 0 50 Input ~ 0
TEENSY_AD0_OUT
Text GLabel 5900 3700 0 50 Input ~ 0
TEENSY_AD1_OUT
Text GLabel 5900 3800 0 50 Input ~ 0
TEENSY_AD2_OUT
Text GLabel 5900 3900 0 50 Input ~ 0
TEENSY_AD3_OUT
Text GLabel 5900 4000 0 50 Input ~ 0
TEENSY_AD4_OUT
Text GLabel 5900 4100 0 50 Input ~ 0
TEENSY_AD5_OUT
Text GLabel 5900 4200 0 50 Input ~ 0
TEENSY_AD6_OUT
Text GLabel 5900 4300 0 50 Input ~ 0
TEENSY_AD7_OUT
$Comp
L power:+3.3V #PWR010
U 1 1 61C82B60
P 5900 4500
F 0 "#PWR010" H 5900 4350 50 0001 C CNN
F 1 "+3.3V" V 5900 4750 50 0000 C CNN
F 2 "" H 5900 4500 50 0001 C CNN
F 3 "" H 5900 4500 50 0001 C CNN
1 5900 4500
0 -1 -1 0
$EndComp
Wire Wire Line
6500 4900 6500 5000
Wire Wire Line
5900 4600 6000 4600
Text GLabel 5900 4600 0 50 Input ~ 0
TEENSY_DATA_OE_n
Text Notes 1850 1100 0 276 ~ 55
MCLZ8
Text GLabel 4700 6650 0 50 Input ~ 0
CPU_AD0
Wire Wire Line
4700 5950 4800 5950
Text GLabel 4700 6550 0 50 Input ~ 0
CPU_AD1
Wire Wire Line
4700 6050 4800 6050
Text GLabel 4700 6450 0 50 Input ~ 0
CPU_AD2
Wire Wire Line
4700 6150 4800 6150
Text GLabel 4700 6350 0 50 Input ~ 0
CPU_AD3
Wire Wire Line
4700 6250 4800 6250
Text GLabel 4700 6250 0 50 Input ~ 0
CPU_AD4
Wire Wire Line
4700 6350 4800 6350
Text GLabel 4700 6150 0 50 Input ~ 0
CPU_AD5
Wire Wire Line
4700 6450 4800 6450
Text GLabel 4700 6050 0 50 Input ~ 0
CPU_AD6
Wire Wire Line
4700 6550 4800 6550
Text GLabel 4700 5950 0 50 Input ~ 0
CPU_AD7
Wire Wire Line
4700 6650 4800 6650
$Comp
L power:GND #PWR014
U 1 1 61BB88CC
P 5300 7350
F 0 "#PWR014" H 5300 7100 50 0001 C CNN
F 1 "GND" H 5305 7177 50 0000 C CNN
F 2 "" H 5300 7350 50 0001 C CNN
F 3 "" H 5300 7350 50 0001 C CNN
1 5300 7350
1 0 0 -1
$EndComp
Wire Wire Line
5300 7350 5300 7300
$Comp
L power:+3.3V #PWR013
U 1 1 61BB9EEB
P 5300 5550
F 0 "#PWR013" H 5300 5400 50 0001 C CNN
F 1 "+3.3V" H 5315 5723 50 0000 C CNN
F 2 "" H 5300 5550 50 0001 C CNN
F 3 "" H 5300 5550 50 0001 C CNN
1 5300 5550
1 0 0 -1
$EndComp
Wire Wire Line
5300 5650 5300 5550
Wire Wire Line
5900 5950 5800 5950
Wire Wire Line
5900 6050 5800 6050
Wire Wire Line
5900 6150 5800 6150
Wire Wire Line
5900 6250 5800 6250
Wire Wire Line
5900 6350 5800 6350
Text GLabel 5900 6150 2 50 Input ~ 0
TEENSY_AD5_IN
Wire Wire Line
5900 6450 5800 6450
Text GLabel 5900 6050 2 50 Input ~ 0
TEENSY_AD6_IN
Wire Wire Line
5900 6550 5800 6550
Text GLabel 5900 5950 2 50 Input ~ 0
TEENSY_AD7_IN
Wire Wire Line
5900 6650 5800 6650
Wire Wire Line
5300 7300 4700 7300
Wire Wire Line
4700 7300 4700 6950
Wire Wire Line
4700 6950 4800 6950
Connection ~ 5300 7300
Wire Wire Line
5300 7300 5300 7250
Text GLabel 3950 2700 2 50 Input ~ 0
TEENSY_AD0_IN
Text GLabel 3950 2800 2 50 Input ~ 0
TEENSY_AD1_IN
Text GLabel 3950 2900 2 50 Input ~ 0
TEENSY_AD2_IN
Text GLabel 3950 3000 2 50 Input ~ 0
TEENSY_AD3_IN
Text GLabel 3950 3100 2 50 Input ~ 0
TEENSY_AD4_IN
Wire Wire Line
1550 2100 1650 2100
Wire Wire Line
1550 2200 1650 2200
Wire Wire Line
1550 2300 1650 2300
Wire Wire Line
1550 2400 1650 2400
$Comp
L power:GND #PWR03
U 1 1 61CD3DF8
P 1550 1900
F 0 "#PWR03" H 1550 1650 50 0001 C CNN
F 1 "GND" V 1550 1700 50 0000 C CNN
F 2 "" H 1550 1900 50 0001 C CNN
F 3 "" H 1550 1900 50 0001 C CNN
1 1550 1900
0 1 1 0
$EndComp
Wire Wire Line
1550 1900 1650 1900
$Comp
L power:GND #PWR07
U 1 1 61CE84A9
P 4000 2000
F 0 "#PWR07" H 4000 1750 50 0001 C CNN
F 1 "GND" V 4000 1800 50 0000 C CNN
F 2 "" H 4000 2000 50 0001 C CNN
F 3 "" H 4000 2000 50 0001 C CNN
1 4000 2000
0 -1 -1 0
$EndComp
Wire Wire Line
3850 2000 4000 2000
$Comp
L power:+3.3V #PWR08
U 1 1 61CED9E3
P 4000 2100
F 0 "#PWR08" H 4000 1950 50 0001 C CNN
F 1 "+3.3V" V 4000 2350 50 0000 C CNN
F 2 "" H 4000 2100 50 0001 C CNN
F 3 "" H 4000 2100 50 0001 C CNN
1 4000 2100
0 1 1 0
$EndComp
Wire Wire Line
3850 2100 4000 2100
$Comp
L power:GND #PWR09
U 1 1 61D0CC7F
P 4000 3300
F 0 "#PWR09" H 4000 3050 50 0001 C CNN
F 1 "GND" V 4000 3100 50 0000 C CNN
F 2 "" H 4000 3300 50 0001 C CNN
F 3 "" H 4000 3300 50 0001 C CNN
1 4000 3300
0 -1 -1 0
$EndComp
Wire Wire Line
3850 3300 4000 3300
$Comp
L power:+3.3V #PWR02
U 1 1 61D121B1
P 1500 3300
F 0 "#PWR02" H 1500 3150 50 0001 C CNN
F 1 "+3.3V" V 1500 3550 50 0000 C CNN
F 2 "" H 1500 3300 50 0001 C CNN
F 3 "" H 1500 3300 50 0001 C CNN
1 1500 3300
0 -1 -1 0
$EndComp
Wire Wire Line
1650 3300 1500 3300
Wire Wire Line
1550 2500 1650 2500
Wire Wire Line
1550 2600 1650 2600
Wire Wire Line
1550 2700 1650 2700
Wire Wire Line
1550 2800 1650 2800
Wire Wire Line
1550 2900 1650 2900
Wire Wire Line
1550 3000 1650 3000
Wire Wire Line
1550 4000 1650 4000
Wire Wire Line
1550 4100 1650 4100
Wire Wire Line
1550 4200 1650 4200
Wire Wire Line
3850 2200 3950 2200
Wire Wire Line
3850 2300 3950 2300
Wire Wire Line
3850 2400 3950 2400
Wire Wire Line
3850 2500 3950 2500
Wire Wire Line
3850 2600 3950 2600
Wire Wire Line
3850 2700 3950 2700
Wire Wire Line
3850 2800 3950 2800
Wire Wire Line
3850 2900 3950 2900
Wire Wire Line
3850 3900 3950 3900
Wire Wire Line
3850 4000 3950 4000
Wire Wire Line
3850 4100 3950 4100
Wire Wire Line
3850 4200 3950 4200
Wire Wire Line
3850 3500 3950 3500
Wire Wire Line
3850 3600 3950 3600
Wire Wire Line
3850 3700 3950 3700
Wire Wire Line
3850 3800 3950 3800
Wire Wire Line
3850 3400 3950 3400
Wire Wire Line
3850 3000 3950 3000
Wire Wire Line
3850 3100 3950 3100
Wire Wire Line
3850 3200 3950 3200
Wire Wire Line
1550 2000 1650 2000
Text GLabel 1550 2200 0 50 Input ~ 0
TEENSY_DATA_OE_n
Text GLabel 1550 2300 0 50 Input ~ 0
TEENSY_AD0_OUT
Text GLabel 1550 2400 0 50 Input ~ 0
TEENSY_AD1_OUT
Text GLabel 1550 2500 0 50 Input ~ 0
TEENSY_AD2_OUT
Text GLabel 1550 2600 0 50 Input ~ 0
TEENSY_AD3_OUT
Text GLabel 1550 2700 0 50 Input ~ 0
TEENSY_AD4_OUT
Text GLabel 1550 2800 0 50 Input ~ 0
TEENSY_AD5_OUT
Text GLabel 1550 2900 0 50 Input ~ 0
TEENSY_AD6_OUT
Text GLabel 1550 3000 0 50 Input ~ 0
TEENSY_AD7_OUT
Text GLabel 1550 4000 0 50 Input ~ 0
CPU_A15
Text GLabel 1550 4100 0 50 Input ~ 0
CPU_A14
Text GLabel 1550 4200 0 50 Input ~ 0
CPU_A13
Text GLabel 3950 4200 2 50 Input ~ 0
CPU_A12
Text GLabel 3950 4100 2 50 Input ~ 0
CPU_A11
Text GLabel 3950 4000 2 50 Input ~ 0
CPU_A10
Text GLabel 3950 3900 2 50 Input ~ 0
CPU_A9
Text GLabel 3950 3800 2 50 Input ~ 0
CPU_A8
Text GLabel 3950 3600 2 50 Input ~ 0
TEENSY_AD7_IN
Text GLabel 3950 3500 2 50 Input ~ 0
TEENSY_AD6_IN
Text GLabel 3950 3400 2 50 Input ~ 0
TEENSY_AD5_IN
Text GLabel 3950 2400 2 50 Input ~ 0
TEENSY_CLK
Text GLabel 3950 2500 2 50 Input ~ 0
TEENSY_INTR
Text GLabel 3950 2600 2 50 Input ~ 0
TEENSY_NMI
Text GLabel 3950 2200 2 50 Input ~ 0
TEENSY_RESET
Text GLabel 3950 2300 2 50 Input ~ 0
TEENSY_WAIT
$Comp
L teensy:Teensy4.1 U1
U 1 1 61B9A39C
P 2750 4050
F 0 "U1" H 2750 6615 50 0000 C CNN
F 1 "Teensy4.1" H 2750 6524 50 0000 C CNN
F 2 "Teensy:Teensy41_Ted_Modified" H 2350 4450 50 0001 C CNN
F 3 "" H 2350 4450 50 0001 C CNN
1 2750 4050
1 0 0 -1
$EndComp
$Comp
L 74xx:74LS573 U3
U 1 1 61B9DB3E
P 5300 6450
F 0 "U3" H 4900 7200 50 0000 C CNN
F 1 "SN74LVC573A" H 4850 7100 50 0000 C CNN
F 2 "Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm" H 5300 6450 50 0001 C CNN
F 3 "74xx/74hc573.pdf" H 5300 6450 50 0001 C CNN
1 5300 6450
1 0 0 -1
$EndComp
$Comp
L 74xx:74LS573 U5
U 1 1 61C0E7A1
P 6500 4100
F 0 "U5" H 6100 4850 50 0000 C CNN
F 1 "SN74LVC573A" H 6100 4750 50 0000 C CNN
F 2 "Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm" H 6500 4100 50 0001 C CNN
F 3 "74xx/74hc573.pdf" H 6500 4100 50 0001 C CNN
1 6500 4100
1 0 0 -1
$EndComp
$Comp
L 74xx:74LS573 U4
U 1 1 61C1662B
P 2400 6500
F 0 "U4" H 2000 7250 50 0000 C CNN
F 1 "SN74LVC573A" H 2000 7150 50 0000 C CNN
F 2 "Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm" H 2400 6500 50 0001 C CNN
F 3 "74xx/74hc573.pdf" H 2400 6500 50 0001 C CNN
1 2400 6500
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR05
U 1 1 61C16641
P 2400 7400
F 0 "#PWR05" H 2400 7150 50 0001 C CNN
F 1 "GND" H 2405 7227 50 0000 C CNN
F 2 "" H 2400 7400 50 0001 C CNN
F 3 "" H 2400 7400 50 0001 C CNN
1 2400 7400
1 0 0 -1
$EndComp
Wire Wire Line
2400 7400 2400 7350
$Comp
L power:+3.3V #PWR04
U 1 1 61C16648
P 2400 5600
F 0 "#PWR04" H 2400 5450 50 0001 C CNN
F 1 "+3.3V" H 2415 5773 50 0000 C CNN
F 2 "" H 2400 5600 50 0001 C CNN
F 3 "" H 2400 5600 50 0001 C CNN
1 2400 5600
1 0 0 -1
$EndComp
Wire Wire Line
2400 5700 2400 5600
Text GLabel 3000 6200 2 50 Input ~ 0
TEENSY_CLK
Wire Wire Line
3000 6000 2900 6000
Text GLabel 3000 6100 2 50 Input ~ 0
TEENSY_INTR
Wire Wire Line
3000 6100 2900 6100
Text GLabel 3000 6000 2 50 Input ~ 0
TEENSY_NMI
Wire Wire Line
3000 6200 2900 6200
Text GLabel 3000 6400 2 50 Input ~ 0
TEENSY_RESET
Wire Wire Line
3000 6300 2900 6300
Text GLabel 3000 6300 2 50 Input ~ 0
TEENSY_WAIT
Wire Wire Line
3000 6400 2900 6400
Wire Wire Line
2400 7350 1800 7350
Wire Wire Line
1800 7350 1800 7000
Wire Wire Line
1800 7000 1900 7000
Connection ~ 2400 7350
Wire Wire Line
2400 7350 2400 7300
Text GLabel 1750 6100 0 50 Input ~ 0
CPU_INTR
Text GLabel 1750 6000 0 50 Input ~ 0
CPU_NMI
Text GLabel 1750 6400 0 50 Input ~ 0
CPU_RESET
Text GLabel 1750 6200 0 50 Input ~ 0
CPU_CLK
$Comp
L power:+3.3V #PWR01
U 1 1 61CC9A6D
P 1700 6900
F 0 "#PWR01" H 1700 6750 50 0001 C CNN
F 1 "+3.3V" V 1700 7150 50 0000 C CNN
F 2 "" H 1700 6900 50 0001 C CNN
F 3 "" H 1700 6900 50 0001 C CNN
1 1700 6900
0 -1 -1 0
$EndComp
Wire Wire Line
1700 6900 1900 6900
Wire Wire Line
1900 6000 1750 6000
Wire Wire Line
1900 6200 1750 6200
Wire Wire Line
1900 6300 1750 6300
Wire Wire Line
1750 6100 1900 6100
Text GLabel 5900 6450 2 50 Input ~ 0
TEENSY_AD2_IN
Text GLabel 5900 6350 2 50 Input ~ 0
TEENSY_AD3_IN
Text GLabel 5900 6250 2 50 Input ~ 0
TEENSY_AD4_IN
Text GLabel 5900 6650 2 50 Input ~ 0
TEENSY_AD0_IN
Text GLabel 5900 6550 2 50 Input ~ 0
TEENSY_AD1_IN
Wire Wire Line
1900 6400 1750 6400
Text GLabel 1750 6300 0 50 Input ~ 0
CPU_WAIT
NoConn ~ 3950 3200
NoConn ~ 3950 3700
NoConn ~ 1550 2000
NoConn ~ 1550 2100
NoConn ~ 2900 6500
NoConn ~ 2900 6600
NoConn ~ 2900 6700
Wire Wire Line
3850 1900 4000 1900
$Comp
L power:+5V #PWR06
U 1 1 61CF31EE
P 4000 1900
F 0 "#PWR06" H 4000 1750 50 0001 C CNN
F 1 "+5V" V 4000 2100 50 0000 C CNN
F 2 "" H 4000 1900 50 0001 C CNN
F 3 "" H 4000 1900 50 0001 C CNN
1 4000 1900
0 1 1 0
$EndComp
$Comp
L power:GND #PWR0101
U 1 1 62113383
P 1800 6700
F 0 "#PWR0101" H 1800 6450 50 0001 C CNN
F 1 "GND" V 1800 6500 50 0000 C CNN
F 2 "" H 1800 6700 50 0001 C CNN
F 3 "" H 1800 6700 50 0001 C CNN
1 1800 6700
0 1 1 0
$EndComp
Wire Wire Line
1800 6700 1850 6700
Wire Wire Line
1850 6700 1850 6600
Wire Wire Line
1850 6600 1900 6600
Connection ~ 1850 6700
Wire Wire Line
1850 6700 1900 6700
Wire Wire Line
1900 6500 1850 6500
Wire Wire Line
1850 6500 1850 6600
Connection ~ 1850 6600
Text Notes 7250 7050 0 157 ~ 0
MicroCore Labs\nMCLZ8
$Comp
L power:+3.3V #PWR0102
U 1 1 6229E980
P 4600 6850
F 0 "#PWR0102" H 4600 6700 50 0001 C CNN
F 1 "+3.3V" V 4600 7100 50 0000 C CNN
F 2 "" H 4600 6850 50 0001 C CNN
F 3 "" H 4600 6850 50 0001 C CNN
1 4600 6850
0 -1 -1 0
$EndComp
Wire Wire Line
4600 6850 4800 6850
Wire Wire Line
9550 5100 9550 5250
$Comp
L CPU:Z80CPU U6
U 1 1 622909D1
P 9550 3600
F 0 "U6" H 9156 5281 50 0000 C CNN
F 1 "Z80CPU" H 9077 5190 50 0000 C CNN
F 2 "Package_DIP:DIP-40_W15.24mm" H 9550 4000 50 0001 C CNN
F 3 "www.zilog.com/manage_directlink.php?filepath=docs/z80/um0080" H 9550 4000 50 0001 C CNN
1 9550 3600
1 0 0 -1
$EndComp
Text GLabel 10350 4100 2 50 Input ~ 0
CPU_AD0
Text GLabel 10350 4200 2 50 Input ~ 0
CPU_AD1
Text GLabel 10350 4300 2 50 Input ~ 0
CPU_AD2
Text GLabel 10350 4400 2 50 Input ~ 0
CPU_AD3
Text GLabel 10350 4500 2 50 Input ~ 0
CPU_AD4
Text GLabel 10350 4600 2 50 Input ~ 0
CPU_AD5
Text GLabel 10350 4700 2 50 Input ~ 0
CPU_AD6
Text GLabel 10350 4800 2 50 Input ~ 0
CPU_AD7
Wire Wire Line
10350 4800 10250 4800
Wire Wire Line
10350 4700 10250 4700
Wire Wire Line
10350 4600 10250 4600
Wire Wire Line
10350 4500 10250 4500
Wire Wire Line
10350 4400 10250 4400
Wire Wire Line
10350 4300 10250 4300
Wire Wire Line
10350 4200 10250 4200
Wire Wire Line
10350 4100 10250 4100
Wire Wire Line
8850 2700 8750 2700
Wire Wire Line
8850 3600 8750 3600
Wire Wire Line
8850 2400 8750 2400
Wire Wire Line
8850 3000 8750 3000
Wire Wire Line
8850 3100 8750 3100
Wire Wire Line
1450 3100 1650 3100
Wire Wire Line
1450 3800 1650 3800
Wire Wire Line
1450 3900 1650 3900
Wire Wire Line
1450 3700 1650 3700
Wire Wire Line
1450 3600 1650 3600
Wire Wire Line
1450 3500 1650 3500
Wire Wire Line
1450 3400 1650 3400
Wire Wire Line
5900 1250 6000 1250
Wire Wire Line
5900 1350 6000 1350
Wire Wire Line
5900 1450 6000 1450
Wire Wire Line
5900 1550 6000 1550
Wire Wire Line
5900 1650 6000 1650
Wire Wire Line
5900 1750 6000 1750
Wire Wire Line
5900 1850 6000 1850
Wire Wire Line
5900 1950 6000 1950
$Comp
L power:GND #PWR0103
U 1 1 622D405C
P 6500 2650
F 0 "#PWR0103" H 6500 2400 50 0001 C CNN
F 1 "GND" H 6505 2477 50 0000 C CNN
F 2 "" H 6500 2650 50 0001 C CNN
F 3 "" H 6500 2650 50 0001 C CNN
1 6500 2650
1 0 0 -1
$EndComp
$Comp
L power:+3.3V #PWR0104
U 1 1 622D4062
P 6500 850
F 0 "#PWR0104" H 6500 700 50 0001 C CNN
F 1 "+3.3V" H 6515 1023 50 0000 C CNN
F 2 "" H 6500 850 50 0001 C CNN
F 3 "" H 6500 850 50 0001 C CNN
1 6500 850
1 0 0 -1
$EndComp
Wire Wire Line
6500 950 6500 850
Wire Wire Line
5900 2150 6000 2150
Text GLabel 7100 1250 2 50 Input ~ 0
CPU_A0
Text GLabel 7100 1350 2 50 Input ~ 0
CPU_A1
Text GLabel 7100 1450 2 50 Input ~ 0
CPU_A2
Text GLabel 7100 1550 2 50 Input ~ 0
CPU_A3
Text GLabel 7100 1650 2 50 Input ~ 0
CPU_A4
Text GLabel 7100 1750 2 50 Input ~ 0
CPU_A5
Text GLabel 7100 1850 2 50 Input ~ 0
CPU_A6
Text GLabel 7100 1950 2 50 Input ~ 0
CPU_A7
Wire Wire Line
7100 1950 7000 1950
Wire Wire Line
7100 1850 7000 1850
Wire Wire Line
7100 1750 7000 1750
Wire Wire Line
7100 1650 7000 1650
Wire Wire Line
7100 1550 7000 1550
Wire Wire Line
7100 1450 7000 1450
Wire Wire Line
7100 1350 7000 1350
Wire Wire Line
7100 1250 7000 1250
Text GLabel 5900 1250 0 50 Input ~ 0
TEENSY_AD0_OUT
Text GLabel 5900 1350 0 50 Input ~ 0
TEENSY_AD1_OUT
Text GLabel 5900 1450 0 50 Input ~ 0
TEENSY_AD2_OUT
Text GLabel 5900 1550 0 50 Input ~ 0
TEENSY_AD3_OUT
Text GLabel 5900 1650 0 50 Input ~ 0
TEENSY_AD4_OUT
Text GLabel 5900 1750 0 50 Input ~ 0
TEENSY_AD5_OUT
Text GLabel 5900 1850 0 50 Input ~ 0
TEENSY_AD6_OUT
Text GLabel 5900 1950 0 50 Input ~ 0
TEENSY_AD7_OUT
Wire Wire Line
6500 2550 6500 2600
$Comp
L 74xx:74LS573 U7
U 1 1 622D408B
P 6500 1750
F 0 "U7" H 6100 2500 50 0000 C CNN
F 1 "SN74LVC573A" H 6100 2400 50 0000 C CNN
F 2 "Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm" H 6500 1750 50 0001 C CNN
F 3 "74xx/74hc573.pdf" H 6500 1750 50 0001 C CNN
1 6500 1750
1 0 0 -1
$EndComp
Wire Wire Line
5900 2250 6000 2250
Text GLabel 5900 2150 0 50 Input ~ 0
TEENSY_ADDR_LATCH_n
Wire Wire Line
6500 2600 5900 2600
Wire Wire Line
5900 2600 5900 2250
Connection ~ 6500 2600
Wire Wire Line
6500 2600 6500 2650
Text GLabel 1450 3100 0 50 Input ~ 0
TEENSY_ADDR_LATCH_n
Text GLabel 8750 3400 0 50 Input ~ 0
CPU_M1
Wire Wire Line
8850 3400 8750 3400
Text GLabel 1450 3200 0 50 Input ~ 0
CPU_M1
Wire Wire Line
1450 3200 1650 3200
Text GLabel 8750 3700 0 50 Input ~ 0
CPU_HALT
Wire Wire Line
8850 3700 8750 3700
Text GLabel 1450 3400 0 50 Input ~ 0
CPU_HALT
Text GLabel 8750 4100 0 50 Input ~ 0
CPU_RD
Wire Wire Line
8850 4100 8750 4100
Text GLabel 8750 4200 0 50 Input ~ 0
CPU_WR
Wire Wire Line
8850 4200 8750 4200
Text GLabel 8750 4300 0 50 Input ~ 0
CPU_MREQ
Wire Wire Line
8850 4300 8750 4300
Text GLabel 8750 4400 0 50 Input ~ 0
CPU_IOREQ
Wire Wire Line
8850 4400 8750 4400
Text GLabel 1450 3500 0 50 Input ~ 0
CPU_RD
Text GLabel 1450 3600 0 50 Input ~ 0
CPU_WR
Text GLabel 1450 3700 0 50 Input ~ 0
CPU_MREQ
Text GLabel 1450 3800 0 50 Input ~ 0
CPU_IOREQ
Text GLabel 1450 3900 0 50 Input ~ 0
CPU_REFRESH
Text GLabel 8750 3500 0 50 Input ~ 0
CPU_REFRESH
Wire Wire Line
8850 3500 8750 3500
$EndSCHEMATC

936
MCLZ8/PCB/MCLZ8_PCB.sch-bak Normal file
View File

@ -0,0 +1,936 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L power:GND #PWR015
U 1 1 61B99BEA
P 9550 5250
F 0 "#PWR015" H 9550 5000 50 0001 C CNN
F 1 "GND" H 9555 5077 50 0000 C CNN
F 2 "" H 9550 5250 50 0001 C CNN
F 3 "" H 9550 5250 50 0001 C CNN
1 9550 5250
1 0 0 -1
$EndComp
Text GLabel 10350 2400 2 50 Input ~ 0
CPU_A0
Wire Wire Line
10350 2400 10250 2400
Text GLabel 10350 2500 2 50 Input ~ 0
CPU_A1
Wire Wire Line
10350 2500 10250 2500
Text GLabel 10350 2600 2 50 Input ~ 0
CPU_A2
Wire Wire Line
10350 2600 10250 2600
Text GLabel 10350 2700 2 50 Input ~ 0
CPU_A3
Wire Wire Line
10350 2700 10250 2700
Text GLabel 10350 2800 2 50 Input ~ 0
CPU_A4
Wire Wire Line
10350 2800 10250 2800
Text GLabel 10350 2900 2 50 Input ~ 0
CPU_A5
Wire Wire Line
10350 2900 10250 2900
Text GLabel 10350 3000 2 50 Input ~ 0
CPU_A6
Wire Wire Line
10350 3000 10250 3000
Text GLabel 10350 3100 2 50 Input ~ 0
CPU_A7
Wire Wire Line
10350 3100 10250 3100
Text GLabel 10350 3200 2 50 Input ~ 0
CPU_A8
Wire Wire Line
10350 3200 10250 3200
Text GLabel 10350 3300 2 50 Input ~ 0
CPU_A9
Wire Wire Line
10350 3300 10250 3300
Text GLabel 10350 3400 2 50 Input ~ 0
CPU_A10
Wire Wire Line
10350 3400 10250 3400
Text GLabel 10350 3500 2 50 Input ~ 0
CPU_A11
Wire Wire Line
10350 3500 10250 3500
Text GLabel 10350 3600 2 50 Input ~ 0
CPU_A12
Wire Wire Line
10350 3600 10250 3600
Text GLabel 10350 3700 2 50 Input ~ 0
CPU_A13
Wire Wire Line
10350 3700 10250 3700
Text GLabel 10350 3800 2 50 Input ~ 0
CPU_A14
Wire Wire Line
10350 3800 10250 3800
Text GLabel 10350 3900 2 50 Input ~ 0
CPU_A15
Wire Wire Line
10350 3900 10250 3900
Text GLabel 8750 3100 0 50 Input ~ 0
CPU_INTR
Text GLabel 8750 3000 0 50 Input ~ 0
CPU_NMI
Text GLabel 8750 2400 0 50 Input ~ 0
CPU_RESET
Text GLabel 8750 3600 0 50 Input ~ 0
CPU_WAIT
Text GLabel 8750 2700 0 50 Input ~ 0
CPU_CLK
$Comp
L power:+5V #PWR016
U 1 1 61BB1FD6
P 9550 1950
F 0 "#PWR016" H 9550 1800 50 0001 C CNN
F 1 "+5V" H 9565 2123 50 0000 C CNN
F 2 "" H 9550 1950 50 0001 C CNN
F 3 "" H 9550 1950 50 0001 C CNN
1 9550 1950
1 0 0 -1
$EndComp
Wire Wire Line
9550 2100 9550 1950
Wire Wire Line
5900 3600 6000 3600
Wire Wire Line
5900 3700 6000 3700
Wire Wire Line
5900 3800 6000 3800
Wire Wire Line
5900 3900 6000 3900
Wire Wire Line
5900 4000 6000 4000
Wire Wire Line
5900 4100 6000 4100
Wire Wire Line
5900 4200 6000 4200
Wire Wire Line
5900 4300 6000 4300
$Comp
L power:GND #PWR012
U 1 1 61C0E7B7
P 6500 5000
F 0 "#PWR012" H 6500 4750 50 0001 C CNN
F 1 "GND" H 6505 4827 50 0000 C CNN
F 2 "" H 6500 5000 50 0001 C CNN
F 3 "" H 6500 5000 50 0001 C CNN
1 6500 5000
1 0 0 -1
$EndComp
$Comp
L power:+3.3V #PWR011
U 1 1 61C0E7BE
P 6500 3200
F 0 "#PWR011" H 6500 3050 50 0001 C CNN
F 1 "+3.3V" H 6515 3373 50 0000 C CNN
F 2 "" H 6500 3200 50 0001 C CNN
F 3 "" H 6500 3200 50 0001 C CNN
1 6500 3200
1 0 0 -1
$EndComp
Wire Wire Line
6500 3300 6500 3200
Wire Wire Line
5900 4500 6000 4500
Text GLabel 7100 3600 2 50 Input ~ 0
CPU_AD0
Text GLabel 7100 3700 2 50 Input ~ 0
CPU_AD1
Text GLabel 7100 3800 2 50 Input ~ 0
CPU_AD2
Text GLabel 7100 3900 2 50 Input ~ 0
CPU_AD3
Text GLabel 7100 4000 2 50 Input ~ 0
CPU_AD4
Text GLabel 7100 4100 2 50 Input ~ 0
CPU_AD5
Text GLabel 7100 4200 2 50 Input ~ 0
CPU_AD6
Text GLabel 7100 4300 2 50 Input ~ 0
CPU_AD7
Wire Wire Line
7100 4300 7000 4300
Wire Wire Line
7100 4200 7000 4200
Wire Wire Line
7100 4100 7000 4100
Wire Wire Line
7100 4000 7000 4000
Wire Wire Line
7100 3900 7000 3900
Wire Wire Line
7100 3800 7000 3800
Wire Wire Line
7100 3700 7000 3700
Wire Wire Line
7100 3600 7000 3600
Text GLabel 5900 3600 0 50 Input ~ 0
TEENSY_AD0_OUT
Text GLabel 5900 3700 0 50 Input ~ 0
TEENSY_AD1_OUT
Text GLabel 5900 3800 0 50 Input ~ 0
TEENSY_AD2_OUT
Text GLabel 5900 3900 0 50 Input ~ 0
TEENSY_AD3_OUT
Text GLabel 5900 4000 0 50 Input ~ 0
TEENSY_AD4_OUT
Text GLabel 5900 4100 0 50 Input ~ 0
TEENSY_AD5_OUT
Text GLabel 5900 4200 0 50 Input ~ 0
TEENSY_AD6_OUT
Text GLabel 5900 4300 0 50 Input ~ 0
TEENSY_AD7_OUT
$Comp
L power:+3.3V #PWR010
U 1 1 61C82B60
P 5900 4500
F 0 "#PWR010" H 5900 4350 50 0001 C CNN
F 1 "+3.3V" V 5900 4750 50 0000 C CNN
F 2 "" H 5900 4500 50 0001 C CNN
F 3 "" H 5900 4500 50 0001 C CNN
1 5900 4500
0 -1 -1 0
$EndComp
Wire Wire Line
6500 4900 6500 5000
Wire Wire Line
5900 4600 6000 4600
Text GLabel 5900 4600 0 50 Input ~ 0
TEENSY_DATA_OE_n
Text Notes 1300 1000 0 276 ~ 55
MCLZ8
Text GLabel 4700 6650 0 50 Input ~ 0
CPU_AD0
Wire Wire Line
4700 5950 4800 5950
Text GLabel 4700 6550 0 50 Input ~ 0
CPU_AD1
Wire Wire Line
4700 6050 4800 6050
Text GLabel 4700 6450 0 50 Input ~ 0
CPU_AD2
Wire Wire Line
4700 6150 4800 6150
Text GLabel 4700 6350 0 50 Input ~ 0
CPU_AD3
Wire Wire Line
4700 6250 4800 6250
Text GLabel 4700 6250 0 50 Input ~ 0
CPU_AD4
Wire Wire Line
4700 6350 4800 6350
Text GLabel 4700 6150 0 50 Input ~ 0
CPU_AD5
Wire Wire Line
4700 6450 4800 6450
Text GLabel 4700 6050 0 50 Input ~ 0
CPU_AD6
Wire Wire Line
4700 6550 4800 6550
Text GLabel 4700 5950 0 50 Input ~ 0
CPU_AD7
Wire Wire Line
4700 6650 4800 6650
$Comp
L power:GND #PWR014
U 1 1 61BB88CC
P 5300 7350
F 0 "#PWR014" H 5300 7100 50 0001 C CNN
F 1 "GND" H 5305 7177 50 0000 C CNN
F 2 "" H 5300 7350 50 0001 C CNN
F 3 "" H 5300 7350 50 0001 C CNN
1 5300 7350
1 0 0 -1
$EndComp
Wire Wire Line
5300 7350 5300 7300
$Comp
L power:+3.3V #PWR013
U 1 1 61BB9EEB
P 5300 5550
F 0 "#PWR013" H 5300 5400 50 0001 C CNN
F 1 "+3.3V" H 5315 5723 50 0000 C CNN
F 2 "" H 5300 5550 50 0001 C CNN
F 3 "" H 5300 5550 50 0001 C CNN
1 5300 5550
1 0 0 -1
$EndComp
Wire Wire Line
5300 5650 5300 5550
Wire Wire Line
5900 5950 5800 5950
Wire Wire Line
5900 6050 5800 6050
Wire Wire Line
5900 6150 5800 6150
Wire Wire Line
5900 6250 5800 6250
Wire Wire Line
5900 6350 5800 6350
Text GLabel 5900 6150 2 50 Input ~ 0
TEENSY_AD5_IN
Wire Wire Line
5900 6450 5800 6450
Text GLabel 5900 6050 2 50 Input ~ 0
TEENSY_AD6_IN
Wire Wire Line
5900 6550 5800 6550
Text GLabel 5900 5950 2 50 Input ~ 0
TEENSY_AD7_IN
Wire Wire Line
5900 6650 5800 6650
Wire Wire Line
5300 7300 4700 7300
Wire Wire Line
4700 7300 4700 6950
Wire Wire Line
4700 6950 4800 6950
Connection ~ 5300 7300
Wire Wire Line
5300 7300 5300 7250
Text GLabel 3950 2700 2 50 Input ~ 0
TEENSY_AD0_IN
Text GLabel 3950 2800 2 50 Input ~ 0
TEENSY_AD1_IN
Text GLabel 3950 2900 2 50 Input ~ 0
TEENSY_AD2_IN
Text GLabel 3950 3000 2 50 Input ~ 0
TEENSY_AD3_IN
Text GLabel 3950 3100 2 50 Input ~ 0
TEENSY_AD4_IN
Wire Wire Line
1550 2100 1650 2100
Wire Wire Line
1550 2200 1650 2200
Wire Wire Line
1550 2300 1650 2300
Wire Wire Line
1550 2400 1650 2400
$Comp
L power:GND #PWR03
U 1 1 61CD3DF8
P 1550 1900
F 0 "#PWR03" H 1550 1650 50 0001 C CNN
F 1 "GND" V 1550 1700 50 0000 C CNN
F 2 "" H 1550 1900 50 0001 C CNN
F 3 "" H 1550 1900 50 0001 C CNN
1 1550 1900
0 1 1 0
$EndComp
Wire Wire Line
1550 1900 1650 1900
$Comp
L power:GND #PWR07
U 1 1 61CE84A9
P 4000 2000
F 0 "#PWR07" H 4000 1750 50 0001 C CNN
F 1 "GND" V 4000 1800 50 0000 C CNN
F 2 "" H 4000 2000 50 0001 C CNN
F 3 "" H 4000 2000 50 0001 C CNN
1 4000 2000
0 -1 -1 0
$EndComp
Wire Wire Line
3850 2000 4000 2000
$Comp
L power:+3.3V #PWR08
U 1 1 61CED9E3
P 4000 2100
F 0 "#PWR08" H 4000 1950 50 0001 C CNN
F 1 "+3.3V" V 4000 2350 50 0000 C CNN
F 2 "" H 4000 2100 50 0001 C CNN
F 3 "" H 4000 2100 50 0001 C CNN
1 4000 2100
0 1 1 0
$EndComp
Wire Wire Line
3850 2100 4000 2100
$Comp
L power:GND #PWR09
U 1 1 61D0CC7F
P 4000 3300
F 0 "#PWR09" H 4000 3050 50 0001 C CNN
F 1 "GND" V 4000 3100 50 0000 C CNN
F 2 "" H 4000 3300 50 0001 C CNN
F 3 "" H 4000 3300 50 0001 C CNN
1 4000 3300
0 -1 -1 0
$EndComp
Wire Wire Line
3850 3300 4000 3300
$Comp
L power:+3.3V #PWR02
U 1 1 61D121B1
P 1500 3300
F 0 "#PWR02" H 1500 3150 50 0001 C CNN
F 1 "+3.3V" V 1500 3550 50 0000 C CNN
F 2 "" H 1500 3300 50 0001 C CNN
F 3 "" H 1500 3300 50 0001 C CNN
1 1500 3300
0 -1 -1 0
$EndComp
Wire Wire Line
1650 3300 1500 3300
Wire Wire Line
1550 2500 1650 2500
Wire Wire Line
1550 2600 1650 2600
Wire Wire Line
1550 2700 1650 2700
Wire Wire Line
1550 2800 1650 2800
Wire Wire Line
1550 2900 1650 2900
Wire Wire Line
1550 3000 1650 3000
Wire Wire Line
1550 4000 1650 4000
Wire Wire Line
1550 4100 1650 4100
Wire Wire Line
1550 4200 1650 4200
Wire Wire Line
3850 2200 3950 2200
Wire Wire Line
3850 2300 3950 2300
Wire Wire Line
3850 2400 3950 2400
Wire Wire Line
3850 2500 3950 2500
Wire Wire Line
3850 2600 3950 2600
Wire Wire Line
3850 2700 3950 2700
Wire Wire Line
3850 2800 3950 2800
Wire Wire Line
3850 2900 3950 2900
Wire Wire Line
3850 3900 3950 3900
Wire Wire Line
3850 4000 3950 4000
Wire Wire Line
3850 4100 3950 4100
Wire Wire Line
3850 4200 3950 4200
Wire Wire Line
3850 3500 3950 3500
Wire Wire Line
3850 3600 3950 3600
Wire Wire Line
3850 3700 3950 3700
Wire Wire Line
3850 3800 3950 3800
Wire Wire Line
3850 3400 3950 3400
Wire Wire Line
3850 3000 3950 3000
Wire Wire Line
3850 3100 3950 3100
Wire Wire Line
3850 3200 3950 3200
Wire Wire Line
1550 2000 1650 2000
Text GLabel 1550 2200 0 50 Input ~ 0
TEENSY_DATA_OE_n
Text GLabel 1550 2300 0 50 Input ~ 0
TEENSY_AD0_OUT
Text GLabel 1550 2400 0 50 Input ~ 0
TEENSY_AD1_OUT
Text GLabel 1550 2500 0 50 Input ~ 0
TEENSY_AD2_OUT
Text GLabel 1550 2600 0 50 Input ~ 0
TEENSY_AD3_OUT
Text GLabel 1550 2700 0 50 Input ~ 0
TEENSY_AD4_OUT
Text GLabel 1550 2800 0 50 Input ~ 0
TEENSY_AD5_OUT
Text GLabel 1550 2900 0 50 Input ~ 0
TEENSY_AD6_OUT
Text GLabel 1550 3000 0 50 Input ~ 0
TEENSY_AD7_OUT
Text GLabel 1550 4000 0 50 Input ~ 0
CPU_A15
Text GLabel 1550 4100 0 50 Input ~ 0
CPU_A14
Text GLabel 1550 4200 0 50 Input ~ 0
CPU_A13
Text GLabel 3950 4200 2 50 Input ~ 0
CPU_A12
Text GLabel 3950 4100 2 50 Input ~ 0
CPU_A11
Text GLabel 3950 4000 2 50 Input ~ 0
CPU_A10
Text GLabel 3950 3900 2 50 Input ~ 0
CPU_A9
Text GLabel 3950 3800 2 50 Input ~ 0
CPU_A8
Text GLabel 3950 3600 2 50 Input ~ 0
TEENSY_AD7_IN
Text GLabel 3950 3500 2 50 Input ~ 0
TEENSY_AD6_IN
Text GLabel 3950 3400 2 50 Input ~ 0
TEENSY_AD5_IN
Text GLabel 3950 2400 2 50 Input ~ 0
TEENSY_CLK
Text GLabel 3950 2500 2 50 Input ~ 0
TEENSY_INTR
Text GLabel 3950 2600 2 50 Input ~ 0
TEENSY_NMI
Text GLabel 3950 2200 2 50 Input ~ 0
TEENSY_RESET
Text GLabel 3950 2300 2 50 Input ~ 0
TEENSY_WAIT
$Comp
L teensy:Teensy4.1 U1
U 1 1 61B9A39C
P 2750 4050
F 0 "U1" H 2750 6615 50 0000 C CNN
F 1 "Teensy4.1" H 2750 6524 50 0000 C CNN
F 2 "Teensy:Teensy41_Ted_Modified" H 2350 4450 50 0001 C CNN
F 3 "" H 2350 4450 50 0001 C CNN
1 2750 4050
1 0 0 -1
$EndComp
$Comp
L 74xx:74LS573 U3
U 1 1 61B9DB3E
P 5300 6450
F 0 "U3" H 4900 7200 50 0000 C CNN
F 1 "SN74LVC573A" H 4850 7100 50 0000 C CNN
F 2 "Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm" H 5300 6450 50 0001 C CNN
F 3 "74xx/74hc573.pdf" H 5300 6450 50 0001 C CNN
1 5300 6450
1 0 0 -1
$EndComp
$Comp
L 74xx:74LS573 U5
U 1 1 61C0E7A1
P 6500 4100
F 0 "U5" H 6100 4850 50 0000 C CNN
F 1 "SN74LVC573A" H 6100 4750 50 0000 C CNN
F 2 "Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm" H 6500 4100 50 0001 C CNN
F 3 "74xx/74hc573.pdf" H 6500 4100 50 0001 C CNN
1 6500 4100
1 0 0 -1
$EndComp
$Comp
L 74xx:74LS573 U4
U 1 1 61C1662B
P 2400 6500
F 0 "U4" H 2000 7250 50 0000 C CNN
F 1 "SN74LVC573A" H 2000 7150 50 0000 C CNN
F 2 "Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm" H 2400 6500 50 0001 C CNN
F 3 "74xx/74hc573.pdf" H 2400 6500 50 0001 C CNN
1 2400 6500
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR05
U 1 1 61C16641
P 2400 7400
F 0 "#PWR05" H 2400 7150 50 0001 C CNN
F 1 "GND" H 2405 7227 50 0000 C CNN
F 2 "" H 2400 7400 50 0001 C CNN
F 3 "" H 2400 7400 50 0001 C CNN
1 2400 7400
1 0 0 -1
$EndComp
Wire Wire Line
2400 7400 2400 7350
$Comp
L power:+3.3V #PWR04
U 1 1 61C16648
P 2400 5600
F 0 "#PWR04" H 2400 5450 50 0001 C CNN
F 1 "+3.3V" H 2415 5773 50 0000 C CNN
F 2 "" H 2400 5600 50 0001 C CNN
F 3 "" H 2400 5600 50 0001 C CNN
1 2400 5600
1 0 0 -1
$EndComp
Wire Wire Line
2400 5700 2400 5600
Text GLabel 3000 6200 2 50 Input ~ 0
TEENSY_CLK
Wire Wire Line
3000 6000 2900 6000
Text GLabel 3000 6100 2 50 Input ~ 0
TEENSY_INTR
Wire Wire Line
3000 6100 2900 6100
Text GLabel 3000 6000 2 50 Input ~ 0
TEENSY_NMI
Wire Wire Line
3000 6200 2900 6200
Text GLabel 3000 6400 2 50 Input ~ 0
TEENSY_RESET
Wire Wire Line
3000 6300 2900 6300
Text GLabel 3000 6300 2 50 Input ~ 0
TEENSY_WAIT
Wire Wire Line
3000 6400 2900 6400
Wire Wire Line
2400 7350 1800 7350
Wire Wire Line
1800 7350 1800 7000
Wire Wire Line
1800 7000 1900 7000
Connection ~ 2400 7350
Wire Wire Line
2400 7350 2400 7300
Text GLabel 1750 6100 0 50 Input ~ 0
CPU_INTR
Text GLabel 1750 6000 0 50 Input ~ 0
CPU_NMI
Text GLabel 1750 6400 0 50 Input ~ 0
CPU_RESET
Text GLabel 1750 6200 0 50 Input ~ 0
CPU_CLK
$Comp
L power:+3.3V #PWR01
U 1 1 61CC9A6D
P 1700 6900
F 0 "#PWR01" H 1700 6750 50 0001 C CNN
F 1 "+3.3V" V 1700 7150 50 0000 C CNN
F 2 "" H 1700 6900 50 0001 C CNN
F 3 "" H 1700 6900 50 0001 C CNN
1 1700 6900
0 -1 -1 0
$EndComp
Wire Wire Line
1700 6900 1900 6900
Wire Wire Line
1900 6000 1750 6000
Wire Wire Line
1900 6200 1750 6200
Wire Wire Line
1900 6300 1750 6300
Wire Wire Line
1750 6100 1900 6100
Text GLabel 5900 6450 2 50 Input ~ 0
TEENSY_AD2_IN
Text GLabel 5900 6350 2 50 Input ~ 0
TEENSY_AD3_IN
Text GLabel 5900 6250 2 50 Input ~ 0
TEENSY_AD4_IN
Text GLabel 5900 6650 2 50 Input ~ 0
TEENSY_AD0_IN
Text GLabel 5900 6550 2 50 Input ~ 0
TEENSY_AD1_IN
Wire Wire Line
1900 6400 1750 6400
Text GLabel 1750 6300 0 50 Input ~ 0
CPU_WAIT
NoConn ~ 3950 3200
NoConn ~ 3950 3700
NoConn ~ 1550 2000
NoConn ~ 1550 2100
NoConn ~ 2900 6500
NoConn ~ 2900 6600
NoConn ~ 2900 6700
Wire Wire Line
3850 1900 4000 1900
$Comp
L power:+5V #PWR06
U 1 1 61CF31EE
P 4000 1900
F 0 "#PWR06" H 4000 1750 50 0001 C CNN
F 1 "+5V" V 4000 2100 50 0000 C CNN
F 2 "" H 4000 1900 50 0001 C CNN
F 3 "" H 4000 1900 50 0001 C CNN
1 4000 1900
0 1 1 0
$EndComp
$Comp
L power:GND #PWR0101
U 1 1 62113383
P 1800 6700
F 0 "#PWR0101" H 1800 6450 50 0001 C CNN
F 1 "GND" V 1800 6500 50 0000 C CNN
F 2 "" H 1800 6700 50 0001 C CNN
F 3 "" H 1800 6700 50 0001 C CNN
1 1800 6700
0 1 1 0
$EndComp
Wire Wire Line
1800 6700 1850 6700
Wire Wire Line
1850 6700 1850 6600
Wire Wire Line
1850 6600 1900 6600
Connection ~ 1850 6700
Wire Wire Line
1850 6700 1900 6700
Wire Wire Line
1900 6500 1850 6500
Wire Wire Line
1850 6500 1850 6600
Connection ~ 1850 6600
Text Notes 7250 7050 0 157 ~ 0
MicroCore Labs\nMCLZ8
$Comp
L power:+3.3V #PWR0102
U 1 1 6229E980
P 4600 6850
F 0 "#PWR0102" H 4600 6700 50 0001 C CNN
F 1 "+3.3V" V 4600 7100 50 0000 C CNN
F 2 "" H 4600 6850 50 0001 C CNN
F 3 "" H 4600 6850 50 0001 C CNN
1 4600 6850
0 -1 -1 0
$EndComp
Wire Wire Line
4600 6850 4800 6850
Wire Wire Line
9550 5100 9550 5250
$Comp
L CPU:Z80CPU U6
U 1 1 622909D1
P 9550 3600
F 0 "U6" H 9156 5281 50 0000 C CNN
F 1 "Z80CPU" H 9077 5190 50 0000 C CNN
F 2 "Package_DIP:DIP-40_W15.24mm" H 9550 4000 50 0001 C CNN
F 3 "www.zilog.com/manage_directlink.php?filepath=docs/z80/um0080" H 9550 4000 50 0001 C CNN
1 9550 3600
1 0 0 -1
$EndComp
Text GLabel 10350 4100 2 50 Input ~ 0
CPU_AD0
Text GLabel 10350 4200 2 50 Input ~ 0
CPU_AD1
Text GLabel 10350 4300 2 50 Input ~ 0
CPU_AD2
Text GLabel 10350 4400 2 50 Input ~ 0
CPU_AD3
Text GLabel 10350 4500 2 50 Input ~ 0
CPU_AD4
Text GLabel 10350 4600 2 50 Input ~ 0
CPU_AD5
Text GLabel 10350 4700 2 50 Input ~ 0
CPU_AD6
Text GLabel 10350 4800 2 50 Input ~ 0
CPU_AD7
Wire Wire Line
10350 4800 10250 4800
Wire Wire Line
10350 4700 10250 4700
Wire Wire Line
10350 4600 10250 4600
Wire Wire Line
10350 4500 10250 4500
Wire Wire Line
10350 4400 10250 4400
Wire Wire Line
10350 4300 10250 4300
Wire Wire Line
10350 4200 10250 4200
Wire Wire Line
10350 4100 10250 4100
Wire Wire Line
8850 2700 8750 2700
Wire Wire Line
8850 3600 8750 3600
Wire Wire Line
8850 2400 8750 2400
Wire Wire Line
8850 3000 8750 3000
Wire Wire Line
8850 3100 8750 3100
Wire Wire Line
1450 3100 1650 3100
Wire Wire Line
1450 3800 1650 3800
Wire Wire Line
1450 3900 1650 3900
Wire Wire Line
1450 3700 1650 3700
Wire Wire Line
1450 3600 1650 3600
Wire Wire Line
1450 3500 1650 3500
Wire Wire Line
1450 3400 1650 3400
Wire Wire Line
5900 1250 6000 1250
Wire Wire Line
5900 1350 6000 1350
Wire Wire Line
5900 1450 6000 1450
Wire Wire Line
5900 1550 6000 1550
Wire Wire Line
5900 1650 6000 1650
Wire Wire Line
5900 1750 6000 1750
Wire Wire Line
5900 1850 6000 1850
Wire Wire Line
5900 1950 6000 1950
$Comp
L power:GND #PWR0103
U 1 1 622D405C
P 6500 2650
F 0 "#PWR0103" H 6500 2400 50 0001 C CNN
F 1 "GND" H 6505 2477 50 0000 C CNN
F 2 "" H 6500 2650 50 0001 C CNN
F 3 "" H 6500 2650 50 0001 C CNN
1 6500 2650
1 0 0 -1
$EndComp
$Comp
L power:+3.3V #PWR0104
U 1 1 622D4062
P 6500 850
F 0 "#PWR0104" H 6500 700 50 0001 C CNN
F 1 "+3.3V" H 6515 1023 50 0000 C CNN
F 2 "" H 6500 850 50 0001 C CNN
F 3 "" H 6500 850 50 0001 C CNN
1 6500 850
1 0 0 -1
$EndComp
Wire Wire Line
6500 950 6500 850
Wire Wire Line
5900 2150 6000 2150
Text GLabel 7100 1250 2 50 Input ~ 0
CPU_A0
Text GLabel 7100 1350 2 50 Input ~ 0
CPU_A1
Text GLabel 7100 1450 2 50 Input ~ 0
CPU_A2
Text GLabel 7100 1550 2 50 Input ~ 0
CPU_A3
Text GLabel 7100 1650 2 50 Input ~ 0
CPU_A4
Text GLabel 7100 1750 2 50 Input ~ 0
CPU_A5
Text GLabel 7100 1850 2 50 Input ~ 0
CPU_A6
Text GLabel 7100 1950 2 50 Input ~ 0
CPU_A7
Wire Wire Line
7100 1950 7000 1950
Wire Wire Line
7100 1850 7000 1850
Wire Wire Line
7100 1750 7000 1750
Wire Wire Line
7100 1650 7000 1650
Wire Wire Line
7100 1550 7000 1550
Wire Wire Line
7100 1450 7000 1450
Wire Wire Line
7100 1350 7000 1350
Wire Wire Line
7100 1250 7000 1250
Text GLabel 5900 1250 0 50 Input ~ 0
TEENSY_AD0_OUT
Text GLabel 5900 1350 0 50 Input ~ 0
TEENSY_AD1_OUT
Text GLabel 5900 1450 0 50 Input ~ 0
TEENSY_AD2_OUT
Text GLabel 5900 1550 0 50 Input ~ 0
TEENSY_AD3_OUT
Text GLabel 5900 1650 0 50 Input ~ 0
TEENSY_AD4_OUT
Text GLabel 5900 1750 0 50 Input ~ 0
TEENSY_AD5_OUT
Text GLabel 5900 1850 0 50 Input ~ 0
TEENSY_AD6_OUT
Text GLabel 5900 1950 0 50 Input ~ 0
TEENSY_AD7_OUT
Wire Wire Line
6500 2550 6500 2600
$Comp
L 74xx:74LS573 U7
U 1 1 622D408B
P 6500 1750
F 0 "U7" H 6100 2500 50 0000 C CNN
F 1 "SN74LVC573A" H 6100 2400 50 0000 C CNN
F 2 "Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm" H 6500 1750 50 0001 C CNN
F 3 "74xx/74hc573.pdf" H 6500 1750 50 0001 C CNN
1 6500 1750
1 0 0 -1
$EndComp
Wire Wire Line
5900 2250 6000 2250
Text GLabel 5900 2150 0 50 Input ~ 0
TEENSY_ADDR_LATCH_n
Wire Wire Line
6500 2600 5900 2600
Wire Wire Line
5900 2600 5900 2250
Connection ~ 6500 2600
Wire Wire Line
6500 2600 6500 2650
Text GLabel 1450 3100 0 50 Input ~ 0
TEENSY_ADDR_LATCH_n
Text GLabel 8750 3400 0 50 Input ~ 0
CPU_M1
Wire Wire Line
8850 3400 8750 3400
Text GLabel 1450 3200 0 50 Input ~ 0
CPU_M1
Wire Wire Line
1450 3200 1650 3200
Text GLabel 8750 3700 0 50 Input ~ 0
CPU_HALT
Wire Wire Line
8850 3700 8750 3700
Text GLabel 1450 3400 0 50 Input ~ 0
CPU_HALT
Text GLabel 8750 4100 0 50 Input ~ 0
CPU_RD
Wire Wire Line
8850 4100 8750 4100
Text GLabel 8750 4200 0 50 Input ~ 0
CPU_WR
Wire Wire Line
8850 4200 8750 4200
Text GLabel 8750 4300 0 50 Input ~ 0
CPU_MREQ
Wire Wire Line
8850 4300 8750 4300
Text GLabel 8750 4400 0 50 Input ~ 0
CPU_IOREQ
Wire Wire Line
8850 4400 8750 4400
Text GLabel 1450 3500 0 50 Input ~ 0
CPU_RD
Text GLabel 1450 3600 0 50 Input ~ 0
CPU_WR
Text GLabel 1450 3700 0 50 Input ~ 0
CPU_MREQ
Text GLabel 1450 3800 0 50 Input ~ 0
CPU_IOREQ
Text GLabel 1450 3900 0 50 Input ~ 0
CPU_REFRESH
Text GLabel 8750 3500 0 50 Input ~ 0
CPU_REFRESH
Wire Wire Line
8850 3500 8750 3500
$EndSCHEMATC

BIN
MCLZ8/PCB/PCB_Products/MCLZ8_BOM.xlsx Normal file
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Binary file not shown.

111
MCLZ8/PCB/PCB_Products/MCLZ8_PCB-B_Mask.gbs Normal file
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G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.8)-1*
G04 #@! TF.CreationDate,2022-03-12T16:36:43-08:00*
G04 #@! TF.ProjectId,MCLZ8_PCB,4d434c5a-385f-4504-9342-2e6b69636164,rev?*
G04 #@! TF.SameCoordinates,Original*
G04 #@! TF.FileFunction,Soldermask,Bot*
G04 #@! TF.FilePolarity,Negative*
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW (5.1.8)-1) date 2022-03-12 16:36:43*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
%ADD10O,1.600000X1.600000*%
%ADD11R,1.600000X1.600000*%
%ADD12C,1.600000*%
G04 APERTURE END LIST*
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X159212280Y-57929780D03*
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X178290220Y-100944680D03*
X178290220Y-98404680D03*
X178290220Y-95864680D03*
X178290220Y-93324680D03*
X178290220Y-90784680D03*
X178290220Y-88244680D03*
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Ref,Val,Package,PosX,PosY,Rot,Side
1 Ref Val Package PosX PosY Rot Side

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{
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"Revision": "rev?"
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Designator,Val,Package,Mid X,Mid Y,Rotation,Layer
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U4,SN74LVC573A,TSSOP-20_4.4x6.5mm_P0.65mm,8.9154,15.03172,0,top
U5,SN74LVC573A,TSSOP-20_4.4x6.5mm_P0.65mm,27.92476,20.03298,180,top
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3 U4 SN74LVC573A TSSOP-20_4.4x6.5mm_P0.65mm 8.9154 15.03172 0 top
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README.md
View File

@ -7,6 +7,7 @@ My YouTube Channel with some videos of the stuff in action: www.youtube.com/chan
Boards:
MCLZ8 - Zilog Z80 emulator which runs on a Teensy 4.1 and can be used as a drop-in replacment
MCL86+ - Intel 8088 emulator which runs on a Teensy 4.1 and can be used as a drop-in replacment
MCL86jr - IBMPCjr Accelerator which boosts performance to IBM PC/AT speed
MCL65+ - MOS 6502 emulator which runs on a Teensy 4.1 and can be used as a 6502 drop-in replacment