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Uploaded_4_15_2025

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Ted Fried 2025-04-15 17:28:45 -07:00
parent 19d3ff9318
commit a73f25d540
8 changed files with 30740 additions and 9347 deletions
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0
MCL86jr/Code/MCL_FAST.COM → MCL86jr/Acceleration Programs/MCL_FAST.COM
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MCL86jr/Code/MCL_SLOW.COM → MCL86jr/Acceleration Programs/MCL_SLOW.COM
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21313
MCL86jr/FPGA Configuration Files/Config_Flash_W25Q128BV.mcs Normal file
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MCL86jr/FPGA Configuration Files/mcl86jr.bit Normal file
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MCL86jr/FPGA/Untitled.mcs
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MCL86jr/FPGA/src4synth/MCL86_Microcode_Xilinx_Version_4.coe Normal file
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242
MCL86jr/FPGA/src4synth/eu.v
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@ -1,7 +1,7 @@
//
//
// File Name : eu.v
// Used on : MCL86jr Board
// File Name : mcl86_eu_core.v
// Used on :
// Author : Ted Fried, MicroCore Labs
// Creation : 10/8/2015
// Code Type : Synthesizable
@ -19,8 +19,8 @@
// Revision 1.0 10/8/15
// Initial revision
//
// Revision 2.0 3/21/21
// Fixed overflow flag calculations
// Revision 2.0 11/6/22
// Changed overflow flag calculation into rtl instead of microcode
//
//
//------------------------------------------------------------------------
@ -102,10 +102,13 @@ reg eu_tr_latched;
reg biu_done_caught;
reg eu_biu_req_d1;
reg intr_enable_delayed;
reg eu_overflow_override;
reg eu_add_overflow8_fixed;
reg eu_add_overflow16_fixed;
wire eu_prefix_rep;
wire eu_prefix_repnz;
wire eu_tf_debounce;
wire eu_prefix_lock ;
wire eu_prefix_lock;
wire eu_biu_req;
wire eu_parity;
wire eu_flag_o;
@ -158,12 +161,12 @@ wire [15:0] eu_alu_out;
wire [15:0] eu_operand0;
wire [15:0] eu_operand1;
wire [31:0] eu_rom_data;
wire [15:0] add_total;
wire [15:0] sub_total;
wire [15:0] adc_total;
wire [15:0] sbb_total;
wire [15:0] adc_total;
wire [15:0] sbb_total;
reg eu_overflow_fix;
reg eu_add_overflow8_fixed;
reg eu_add_overflow16_fixed;
//------------------------------------------------------------------------
@ -336,11 +339,13 @@ assign intr_asserted = BIU_INTR & intr_enable_delayed;
assign new_instruction = (eu_rom_address[12:8]==5'h01) ? 1'b1 : 1'b0;
assign add_total = eu_register_r0 + eu_register_r1;
assign adc_total = eu_register_r0 + eu_register_r1 + eu_flag_c;
assign sub_total = eu_register_r0 - eu_register_r1;
assign sbb_total = eu_register_r0 - eu_register_r1 - eu_flag_c;
//------------------------------------------------------------------------------------------
//
// EU Microsequencer
@ -418,97 +423,166 @@ else
biu_done_d1 <= BIU_DONE;
biu_done_d2 <= biu_done_d1;
eu_biu_req_d1 <= eu_biu_req;
if (biu_done_d1==1'b0 && BIU_DONE==1'b1)
if (biu_done_d2==1'b0 && biu_done_d1==1'b1)
biu_done_caught <= 1'b1;
else if (eu_biu_req_d1==1'b1 && eu_biu_req==1'b0)
biu_done_caught <= 1'b0;
// ADC - Byte
//
if (eu_rom_address == 16'h0A03)
begin
eu_overflow_fix <= 1'b1;
if ( ( (eu_register_r0[7]==1'b0) && (eu_register_r1[7]==1'b0) && (adc_total[7]==1'b1) ) ||
( (eu_register_r0[7]==1'b1) && (eu_register_r1[7]==1'b1) && (adc_total[7]==1'b0) ) )
// ADD - Byte
//
if (eu_rom_address == 16'h09C9)
begin
eu_add_overflow8_fixed <= 1'b1;
end
else
eu_overflow_override <= 1'b1;
if ( ( (eu_register_r0[7]==1'b0) && (eu_register_r1[7]==1'b0) && (add_total[7]==1'b1) ) ||
( (eu_register_r0[7]==1'b1) && (eu_register_r1[7]==1'b1) && (add_total[7]==1'b0) ) )
begin
eu_add_overflow8_fixed <= 1'b1;
end
else
begin
eu_add_overflow8_fixed <= 1'b0;
end
end
// ADC - Byte
//
if (eu_rom_address == 16'h0A03)
begin
eu_add_overflow8_fixed <= 1'b0;
eu_overflow_override <= 1'b1;
if ( ( (eu_register_r0[7]==1'b0) && (eu_register_r1[7]==1'b0) && (adc_total[7]==1'b1) ) ||
( (eu_register_r0[7]==1'b1) && (eu_register_r1[7]==1'b1) && (adc_total[7]==1'b0) ) )
begin
eu_add_overflow8_fixed <= 1'b1;
end
else
begin
eu_add_overflow8_fixed <= 1'b0;
end
end
// SUB - Byte
//
if (eu_rom_address == 16'h0A46)
begin
eu_overflow_override <= 1'b1;
if ( ( (eu_register_r0[7]==1'b0) && (eu_register_r1[7]==1'b1) && (sub_total[7]==1'b1) ) ||
( (eu_register_r0[7]==1'b1) && (eu_register_r1[7]==1'b0) && (sub_total[7]==1'b0) ) )
begin
eu_add_overflow8_fixed <= 1'b1;
end
else
begin
eu_add_overflow8_fixed <= 1'b0;
end
end
// SBB - Byte
//
if (eu_rom_address == 16'h0AAE)
begin
eu_overflow_override <= 1'b1;
if ( ( (eu_register_r0[7]==1'b0) && (eu_register_r1[7]==1'b1) && (sbb_total[7]==1'b1) ) ||
( (eu_register_r0[7]==1'b1) && (eu_register_r1[7]==1'b0) && (sbb_total[7]==1'b0) ) )
begin
eu_add_overflow8_fixed <= 1'b1;
end
else
begin
eu_add_overflow8_fixed <= 1'b0;
end
end
// ADD - Word
//
if (eu_rom_address == 16'h09CC)
begin
eu_overflow_override <= 1'b1;
if ( ( (eu_register_r0[15]==1'b0) && (eu_register_r1[15]==1'b0) && (add_total[15]==1'b1) ) ||
( (eu_register_r0[15]==1'b1) && (eu_register_r1[15]==1'b1) && (add_total[15]==1'b0) ) )
begin
eu_add_overflow16_fixed <= 1'b1;
end
else
begin
eu_add_overflow16_fixed <= 1'b0;
end
end
// ADC - Word
//
if (eu_rom_address == 16'h0A12)
begin
eu_overflow_override <= 1'b1;
if ( ( (eu_register_r0[15]==1'b0) && (eu_register_r1[15]==1'b0) && (adc_total[15]==1'b1) ) ||
( (eu_register_r0[15]==1'b1) && (eu_register_r1[15]==1'b1) && (adc_total[15]==1'b0) ) )
begin
eu_add_overflow16_fixed <= 1'b1;
end
else
begin
eu_add_overflow16_fixed <= 1'b0;
end
end
// SUB - Word
//
if (eu_rom_address == 16'h0A52)
begin
eu_overflow_override <= 1'b1;
if ( ( (eu_register_r0[15]==1'b0) && (eu_register_r1[15]==1'b1) && (sub_total[15]==1'b1) ) ||
( (eu_register_r0[15]==1'b1) && (eu_register_r1[15]==1'b0) && (sub_total[15]==1'b0) ) )
begin
eu_add_overflow16_fixed <= 1'b1;
end
else
begin
eu_add_overflow16_fixed <= 1'b0;
end
end
// SBB - Word
//
if (eu_rom_address == 16'h0ABA)
begin
eu_overflow_override <= 1'b1;
if ( ( (eu_register_r0[15]==1'b0) && (eu_register_r1[15]==1'b1) && (sbb_total[15]==1'b1) ) ||
( (eu_register_r0[15]==1'b1) && (eu_register_r1[15]==1'b0) && (sbb_total[15]==1'b0) ) )
begin
eu_add_overflow16_fixed <= 1'b1;
end
else
begin
eu_add_overflow16_fixed <= 1'b0;
end
end
end
// SBB - Byte
//
if (eu_rom_address == 16'h0AAE)
begin
eu_overflow_fix <= 1'b1;
if ( ( (eu_register_r0[7]==1'b0) && (eu_register_r1[7]==1'b1) && (sbb_total[7]==1'b1) ) ||
( (eu_register_r0[7]==1'b1) && (eu_register_r1[7]==1'b0) && (sbb_total[7]==1'b0) ) )
begin
eu_add_overflow8_fixed <= 1'b1;
end
else
begin
eu_add_overflow8_fixed <= 1'b0;
end
end
// ADC - Word
//
if (eu_rom_address == 16'h0A12)
begin
eu_overflow_fix <= 1'b1;
if ( ( (eu_register_r0[15]==1'b0) && (eu_register_r1[15]==1'b0) && (adc_total[15]==1'b1) ) ||
( (eu_register_r0[15]==1'b1) && (eu_register_r1[15]==1'b1) && (adc_total[15]==1'b0) ) )
begin
eu_add_overflow16_fixed <= 1'b1;
end
else
begin
eu_add_overflow16_fixed <= 1'b0;
end
end
// Debounce the overflow flag override when microcode returns to the main loop
//
if (eu_rom_address == 16'h0011) eu_overflow_override <= 1'b0;
// SBB - Word
//
if (eu_rom_address == 16'h0ABA)
begin
eu_overflow_fix <= 1'b1;
if ( ( (eu_register_r0[15]==1'b0) && (eu_register_r1[15]==1'b1) && (sbb_total[15]==1'b1) ) ||
( (eu_register_r0[15]==1'b1) && (eu_register_r1[15]==1'b0) && (sbb_total[15]==1'b0) ) )
begin
eu_add_overflow16_fixed <= 1'b1;
end
else
begin
eu_add_overflow16_fixed <= 1'b0;
end
end
if (eu_rom_address == 16'h0011) eu_overflow_fix <= 1'b0;
// Generate and store flags for addition
if (eu_stall_pipeline==1'b0 && eu_opcode_type==3'h2)
begin
eu_add_carry <= carry[16];
eu_add_carry8 <= carry[8];
eu_add_aux_carry <= carry[4];
eu_add_overflow16 <= (eu_overflow_fix==1'b1) ? eu_add_overflow16_fixed : (carry[16] ^ carry[15]);
eu_add_overflow8 <= (eu_overflow_fix==1'b1) ? eu_add_overflow8_fixed : (carry[8] ^ carry[7]);
eu_add_overflow16 <= (eu_overflow_override==1'b1) ? eu_add_overflow16_fixed : (carry[16] ^ carry[15]);
eu_add_overflow8 <= (eu_overflow_override==1'b1) ? eu_add_overflow8_fixed : (carry[8] ^ carry[7] );
end
// Register writeback
if (eu_stall_pipeline==1'b0 && eu_opcode_type!=3'h0 && eu_opcode_type!=3'h1)
begin

6
MCL86jr/README.md
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@ -2,10 +2,14 @@
This board is a drop-in replacement for the 8088 CPU inside of the PCjr. It utilizes a Xilinx Spartan-6 FPGA and 512KB of SRAM.
The CPU core is the MCL86 and can be run in cycle accurare mode as a mode that boosts PCjr performance by almost 6X which is as fast as an 8Mhz IBM PC AT!
The CPU core is the MCL86 and can be run in cycle accurare mode which boosts PCjr performance by almost 6X which is close to the speed of an 8Mhz IBM PC AT!
The board schematic and layout were done using KiCad and all of the development files are in the PCBA directory. The board was manufacured and assembled by PCBWay.
Updated on 4/15/2025
- Microcode and EU files updated to integrate bug fixes found in the MCL86 on the MiSTer PCXT project
- FPGA Configuration Files folder added which contains the FPGA direct programming .bit file and also the configuration Flash .mc file
For questions email me at www.MicroCoreLabs.com