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Uploaded_10_4_2025

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Ted Fried 2025-10-04 23:38:43 -07:00
parent 0255927345
commit fc24eab83d
3 changed files with 10771 additions and 10757 deletions
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13
MCL86/Core/eu.v
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@ -108,6 +108,7 @@ reg intr_enable_delayed;
reg eu_overflow_override; reg eu_overflow_override;
reg eu_add_overflow8_fixed; reg eu_add_overflow8_fixed;
reg eu_add_overflow16_fixed; reg eu_add_overflow16_fixed;
reg idiv_opcode;
wire eu_prefix_rep; wire eu_prefix_rep;
wire eu_prefix_repnz; wire eu_prefix_repnz;
wire eu_tf_debounce; wire eu_tf_debounce;
@ -180,7 +181,7 @@ wire [15:0] sbb_total;
// //
//------------------------------------------------------------------------ //------------------------------------------------------------------------
EU4Kx32 EU_4Kx32_i ( EU4Kx32 EU4Kx32_i (
.clka (CORE_CLK_INT), .clka (CORE_CLK_INT),
.addra (eu_rom_address[11:0]), .addra (eu_rom_address[11:0]),
@ -254,8 +255,8 @@ assign eu_operand1 = (eu_opcode_op1_sel==4'h0) ? BIU_REGISTER_ES :
// JUMP condition codes // JUMP condition codes
assign eu_jump_boolean = ( (eu_rom_address == 'h0E76) && (eu_register_ax[15:7]!='h0)) ? 1'b1 : assign eu_jump_boolean = ( (idiv_opcode=='h1) && (eu_rom_address == 'h0E76) && (eu_register_ax[15:7]!='h0)) ? 1'b1 :
( (eu_rom_address == 'h0F02) && ( (eu_register_dx!='h0) || (eu_register_ax[15]!='h0) )) ? 1'b1 : ( (idiv_opcode=='h1) && (eu_rom_address == 'h0F02) && ( (eu_register_dx!='h0) || (eu_register_ax[15]!='h0) )) ? 1'b1 :
(eu_opcode_jump_cond==4'h0) ? 1'b1 : // unconditional jump (eu_opcode_jump_cond==4'h0) ? 1'b1 : // unconditional jump
(eu_opcode_jump_cond==4'h1 && eu_alu_last_result!=16'h0) ? 1'b1 : (eu_opcode_jump_cond==4'h1 && eu_alu_last_result!=16'h0) ? 1'b1 :
(eu_opcode_jump_cond==4'h2 && eu_alu_last_result==16'h0) ? 1'b1 : (eu_opcode_jump_cond==4'h2 && eu_alu_last_result==16'h0) ? 1'b1 :
@ -396,6 +397,7 @@ begin : EU_MICROSEQUENCER
eu_rom_address <= 13'h0020; eu_rom_address <= 13'h0020;
eu_calling_address <= 'h0; eu_calling_address <= 'h0;
intr_enable_delayed <= 1'b0; intr_enable_delayed <= 1'b0;
idiv_opcode <= 'h0;
end end
else else
@ -582,8 +584,13 @@ else
eu_overflow_override <= 1'b0; eu_overflow_override <= 1'b0;
initial_ax <= eu_register_ax; initial_ax <= eu_register_ax;
initial_dx <= eu_register_dx; initial_dx <= eu_register_dx;
idiv_opcode <= 'h0;
end end
if ( (eu_rom_address=='h0E54) || (eu_rom_address=='h0ED0) )
begin
idiv_opcode <= 'h1;
end
// Generate and store flags for addition // Generate and store flags for addition

21500
MCL86jr/FPGA Configuration Files/ConfigFlash_W25Q128BV.mcs → MCL86jr/FPGA Configuration Files/Config_Flash_W25Q128BV.mcs
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11
MCL86jr/FPGA/src4synth/eu.v
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@ -108,6 +108,7 @@ reg intr_enable_delayed;
reg eu_overflow_override; reg eu_overflow_override;
reg eu_add_overflow8_fixed; reg eu_add_overflow8_fixed;
reg eu_add_overflow16_fixed; reg eu_add_overflow16_fixed;
reg idiv_opcode;
wire eu_prefix_rep; wire eu_prefix_rep;
wire eu_prefix_repnz; wire eu_prefix_repnz;
wire eu_tf_debounce; wire eu_tf_debounce;
@ -254,8 +255,8 @@ assign eu_operand1 = (eu_opcode_op1_sel==4'h0) ? BIU_REGISTER_ES :
// JUMP condition codes // JUMP condition codes
assign eu_jump_boolean = ( (eu_rom_address == 'h0E76) && (eu_register_ax[15:7]!='h0)) ? 1'b1 : assign eu_jump_boolean = ( (idiv_opcode=='h1) && (eu_rom_address == 'h0E76) && (eu_register_ax[15:7]!='h0)) ? 1'b1 :
( (eu_rom_address == 'h0F02) && ( (eu_register_dx!='h0) || (eu_register_ax[15]!='h0) )) ? 1'b1 : ( (idiv_opcode=='h1) && (eu_rom_address == 'h0F02) && ( (eu_register_dx!='h0) || (eu_register_ax[15]!='h0) )) ? 1'b1 :
(eu_opcode_jump_cond==4'h0) ? 1'b1 : // unconditional jump (eu_opcode_jump_cond==4'h0) ? 1'b1 : // unconditional jump
(eu_opcode_jump_cond==4'h1 && eu_alu_last_result!=16'h0) ? 1'b1 : (eu_opcode_jump_cond==4'h1 && eu_alu_last_result!=16'h0) ? 1'b1 :
(eu_opcode_jump_cond==4'h2 && eu_alu_last_result==16'h0) ? 1'b1 : (eu_opcode_jump_cond==4'h2 && eu_alu_last_result==16'h0) ? 1'b1 :
@ -396,6 +397,7 @@ begin : EU_MICROSEQUENCER
eu_rom_address <= 13'h0020; eu_rom_address <= 13'h0020;
eu_calling_address <= 'h0; eu_calling_address <= 'h0;
intr_enable_delayed <= 1'b0; intr_enable_delayed <= 1'b0;
idiv_opcode <= 'h0;
end end
else else
@ -582,8 +584,13 @@ else
eu_overflow_override <= 1'b0; eu_overflow_override <= 1'b0;
initial_ax <= eu_register_ax; initial_ax <= eu_register_ax;
initial_dx <= eu_register_dx; initial_dx <= eu_register_dx;
idiv_opcode <= 'h0;
end end
if ( (eu_rom_address=='h0E54) || (eu_rom_address=='h0ED0) )
begin
idiv_opcode <= 'h1;
end
// Generate and store flags for addition // Generate and store flags for addition