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https://github.com/PDP-10/its.git
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203 lines
3.5 KiB
Plaintext
Executable File
203 lines
3.5 KiB
Plaintext
Executable File
;;; -*-midas-*-
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.sbttl Macros for CPU compatibility for PDP11 processors
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;;; ;;; General info:
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;;; ;;; These macros make all PDP-11s look alike in software.
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.if ndf pdp11
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.print "
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The value of PDP11 must be defined before the CPU macro package
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is inserted.
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"
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.error (see previous print)
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.endc
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.if z <pdp11-02> ;define things for the lsi11/2
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qbus==1 ;yas a qbus
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hasxor==1 ;xor includes SXT, XOR, MMARK, SOB, RTT
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hasspl==0 ;only 11/45 and 11/70 have SPL
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haseis==0 ;doesn't have the the Extended Instructions
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.endc
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.if z <pdp11-05>*<pdp11-10>
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qbus==0 ;no qbus on these old beasts
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hasxor==0 ;nor xor
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hasspl==0 ;only 11/45 and 11/70 have SPL
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haseis==0 ;nor EIS
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.endc
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.if z <pdp11-34>
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qbus==0 ;no qbus on this slighty old beast
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hasxor==1 ;winning XOR and friends
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hasspl==0 ;only 11/44, 11/45, and 11/70 have SPL
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haseis==1 ;has winning EIS
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.endc
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.if z <pdp11-23>
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qbus==1 ;super losing QBUS
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hasxor==1 ;winning XOR and friends
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hasspl==0 ;only 11/45 and 11/70 have SPL
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haseis==1 ;and EIS instructions
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.endc
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.sbttl Standard register definitions and priorities
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r0=%0
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r1=%1
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r2=%2
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r3=%3
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r4=%4
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r5=%5
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sp=%6
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pc=%7
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ps==177776 ;the processor status word
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pr0==000
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pr1==040
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pr2==100
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pr3==140
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pr4==200
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pr5==240
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pr6==300
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pr7==340
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psw.t==bit.04
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psw.n==bit.03
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psw.z==bit.02
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psw.v==bit.01
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psw.c==bit.00
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;;; e.g., movea #foo,r4,r5
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.macro movea adder,base,dest,dstmod
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mov base,dest
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add adder,dest'dstmod
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.endm
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.sbttl Instruction macros
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.if z qbus
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;;; MTPS and MFPS exist only on qbus versions. Others should use
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;;; either SPL or direct from mthe psw
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.macro mtps src
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.nlist
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movb src,@#ps
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.list
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.endm
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.macro mfps dst
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.nlist
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movb @#ps,dst
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.list
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.endm
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.endc
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.if z hasspl
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;;; Only the 11/45 and 11/70 have the SPL instruction
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.macro spl n
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.nlist
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mtps #n*40
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.list
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.endm
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.endc
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.if z hasxor ;XOR and friends
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; SOB macro expands into code which performs identically to
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; the SOB instruction found on more powerfull 11 processors
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.macro sob r,addr
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.nlist
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dec r
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bne addr
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.list
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.endm
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; RTT macro expands into a RTI. This is so RTTs can be used in
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; places where they would be called for on 11/40s, 11/45s etc.
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.macro rtt
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rti
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.endm
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; XOR macro simulates XOR instruction on 11/45.
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; Caution: this macro is not intended to work with
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; (Rn)+, -(Rn) or (SP) destinations.
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.macro xor r,d
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.nlist
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mov r,-(sp)
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bic d,(sp)
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bic r,d
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bis (sp)+,d
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.list
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.endm
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; SXT macro performs sign extend as on PDP11/45. (requires if/else macro)
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.macro sxt d
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.nlist
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if mi,<mov #-1,d>
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else <clr d>
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.list
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.endm
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.endc ; hasxor
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%muldv==0 ;not needed, or in hardware
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.if eq haseis
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; ASH macro generates a series of ASR or ASL instructions to
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; simulate the 11/45 ASH instruction.
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.macro ash src,r
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.ntype %.m,r
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.iif ne %.m&70, .error ASH dst must be register
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.ntype %.m,src
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.iif ne %.m-27, .error ASH macro must have constant shift
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%.m===0'src
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.if ge %.m
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.rept %.m
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asl r
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.endr
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.iff
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.rept -%.m
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asr r
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.endr
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.endc
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.endm
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; MUL macro generates call to either MUL1 or MUL2 depending upon
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; whether register destination is even or odd. Simulates 11/45 MUL.
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.macro mul src,r
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.ntype %.m,r
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.iif ne %.m&70, .error MUL dst must be register
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mov src,-(sp)
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mov r,-(sp)
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.iif ne %.m&1, jsr r5,mul1
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.ielse jsr r5,mul2
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mov (sp)+,r
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.iif eq %.m&1, mov (sp)+,r+1
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%muldv==-1
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.endm
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; DIV macro generates call to DIV2 to simulate 11/45 DIV instruction.
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.macro div src,r
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.ntype %.m,r
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.iif ne %.m&70, .error DIV dst must be register
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mov r,-(sp)
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mov r+1,-(sp)
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mov src,-(sp)
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jsr r5,div2
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mov (sp)+,r+1
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mov (sp)+,r
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%muldv==-1
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.endm
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.endc ; eq haseis
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