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github.com:master github.com:modded github.com:v1.3_modded github.com:v1.3
github.com:V1.4 github.com:V1.4-Modded github.com:archive/Feature github.com:archive/Improved github.com:V1.2 github.com:V1.1 github.com:V.1.0

8 Commits
V1.1 ... archive/Fe

Author SHA1 Message Date
Redherring32
cbe4eec15c + Added "1.2" features back into Motherboard.kicad_pcb in feature branch 2022-03-22 22:53:50 -07:00
Redherring32
d530f0018b + Fixed C20 value error 
+ Added sym-lib-table and fp-lib-table to fix symbol/footprint mapping issues
 2021-11-05 16:38:52 -07:00
Redherring32
f2f2795cae + Added Schematics folder, and schematics for NES-CPU-1/02 and NES-CPU-11 
+ Fixed pin numbering error in edge connector footprint
+ Fixed spacing errors in EXP connector footprint
+ Fixed value error with C4
+ Updated readme to reflect new repository structure
 2021-11-05 14:40:52 -07:00
Redherring32
edfe99b377 + Removed expansion audio routing 
+ Removed RST test point
+ Removed stereo audio solder pads
+ Removed P6 alt footprint
+ Removed P6 alt from schematic
+ Removed R15 from schematic
+ Re-added missing "Unused" labels on unpopulated parts
+ Fixed redundant capacitor footprint width variations
 2021-07-23 21:46:57 -07:00
Redherring32
3b9c6e0f49 Updated readme photo to show V1.2 PCB, and added note on video output "improvements" 2021-06-10 11:22:37 -07:00
Redherring32
c3f793accc Fix readme typo 2021-02-25 01:04:50 -06:00
Redherring32
627f0fbb3d + Fixed R13 value error 2021-02-15 12:35:53 -06:00
Redherring32
8fde526eec + Added JST footprint for future open source power/reset button PCB 
+ Fixed outdated RF Modulator footprint
+ Edited schematic to further improve readability
+ Added silkscreen denoting PAL and NTSC X1 frequencies
+ Added mask layer to edge connector to remove soldermask from the mating surfaces
 2021-01-08 17:01:13 -06:00
14 changed files with 20222 additions and 12683 deletions
Expand all files Collapse all files

17374
Board Files/Motherboard.kicad_pcb
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File diff suppressed because it is too large Load Diff

22
Board Files/Motherboard.pro
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@@ -1,4 +1,4 @@
update=12/2/2019 9:31:35 PM update=11/5/2021 4:25:38 PM
version=1 version=1
last_client=kicad last_client=kicad
[general] [general]
@@ -12,16 +12,6 @@ NetIExt=net
version=1 version=1
LibDir= LibDir=
[eeschema/libraries] [eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=F:/NES-RE/Board Files
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew] [pcbnew]
version=1 version=1
PageLayoutDescrFile= PageLayoutDescrFile=
@@ -250,3 +240,13 @@ uViaDrill=0.1
dPairWidth=0.2 dPairWidth=0.2
dPairGap=0.25 dPairGap=0.25
dPairViaGap=0.25 dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=C:/Users/Redherring32/Documents/OpenTendo.git/trunk/Schematics/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

149
Board Files/Motherboard.sch
View File

@@ -1,5 +1,6 @@
EESchema Schematic File Version 4 EESchema Schematic File Version 4
EELAYER 30 0 LIBS:Motherboard-cache
EELAYER 29 0
EELAYER END EELAYER END
$Descr A3 16535 11693 $Descr A3 16535 11693
encoding utf-8 encoding utf-8
@@ -14,7 +15,7 @@ Comment3 "Reverse Engineered by Krzysiobal"
Comment4 "Nintendo Entertainment System (NES) Motherboard" Comment4 "Nintendo Entertainment System (NES) Motherboard"
$EndDescr $EndDescr
$Comp $Comp
L NES-CPU-11:RP2C02_PPU U5 L Motherboard:RP2C02_PPU U5
U 1 1 5D7FE1C0 U 1 1 5D7FE1C0
P 9900 6700 P 9900 6700
F 0 "U5" H 9550 7800 50 0000 C CNN F 0 "U5" H 9550 7800 50 0000 C CNN
@@ -277,7 +278,7 @@ Wire Wire Line
Wire Wire Line Wire Wire Line
11000 7450 11450 7450 11000 7450 11450 7450
$Comp $Comp
L NES-CPU-11:2KB_SRAM U4 L Motherboard:2KB_SRAM U4
U 1 1 5D8358FE U 1 1 5D8358FE
P 11850 7100 P 11850 7100
F 0 "U4" H 11600 7800 50 0000 C CNN F 0 "U4" H 11600 7800 50 0000 C CNN
@@ -324,7 +325,7 @@ Wire Wire Line
Wire Wire Line Wire Wire Line
12250 6850 12700 6850 12250 6850 12700 6850
$Comp $Comp
L NES-CPU-11:74HC373 U2 L Motherboard:74HC373 U2
U 1 1 5D8739AE U 1 1 5D8739AE
P 11850 5700 P 11850 5700
F 0 "U2" H 11600 6300 50 0000 C CNN F 0 "U2" H 11600 6300 50 0000 C CNN
@@ -464,7 +465,7 @@ F 3 "http://www.ti.com/lit/gpn/sn74LS04" H 9350 8350 50 0001 C CNN
1 0 0 -1 1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L NES-CPU-11:RP2A03_CPU U6 L Motherboard:RP2A03_CPU U6
U 1 1 5D911B13 U 1 1 5D911B13
P 9550 2050 P 9550 2050
F 0 "U6" H 9200 3150 50 0000 C CNN F 0 "U6" H 9200 3150 50 0000 C CNN
@@ -722,7 +723,7 @@ Wire Wire Line
Wire Wire Line Wire Wire Line
12550 2750 12150 2750 12550 2750 12150 2750
$Comp $Comp
L NES-CPU-11:2KB_SRAM U1 L Motherboard:2KB_SRAM U1
U 1 1 5DB49A97 U 1 1 5DB49A97
P 10600 3900 P 10600 3900
F 0 "U1" H 10350 4600 50 0000 C CNN F 0 "U1" H 10350 4600 50 0000 C CNN
@@ -831,7 +832,7 @@ Wire Wire Line
Text Notes 9750 800 0 50 ~ 10 Text Notes 9750 800 0 50 ~ 10
CENTRAL PROCESSING UNIT & WORK RAM CENTRAL PROCESSING UNIT & WORK RAM
$Comp $Comp
L NES-CPU-11:Controller_Port Controller_Port_1 L Motherboard:Controller_Port Controller_Port_1
U 1 1 5DCEA036 U 1 1 5DCEA036
P 1350 1650 P 1350 1650
F 0 "Controller_Port_1" H 1350 2000 50 0000 C CNN F 0 "Controller_Port_1" H 1350 2000 50 0000 C CNN
@@ -1007,7 +1008,7 @@ Connection ~ 2800 1950
Wire Wire Line Wire Wire Line
2800 1950 2800 2200 2800 1950 2800 2200
$Comp $Comp
L NES-CPU-11:EXP-CON P2 L Motherboard:EXP-CON P2
U 1 1 5D833A72 U 1 1 5D833A72
P 14250 6750 P 14250 6750
F 0 "P2" H 14250 8100 59 0000 C CNN F 0 "P2" H 14250 8100 59 0000 C CNN
@@ -1018,7 +1019,7 @@ F 3 "" H 14250 6750 50 0001 C CNN
1 0 0 -1 1 0 0 -1
$EndComp $EndComp
$Comp $Comp
L NES-CPU-11:72-Pin_Connector P1 L Motherboard:72-Pin_Connector P1
U 1 1 5D838060 U 1 1 5D838060
P 14250 2850 P 14250 2850
F 0 "P1" H 14250 4915 50 0000 C CNN F 0 "P1" H 14250 4915 50 0000 C CNN
@@ -1513,7 +1514,7 @@ F 3 "~" H 3450 1450 50 0001 C CNN
-1 0 0 1 -1 0 0 1
$EndComp $EndComp
$Comp $Comp
L NES-CPU-11:Diode_Array_7pin_(Cathode-Common) DA1 L Motherboard:Diode_Array_7pin_(Cathode-Common) DA1
U 1 1 5E877EA3 U 1 1 5E877EA3
P 4150 750 P 4150 750
F 0 "DA1" H 3950 750 50 0000 R CNN F 0 "DA1" H 3950 750 50 0000 R CNN
@@ -1528,7 +1529,7 @@ VCC
Wire Wire Line Wire Wire Line
4250 650 4250 900 4250 650 4250 900
$Comp $Comp
L NES-CPU-11:Diode_Array_7pin_(Anode-Common) DA2 L Motherboard:Diode_Array_7pin_(Anode-Common) DA2
U 1 1 5E8CEEDD U 1 1 5E8CEEDD
P 4150 2150 P 4150 2150
F 0 "DA2" H 3800 2050 50 0000 L CNN F 0 "DA2" H 3800 2050 50 0000 L CNN
@@ -1709,7 +1710,7 @@ Text Label 6300 1650 2 50 ~ 0
Text Label 6300 1750 2 50 ~ 0 Text Label 6300 1750 2 50 ~ 0
GND GND
$Comp $Comp
L NES-CPU-11:Controller_Port Controller_Port_2 L Motherboard:Controller_Port Controller_Port_2
U 1 1 5F41BB80 U 1 1 5F41BB80
P 1350 3350 P 1350 3350
F 0 "Controller_Port_2" H 1350 3700 50 0000 C CNN F 0 "Controller_Port_2" H 1350 3700 50 0000 C CNN
@@ -1885,7 +1886,7 @@ F 3 "~" H 3450 3150 50 0001 C CNN
-1 0 0 1 -1 0 0 1
$EndComp $EndComp
$Comp $Comp
L NES-CPU-11:Diode_Array_7pin_(Cathode-Common) DA3 L Motherboard:Diode_Array_7pin_(Cathode-Common) DA3
U 1 1 5F41BBE4 U 1 1 5F41BBE4
P 4150 2450 P 4150 2450
F 0 "DA3" H 3950 2450 50 0000 R CNN F 0 "DA3" H 3950 2450 50 0000 R CNN
@@ -1900,7 +1901,7 @@ VCC
Wire Wire Line Wire Wire Line
4250 2350 4250 2600 4250 2350 4250 2600
$Comp $Comp
L NES-CPU-11:Diode_Array_7pin_(Anode-Common) DA4 L Motherboard:Diode_Array_7pin_(Anode-Common) DA4
U 1 1 5F41BBEC U 1 1 5F41BBEC
P 4150 3850 P 4150 3850
F 0 "DA4" H 3800 3750 50 0000 L CNN F 0 "DA4" H 3800 3750 50 0000 L CNN
@@ -2027,7 +2028,7 @@ F 3 "~" H 2550 3250 50 0001 C CNN
-1 0 0 1 -1 0 0 1
$EndComp $EndComp
$Comp $Comp
L NES-CPU-11:74HC368 U7 L Motherboard:74HC368 U7
U 1 1 5FA4F885 U 1 1 5FA4F885
P 7500 1350 P 7500 1350
F 0 "U7" H 7250 1850 50 0000 C CNN F 0 "U7" H 7250 1850 50 0000 C CNN
@@ -2099,12 +2100,12 @@ Wire Wire Line
Wire Wire Line Wire Wire Line
7900 1700 8350 1700 7900 1700 8350 1700
$Comp $Comp
L NES-CPU-11:74HC368 U8 L Motherboard:74HC368 U8
U 1 1 5FF817ED U 1 1 5FF817ED
P 7450 2500 P 7450 2500
F 0 "U8" H 7200 3000 50 0000 C CNN F 0 "U8" H 7200 3000 50 0000 C CNN
F 1 "40H368 (CII)" H 7300 2000 50 0000 C CNN F 1 "40H368 (CII)" H 7300 2000 50 0000 C CNN
F 2 "Package_DIP:DIP-16_W7.62mm" H 7400 3100 50 0000 C CNN F 2 "Package_DIP:DIP-16_W7.62mm" H 7400 3100 50 0001 C CNN
F 3 "https://www.cl.cam.ac.uk/teaching//2003/Hardware/datasheets/ht6116.pdf" H 7200 3000 50 0001 C CNN F 3 "https://www.cl.cam.ac.uk/teaching//2003/Hardware/datasheets/ht6116.pdf" H 7200 3000 50 0001 C CNN
1 7450 2500 1 7450 2500
1 0 0 -1 1 0 0 -1
@@ -2241,17 +2242,6 @@ Text Label 8800 4100 1 50 ~ 0
Wire Wire Line Wire Wire Line
8800 4100 8800 3800 8800 4100 8800 3800
$Comp $Comp
L Device:R R15
U 1 1 60B446CF
P 13150 6100
F 0 "R15" V 13050 5900 50 0000 L CNN
F 1 "100K" V 13050 6150 50 0000 L CNN
F 2 "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" V 13080 6100 50 0001 C CNN
F 3 "~" H 13150 6100 50 0001 C CNN
1 13150 6100
1 0 0 -1
$EndComp
$Comp
L Device:C_Variable TC1 L Device:C_Variable TC1
U 1 1 5D8E3F5E U 1 1 5D8E3F5E
P 2600 7550 P 2600 7550
@@ -2402,7 +2392,7 @@ U 1 1 5E841A82
P 1800 8550 P 1800 8550
F 0 "C44" V 1650 8550 50 0000 C CNN F 0 "C44" V 1650 8550 50 0000 C CNN
F 1 "220pF" V 1550 8550 50 0000 C CNN F 1 "220pF" V 1550 8550 50 0000 C CNN
F 2 "Capacitor_THT:C_Disc_D3.0mm_W2.0mm_P2.50mm" H 1800 8550 50 0001 C CNN F 2 "Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm" H 1800 8550 50 0001 C CNN
F 3 "~" H 1800 8550 50 0001 C CNN F 3 "~" H 1800 8550 50 0001 C CNN
1 1800 8550 1 1800 8550
0 -1 -1 0 0 -1 -1 0
@@ -2412,7 +2402,7 @@ L Device:R R13
U 1 1 5EC660D3 U 1 1 5EC660D3
P 2200 8800 P 2200 8800
F 0 "R13" V 2100 8650 50 0000 L CNN F 0 "R13" V 2100 8650 50 0000 L CNN
F 1 "1.2K" V 2100 8850 50 0000 L CNN F 1 "150K" V 2100 8850 50 0000 L CNN
F 2 "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" V 2130 8800 50 0001 C CNN F 2 "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" V 2130 8800 50 0001 C CNN
F 3 "~" H 2200 8800 50 0001 C CNN F 3 "~" H 2200 8800 50 0001 C CNN
1 2200 8800 1 2200 8800
@@ -2593,8 +2583,8 @@ $Comp
L Device:C_Small C20 L Device:C_Small C20
U 1 1 6060ABA1 U 1 1 6060ABA1
P 3100 4950 P 3100 4950
F 0 "C20" V 3200 5050 50 0000 C CNN F 0 "C20" V 3200 5100 50 0000 C CNN
F 1 "51pF" V 3200 4850 50 0000 C CNN F 1 "220pF" V 3200 4750 50 0000 C CNN
F 2 "Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm" H 3100 4950 50 0001 C CNN F 2 "Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm" H 3100 4950 50 0001 C CNN
F 3 "~" H 3100 4950 50 0001 C CNN F 3 "~" H 3100 4950 50 0001 C CNN
1 3100 4950 1 3100 4950
@@ -2680,17 +2670,6 @@ Wire Wire Line
Connection ~ 3500 4950 Connection ~ 3500 4950
Text Notes 2300 4650 2 50 ~ 10 Text Notes 2300 4650 2 50 ~ 10
MONO AUDIO MIXER & AMPLIFER MONO AUDIO MIXER & AMPLIFER
$Comp
L NES-CPU-11:Ferrite_Core FC1
U 1 1 5D8FC474
P 3950 5100
F 0 "FC1" H 3737 5125 50 0000 C CNN
F 1 "39u" H 3737 5034 50 0000 C CNN
F 2 "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" H 3950 5100 50 0001 C CNN
F 3 "" H 3950 5100 50 0001 C CNN
1 3950 5100
1 0 0 -1
$EndComp
Text Label 4200 5300 2 50 ~ 0 Text Label 4200 5300 2 50 ~ 0
AUDIO AUDIO
Text Label 4450 4750 2 50 ~ 0 Text Label 4450 4750 2 50 ~ 0
@@ -2703,8 +2682,8 @@ L Device:C_Small C4
U 1 1 5DD404CF U 1 1 5DD404CF
P 3900 5400 P 3900 5400
F 0 "C4" H 4100 5350 50 0000 C CNN F 0 "C4" H 4100 5350 50 0000 C CNN
F 1 "220pF" H 4100 5450 50 0000 C CNN F 1 "10nF" H 4100 5450 50 0000 C CNN
F 2 "Capacitor_THT:C_Disc_D5.0mm_W2.5mm_P5.00mm" H 3900 5400 50 0001 C CNN F 2 "Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm" H 3900 5400 50 0001 C CNN
F 3 "~" H 3900 5400 50 0001 C CNN F 3 "~" H 3900 5400 50 0001 C CNN
1 3900 5400 1 3900 5400
-1 0 0 1 -1 0 0 1
@@ -3016,8 +2995,8 @@ $Comp
L Connector:Conn_01x05_Male P6 L Connector:Conn_01x05_Male P6
U 1 1 60EC5AFE U 1 1 60EC5AFE
P 8200 7600 P 8200 7600
F 0 "P6" H 8150 7500 50 0000 R CNN F 0 "P6" H 8150 7400 50 0000 R CNN
F 1 "PWR/RST IN" H 8150 7600 50 0000 R CNN F 1 "PWR/RST IN" H 8150 7700 50 0000 R CNN
F 2 "NESRE:PowerReset-switch-In" H 8200 7600 50 0001 C CNN F 2 "NESRE:PowerReset-switch-In" H 8200 7600 50 0001 C CNN
F 3 "~" H 8200 7600 50 0001 C CNN F 3 "~" H 8200 7600 50 0001 C CNN
1 8200 7600 1 8200 7600
@@ -3028,14 +3007,14 @@ Wire Wire Line
Wire Wire Line Wire Wire Line
8000 7700 7550 7700 8000 7700 7550 7700
$Comp $Comp
L Connector:Conn_01x09_Male P3 L Connector:Conn_01x06_Male P3
U 1 1 619A2E89 U 1 1 619A2E89
P 8200 6800 P 8200 7000
F 0 "P3" H 8172 6732 50 0000 R CNN F 0 "P3" H 8172 6932 50 0000 R CNN
F 1 "MOD RF" H 8172 6823 50 0000 R CNN F 1 "MOD RF" H 8172 7023 50 0000 R CNN
F 2 "NESRE:Mod_RF" H 8200 6800 50 0001 C CNN F 2 "NESRE:Mod_RF" H 8200 7000 50 0001 C CNN
F 3 "~" H 8200 6800 50 0001 C CNN F 3 "~" H 8200 7000 50 0001 C CNN
1 8200 6800 1 8200 7000
-1 0 0 1 -1 0 0 1
$EndComp $EndComp
Text Label 7550 7200 0 50 ~ 0 Text Label 7550 7200 0 50 ~ 0
@@ -3100,7 +3079,7 @@ U 1 1 5FDFF045
P 5150 7100 P 5150 7100
F 0 "C7" H 5000 7050 50 0000 C CNN F 0 "C7" H 5000 7050 50 0000 C CNN
F 1 "220pF" H 4950 7150 50 0000 C CNN F 1 "220pF" H 4950 7150 50 0000 C CNN
F 2 "Capacitor_THT:C_Disc_D3.4mm_W2.1mm_P2.50mm" H 5150 7100 50 0001 C CNN F 2 "Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm" H 5150 7100 50 0001 C CNN
F 3 "~" H 5150 7100 50 0001 C CNN F 3 "~" H 5150 7100 50 0001 C CNN
1 5150 7100 1 5150 7100
-1 0 0 1 -1 0 0 1
@@ -3111,7 +3090,7 @@ U 1 1 5FC5EB8E
P 4850 7100 P 4850 7100
F 0 "C6" H 5050 7050 50 0000 C CNN F 0 "C6" H 5050 7050 50 0000 C CNN
F 1 "220pF" H 5050 7150 50 0000 C CNN F 1 "220pF" H 5050 7150 50 0000 C CNN
F 2 "Capacitor_THT:C_Disc_D3.4mm_W2.1mm_P2.50mm" H 4850 7100 50 0001 C CNN F 2 "Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm" H 4850 7100 50 0001 C CNN
F 3 "~" H 4850 7100 50 0001 C CNN F 3 "~" H 4850 7100 50 0001 C CNN
1 4850 7100 1 4850 7100
-1 0 0 1 -1 0 0 1
@@ -3120,8 +3099,8 @@ $Comp
L Device:R R1 L Device:R R1
U 1 1 5F7756C9 U 1 1 5F7756C9
P 5150 6500 P 5150 6500
F 0 "R1" V 5050 6350 50 0000 L CNN F 0 "R1" V 5250 6350 50 0000 L CNN
F 1 "1M" V 5050 6550 50 0000 L CNN F 1 "1M" V 5250 6550 50 0000 L CNN
F 2 "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" V 5080 6500 50 0001 C CNN F 2 "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" V 5080 6500 50 0001 C CNN
F 3 "~" H 5150 6500 50 0001 C CNN F 3 "~" H 5150 6500 50 0001 C CNN
1 5150 6500 1 5150 6500
@@ -3314,7 +3293,7 @@ Wire Wire Line
Wire Wire Line Wire Wire Line
8500 4900 8050 4900 8500 4900 8050 4900
$Comp $Comp
L NES-CPU-11:10NES_CIC U10 L Motherboard:10NES_CIC U10
U 1 1 5DB00CBC U 1 1 5DB00CBC
P 7600 5300 P 7600 5300
F 0 "U10" H 7300 5850 50 0000 C CNN F 0 "U10" H 7300 5850 50 0000 C CNN
@@ -3741,25 +3720,8 @@ Wire Wire Line
10750 6850 10350 6850 10750 6850 10350 6850
Text Notes 3150 9100 0 50 ~ 10 Text Notes 3150 9100 0 50 ~ 10
FILTER CAPACITORS FILTER CAPACITORS
Wire Wire Line
13150 5750 13150 5950
Wire Wire Line
13150 5750 13950 5750
Wire Wire Line
13150 6350 13950 6350
Wire Wire Line Wire Wire Line
4850 6800 4850 7000 4850 6800 4850 7000
$Comp
L Device:Crystal_GND2 X2
U 1 1 5DB9934D
P 5000 6800
F 0 "X2" H 5000 7068 50 0000 C CNN
F 1 "4MHz" H 5000 6977 50 0000 C CNN
F 2 "Crystal:Resonator_muRata_CSTLSxxxG-3Pin_W8.0mm_H3.0mm" H 5000 6800 50 0001 C CNN
F 3 "~" H 5000 6800 50 0001 C CNN
1 5000 6800
1 0 0 -1
$EndComp
Wire Wire Line Wire Wire Line
5150 6800 5250 6800 5150 6800 5250 6800
Wire Wire Line Wire Wire Line
@@ -3768,13 +3730,7 @@ Text Label 5000 7150 1 50 ~ 0
GND GND
Wire Wire Line Wire Wire Line
3900 5300 4200 5300 3900 5300 4200 5300
Text Label 8000 6400 2 50 ~ 0 Text Label 7550 6700 0 50 ~ 0
GND
Text Label 8000 6500 2 50 ~ 0
GND
Text Label 8000 6600 2 50 ~ 0
GND
Text Label 8000 6700 2 50 ~ 0
GND GND
Wire Wire Line Wire Wire Line
5500 2950 6300 2950 5500 2950 6300 2950
@@ -3873,5 +3829,30 @@ Connection ~ 3400 8250
Wire Wire Line Wire Wire Line
3400 8250 3450 8250 3400 8250 3450 8250
Wire Wire Line Wire Wire Line
13150 6250 13150 6350 8000 6700 7550 6700
Wire Wire Line
13250 5750 13950 5750
$Comp
L Device:L_Core_Ferrite FC1
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P 3750 5300
F 0 "FC1" V 3975 5300 50 0000 C CNN
F 1 "39uH" V 3884 5300 50 0000 C CNN
F 2 "Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal" H 3750 5300 50 0001 C CNN
F 3 "~" H 3750 5300 50 0001 C CNN
1 3750 5300
0 -1 -1 0
$EndComp
Connection ~ 3900 5300
$Comp
L Device:Crystal_GND2 X2
U 1 1 5DB9934D
P 5000 6800
F 0 "X2" H 5000 7068 50 0000 C CNN
F 1 "4MHz" H 5000 6977 50 0000 C CNN
F 2 "Crystal:Resonator_muRata_CSTLSxxxG-3Pin_W8.0mm_H3.0mm" H 5000 6800 50 0001 C CNN
F 3 "~" H 5000 6800 50 0001 C CNN
1 5000 6800
1 0 0 -1
$EndComp
$EndSCHEMATC $EndSCHEMATC

3
Board Files/fp-lib-table Normal file
View File

@@ -0,0 +1,3 @@
(fp_lib_table
(lib (name NESRE)(type KiCad)(uri "C:/Users/Redherring32/Documents/OpenTendo.git/trunk/Component Footprints/NESRE.pretty")(options "")(descr ""))
)

120
Component Footprints/NESRE.pretty/EXP_Header.kicad_mod
View File

@@ -1,56 +1,76 @@
(module EXP_Header (layer F.Cu) (tedit 5D965D3D) (module EXP_Header (layer F.Cu) (tedit 60FDFAB4)
(fp_text reference P2-EXP1 (at -4.53 2.804) (layer F.SilkS) (fp_text reference P2 (at -1 11) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15))) (effects (font (size 1 1) (thickness 0.15)))
) )
(fp_text value SOCKET-50V (at -2.819 -4.188) (layer F.Fab) (fp_text value EXP-Connector (at -2.733 -3.875) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15))) (effects (font (size 1 1) (thickness 0.15)))
) )
(pad 4 thru_hole circle (at 7.615 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (fp_text user 1 (at -3 7) (layer F.SilkS)
(pad 5 thru_hole circle (at 10.155 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (effects (font (size 1 1) (thickness 0.15)))
(pad 6 thru_hole circle (at 12.7 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) )
(pad 1 thru_hole circle (at -0.008 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (fp_text user 48 (at -3 0) (layer F.SilkS)
(pad 2 thru_hole circle (at 2.532 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (effects (font (size 1 1) (thickness 0.15)))
(pad 3 thru_hole circle (at 5.076 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) )
(pad 8 thru_hole circle (at 17.775 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (fp_text user 24 (at 61 7) (layer F.SilkS)
(pad 9 thru_hole circle (at 20.318 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (effects (font (size 1 1) (thickness 0.15)))
(pad 14 thru_hole circle (at 33.016 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) )
(pad 13 thru_hole circle (at 30.476 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (fp_text user 25 (at 61 0) (layer F.SilkS)
(pad 20 thru_hole circle (at 48.254 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (effects (font (size 1 1) (thickness 0.15)))
(pad 23 thru_hole circle (at 55.878 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) )
(pad 12 thru_hole circle (at 27.937 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (fp_line (start 69.52 9.5) (end 69.52 -3) (layer F.SilkS) (width 0.12))
(pad 21 thru_hole circle (at 50.798 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (fp_line (start -11.1 9.49) (end -11.1 -3.01) (layer F.SilkS) (width 0.12))
(pad 22 thru_hole circle (at 53.338 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (fp_line (start -11.1 -3.01) (end 69.52 -3) (layer F.SilkS) (width 0.12))
(pad 17 thru_hole circle (at 40.64 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (fp_line (start 69.52 9.5) (end -11.1 9.49) (layer F.SilkS) (width 0.12))
(pad 10 thru_hole circle (at 22.858 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (fp_poly (pts (xy 69.52 -3) (xy 66.52 -3) (xy 69.52 0)) (layer F.SilkS) (width 0.1))
(pad 16 thru_hole circle (at 38.095 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (fp_poly (pts (xy -11.1 -3.01) (xy -11.1 -0.01) (xy -8.1 -3.01)) (layer F.SilkS) (width 0.1))
(pad 18 thru_hole circle (at 43.175 6.501) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 48 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 19 thru_hole circle (at 45.715 6.503) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 47 thru_hole circle (at 2.54 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 24 thru_hole circle (at 58.416 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 46 thru_hole circle (at 5.08 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 11 thru_hole circle (at 25.397 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 7 thru_hole circle (at 15.235 6.498) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 15 thru_hole circle (at 35.555 6.498) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 25 thru_hole circle (at 58.421 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 26 thru_hole circle (at 55.883 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 27 thru_hole circle (at 53.343 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 28 thru_hole circle (at 50.803 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 29 thru_hole circle (at 48.259 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 30 thru_hole circle (at 45.72 0.003) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 31 thru_hole circle (at 43.18 0.001) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 32 thru_hole circle (at 40.645 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 33 thru_hole circle (at 38.1 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 34 thru_hole circle (at 35.56 -0.002) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 35 thru_hole circle (at 33.021 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 36 thru_hole circle (at 30.481 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 37 thru_hole circle (at 27.942 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 38 thru_hole circle (at 25.402 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 39 thru_hole circle (at 22.863 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 40 thru_hole circle (at 20.323 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 41 thru_hole circle (at 17.78 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 42 thru_hole circle (at 15.24 -0.002) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 43 thru_hole circle (at 12.705 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 44 thru_hole circle (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 45 thru_hole circle (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 45 thru_hole circle (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 46 thru_hole circle (at 5.081 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 44 thru_hole circle (at 10.16 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 47 thru_hole circle (at 2.537 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 43 thru_hole circle (at 12.7 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 48 thru_hole circle (at -0.003 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)) (pad 42 thru_hole circle (at 15.24 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 41 thru_hole circle (at 17.78 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 40 thru_hole circle (at 20.32 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 39 thru_hole circle (at 22.86 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 38 thru_hole circle (at 25.4 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 37 thru_hole circle (at 27.94 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 36 thru_hole circle (at 30.48 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 35 thru_hole circle (at 33.02 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 34 thru_hole circle (at 35.56 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 33 thru_hole circle (at 38.1 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 32 thru_hole circle (at 40.64 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 31 thru_hole circle (at 43.18 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 30 thru_hole circle (at 45.72 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 29 thru_hole circle (at 48.26 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 28 thru_hole circle (at 50.8 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 27 thru_hole circle (at 53.34 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 26 thru_hole circle (at 55.88 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 25 thru_hole circle (at 58.42 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 1 thru_hole circle (at 0 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at 2.54 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at 5.08 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 4 thru_hole circle (at 7.62 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 5 thru_hole circle (at 10.16 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 6 thru_hole circle (at 12.7 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 7 thru_hole circle (at 15.24 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 8 thru_hole circle (at 17.78 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 9 thru_hole circle (at 20.32 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 10 thru_hole circle (at 22.86 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 11 thru_hole circle (at 25.4 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 12 thru_hole circle (at 27.94 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 13 thru_hole circle (at 30.48 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 14 thru_hole circle (at 33.02 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 15 thru_hole circle (at 35.56 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 16 thru_hole circle (at 38.1 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 17 thru_hole circle (at 40.64 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 18 thru_hole circle (at 43.18 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 19 thru_hole circle (at 45.72 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 20 thru_hole circle (at 48.26 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 21 thru_hole circle (at 50.8 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 22 thru_hole circle (at 53.34 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 23 thru_hole circle (at 55.88 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad 24 thru_hole circle (at 58.42 6.5) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
(pad "" thru_hole circle (at -3.5 3.25) (size 3.5 3.5) (drill 3.5) (layers *.Cu *.Mask))
(pad "" thru_hole circle (at 61.72 3.25) (size 2.5 2.5) (drill 2.5) (layers *.Cu *.Mask))
) )

24
Component Footprints/NESRE.pretty/Mod_RF.kicad_mod
View File

@@ -1,17 +1,17 @@
(module Mod_RF (layer F.Cu) (tedit 5DF56B32) (module Mod_RF (layer F.Cu) (tedit 5FF8DCCF)
(fp_text reference REF** (at 0 0.5) (layer F.SilkS) (fp_text reference P3 (at 0.314 5.086) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15))) (effects (font (size 1 1) (thickness 0.15)))
) )
(fp_text value Mod_RF (at 0 -0.5) (layer F.Fab) (fp_text value "MOD RF" (at 6.224 -1.314) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15))) (effects (font (size 1 1) (thickness 0.15)))
) )
(pad 1 thru_hole circle (at 0 3) (size 3 3) (drill 1.5) (layers *.Cu *.Mask)) (pad 6 thru_hole oval (at 22.344 -2.275 90) (size 4.25 9.25) (drill oval 1.16 5.62) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at 4 3) (size 3 3) (drill 1.5) (layers *.Cu *.Mask)) (pad 6 thru_hole oval (at 22.344 16.575 90) (size 4.25 9.25) (drill oval 1.16 5.62) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at 8 3) (size 3 3) (drill 1.5) (layers *.Cu *.Mask)) (pad 6 thru_hole oval (at -6.23 15.9) (size 4.25 9.25) (drill oval 1.16 5.12) (layers *.Cu *.Mask))
(pad 4 thru_hole circle (at 12 3) (size 3 3) (drill 1.5) (layers *.Cu *.Mask)) (pad 6 thru_hole oval (at -6.23 5.1) (size 4.25 9.25) (drill oval 1.16 5.12) (layers *.Cu *.Mask))
(pad 5 thru_hole circle (at 16 3) (size 3 3) (drill 1.5) (layers *.Cu *.Mask)) (pad 5 thru_hole circle (at 16 2.156) (size 3 3) (drill 1.5) (layers *.Cu *.Mask))
(pad 6 thru_hole oval (at -5.2 6) (size 4.25 9.25) (drill oval 1.16 4.18) (layers *.Cu *.Mask)) (pad 4 thru_hole circle (at 12 2.156) (size 3 3) (drill 1.5) (layers *.Cu *.Mask))
(pad 7 thru_hole oval (at -5.25 16.75) (size 4.25 9.25) (drill oval 1.16 4.18) (layers *.Cu *.Mask)) (pad 3 thru_hole circle (at 8 2.156) (size 3 3) (drill 1.5) (layers *.Cu *.Mask))
(pad 8 thru_hole oval (at 24.134 16.575 90) (size 4.25 9.25) (drill oval 1.16 4.18) (layers *.Cu *.Mask)) (pad 2 thru_hole circle (at 4 2.156) (size 3 3) (drill 1.5) (layers *.Cu *.Mask))
(pad 9 thru_hole oval (at 24.134 -2.275 90) (size 4.25 9.25) (drill oval 1.16 4.18) (layers *.Cu *.Mask)) (pad 1 thru_hole circle (at 0 2.156) (size 3 3) (drill 1.5) (layers *.Cu *.Mask))
) )

148
Component Footprints/NESRE.pretty/NES_Edge_Connector.kicad_mod
View File

@@ -1,80 +1,80 @@
(module NES_Edge_Connector (layer F.Cu) (tedit 5D96B83E) (module NES_Edge_Connector (layer F.Cu) (tedit 5DAD00C1)
(fp_text reference P1-72EDGE1 (at 0 0.5) (layer F.SilkS) (fp_text reference P1 (at 13.525 -0.025) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15))) (effects (font (size 1 1) (thickness 0.15)))
) )
(fp_text value CONN-NES-CARTRIDGE (at 0 -0.5) (layer F.Fab) (fp_text value "72-Pin Connector" (at 13.725 -0.825) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15))) (effects (font (size 1 1) (thickness 0.15)))
) )
(pad 37 smd rect (at 106.25 6.25) (size 3 9) (layers B.Cu B.Paste B.Mask))
(pad 28 smd rect (at 103.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 39 smd rect (at 100.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 40 smd rect (at 98.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 41 smd rect (at 95.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 52 smd rect (at 68.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 55 smd rect (at 60.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 68 smd rect (at 28.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 65 smd rect (at 35.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 61 smd rect (at 45.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 54 smd rect (at 63.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 60 smd rect (at 48.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 63 smd rect (at 40.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 59 smd rect (at 50.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 64 smd rect (at 38.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 66 smd rect (at 33.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 53 smd rect (at 65.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 62 smd rect (at 43.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 67 smd rect (at 30.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 57 smd rect (at 55.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 58 smd rect (at 53.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 56 smd rect (at 58.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 69 smd rect (at 25.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 70 smd rect (at 23.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 71 smd rect (at 20.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 72 smd rect (at 17.75 6.25) (size 3 9) (layers B.Cu B.Paste B.Mask))
(pad 47 smd rect (at 80.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 48 smd rect (at 78.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 50 smd rect (at 73.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 49 smd rect (at 75.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 51 smd rect (at 70.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 46 smd rect (at 83.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 42 smd rect (at 93.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 43 smd rect (at 90.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 44 smd rect (at 88.25 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 45 smd rect (at 85.75 6.25) (size 2 9) (layers B.Cu B.Paste B.Mask))
(pad 36 smd rect (at 106.25 6.25) (size 3 9) (layers F.Cu F.Paste F.Mask))
(pad 35 smd rect (at 103.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 34 smd rect (at 100.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 33 smd rect (at 98.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 32 smd rect (at 95.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 31 smd rect (at 93.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 30 smd rect (at 90.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 29 smd rect (at 88.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 28 smd rect (at 85.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 27 smd rect (at 83.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 26 smd rect (at 80.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 25 smd rect (at 78.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 24 smd rect (at 75.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 23 smd rect (at 73.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 22 smd rect (at 70.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 21 smd rect (at 68.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 20 smd rect (at 65.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 19 smd rect (at 63.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 18 smd rect (at 60.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 17 smd rect (at 58.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 16 smd rect (at 55.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 15 smd rect (at 53.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 14 smd rect (at 50.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 13 smd rect (at 48.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 12 smd rect (at 45.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 11 smd rect (at 43.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 10 smd rect (at 40.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 9 smd rect (at 38.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 8 smd rect (at 35.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 7 smd rect (at 33.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 6 smd rect (at 30.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at 28.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at 25.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at 23.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at 20.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 1 smd rect (at 17.75 6.25) (size 3 9) (layers F.Cu F.Paste F.Mask)) (pad 1 smd rect (at 17.75 6.25) (size 3 9) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at 20.75 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at 23.25 6.25) (size 2 9) (layers F.Cu F.Paste F.Mask))
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) )

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# Open 'Tendo # Open 'Tendo
An Open-Source HardWare (OSHW) recreation of the original 1985 Front-Loading NES motherboard. An Open-Source HardWare (OSHW) recreation of the original 1985 Front-Loading NES motherboard.
## Note on RGB and HDMI:
Neither RGB nor HDMI video output were or are a goal of the OpenTendo project, the goal was/is documentation and preservation, and the project was an exercise in reverse engineering. As such "improved" video outputs will not be added to OpenTendo.
NESRGB and Hi-Def NES can be installed as normal, but will not be incorporated into the OpenTendo PCB
## Repository Structure: ## Repository Structure:
* Board Files: Contains all files necessary to open the project in KiCad, as well as the schematic and schematic symbols * Board Files: Contains all files necessary to open the project in KiCad, as well as the schematic and schematic symbols
* Component Footprints: Contains a library of all the custom footprints used on the board * Component Footprints: Contains a library of all the custom footprints used on the board
* Schematics: Contains schematics for the OEM frontloading NES board revisions, some schematics represent more than one revision
The files required to order PCBs can be found under releases. The files required to order PCBs can be found under releases.
@@ -18,11 +26,11 @@ The files required to order PCBs can be found under releases.
* 1.6mm thickness * 1.6mm thickness
* HASL surface finish * HASL or ENiG surface finish
* And any color you want! * And any color you want!
![Board Front](https://i.imgur.com/nQP6BoM.jpg) ![Board Front](https://i.imgur.com/yBy1h27.jpeg)
The design is as true to the original board as possible, with subtle changes where needed to compensate for outdated/unsourcable parts, The design is as true to the original board as possible, with subtle changes where needed to compensate for outdated/unsourcable parts,
as well as some improvements. (Expansion audio enabled, and other minor changes) as well as some improvements. (Expansion audio enabled, and other minor changes)
@@ -31,7 +39,7 @@ Since this project is open-source you may do as you like with it, whether that i
I am not in any way affiliated with Nintendo, I'm just doing this in my free time as a stepping stone into further Reverse Engineering work. I am not in any way affiliated with Nintendo, I'm just doing this in my free time as a stepping stone into further Reverse Engineering work.
*Note:* At this point in time, any and all motherboards will require the use of an original CPU[1], and PPU[1] to function. *Note:* At this point in time, any and all motherboards will require the use of an original CPU[1], and PPU[2] to function.
These are the only two parts that are custom and have no available replacement, the rest can be replaced with modern, and or easily available parts. These are the only two parts that are custom and have no available replacement, the rest can be replaced with modern, and or easily available parts.
@@ -57,7 +65,7 @@ the TAPR Open Hardware License (www.tapr.org/OHL)
*=Lockster=* -Helping me tremendously along the way, keeping me from going insane, and cleaning up/helping with the final schematic. *=Lockster=* -Helping me tremendously along the way, keeping me from going insane, and cleaning up/helping with the final schematic.
*Krzysiobal* -Putting together the NES-CPU-11 schematic that my schematic is largely built upon. *Krzysiobal* -Putting together the NES-CPU-11 schematic that my schematic is largely referrenced against.
And to all of the awesome people in the NES scene, I wouldn't have been able to do this without the awesome work that some very clever people did before I got here. And to all of the awesome people in the NES scene, I wouldn't have been able to do this without the awesome work that some very clever people did before I got here.

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(sym_lib_table
(lib (name Motherboard)(type Legacy)(uri "C:/Users/Redherring32/Documents/OpenTendo.git/trunk/Board Files/Motherboard.lib")(options "")(descr ""))
)